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Emulator Operation
J
UMPER SETTINGS
The following table lists jumper setting that the are easily configured by the user. See
Figure 2-3 for the jumper locations.
T
2-1. J
ABLE
UMPER SETTINGS
Jumper Pin
Position
J1
N/A
Out (Default)
J2
N/A
Out (Default)
J3
1-2
Out (Default)
J4
1-2
Out (Default)
J6
1-3
In (Default)
J6
2-4
In (Default)
J6
5-7
In
J6
4-6
In
J7
N/A
Open (Default)
J8
1-2
In (Default)
J8
1-2
Out
JP1
1-2
In
JP1
1-2
Out (Default)
JP2
1-2
In (Default)
JP2
1-2
Out
JP3
1-2
In
JP3
1-2
Out (Default)
JP4
1-2
In (Default)
JP4
1-2
Out
2–10
Description
OTP programming adapter pins
OTP programming adapter pins
Reserved for data memory (do not use)
Reserved for external memory (do not use)
ICE chip is powered by the emulator's adjustable
regulator
Target is powered by emulator's adjustable
regulator
ICE chip is powered by a programmable regulator
(The programmable regulator is currently not
supported . Contact ZiLOG customer support to see if
the programmable regulator has been released .)
Target is not powered by emulator
connection on page 2-2 for more information)
Do not Jumper, jumping these pins will short port
4 pin 3 VCC! These two pins are used as a
connector for the port 4 pin 3 IR LED.
Connects Ports 4 pin 3 to target
Disconnects ports 4 pin 3 from target
Disable Vbo
Enable Vbo
AVDD to VDD core
Target board will supply power to AVDD (a 40 pin
part is being emulated)
A 28 pin part is being emulated
VCC_I isolates from AVDD (use internal filter)
Cap's to AVDD
N/A
Set-Up and Installation
(See Emulator
UM005100-IRR0400
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