Xm_Vatp_Tx0/1_Fifo; Xm_Vatp_Rx0/1_Fifo - Dynamic Engineering PMC-XM-DIFF User Manual

'0', there is less data in the FIFO than specified in the control register.
Receive FIFO Full: When read as a '1', the corresponding receive FIFO is full. When
read as a '0', there is room for at least one more word in the FIFO.
INT_STAT: When read as a '1', the corresponding interrupt is active (VINT0 for channel
0 or VINT1 for channel 1). When read as a '0', the interrupt is not active.

XM_VATP_TX0/1_FIFO

[0x0410, 0x0428] TX FIFO Port (read/write)
Data Bit
31-0
FIGURE 18
Data written to this address is written into the transmit FIFO as long as the FIFO is not
full. When this address is read a data-word is read from the transmit FIFO. When the
FIFO becomes empty, the last data-word that was in the FIFO will be returned.

XM_VATP_RX0/1_FIFO

[0x0414, 0x042C] RX FIFO Port (read/write)
Data Bit
31-0
FIGURE 19
Data written to this address is written into the receive FIFO as long as the FIFO is not
full. When this address is read a data-word is read from the receive FIFO. When the
FIFO becomes empty, the last data-word that was in the FIFO will be returned.
TX FIFO Port
Description
FIFO Data 31-0
PMC-XM VIRTEX (ATP) CHANNEL TX FIFO PORT
RX FIFO Port
Description
FIFO Data 31-0
PMC-XM VIRTEX (ATP) CHANNEL RX FIFO PORT
Embedded Solutions
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