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Related Manuals for Dynamic Engineering PMC-4U-CACI
Summary of Contents for Dynamic Engineering PMC-4U-CACI
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Page 1: Serial Data Interface
DYNAMIC ENGINEERING 435 Park Dr., Ben Lomond, Calif. 95005 831-336-8891 Fax 831-336-3840 sales@dyneng.com www.dyneng.com Est. 1988 User Manual PMC-4U-CACI Quad UART - Dual Synchronous Serial Data Interface PMC Module Revision OR Corresponding Hardware: Revision 01... - Page 2 PMC-4U Quad UART - Dual Synchronous Serial Data Interface PMC Module Dynamic Engineering 435 Park Drive Ben Lomond, CA 95005 831-336-8891 831-336-3840 FAX ©2001 by Dynamic Engineering. Trademarks and registered trademarks are owned by their respective manufactures. Manual Revision OR. Revised July 2, 2001. This document contains information of proprietary interest to Dynamic Engineering.
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Page 3: Table Of Contents
Table of Contents PRODUCT DESCRIPTION THEORY OF OPERATION ADDRESS MAP PROGRAMMING REGISTER DEFINITIONS PMC4U_BASE PMC4U_STAT PMC4U_MSK PMC4U_SCC_IVEC PMC4U_DIR_TERM PMC4U_SW_IN PMC4U_SCC_A_CNTL PMC4U_SCC_A_DATA PMC4U_SCC_B_CNTL PMC4U_SCC_B_DATA PMC4U_UART_A PMC4U_UART_B PMC4U_UART_C PMC4U_UART_D PMC4U_IRUPT/PMC4U_IRUPT_CLR Interrupts Loop-back PMC PCI PN1 INTERFACE PIN ASSIGNMENT PMC PCI PN2 INTERFACE PIN ASSIGNMENT PMC-4U FRONT PANEL IO PIN ASSIGNMENT PMC PN4 USER INTERFACE PIN ASSIGNMENT APPLICATIONS GUIDE... - Page 4 Interfacing CONSTRUCTION AND RELIABILITY THERMAL CONSIDERATIONS WARRANTY AND REPAIR SERVICE POLICY OUT OF WARRANTY REPAIRS FOR SERVICE CONTACT: SPECIFICATIONS ORDER INFORMATION SCHEMATICS Hardware and Software Design • Manufacturing Services P a g e...
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Page 5: Hardware And Software Design • Manufacturing Services P A G E
List of Figures FIGURE 1 PMC-4U BLOCK DIAGRAM FIGURE 2 PMC-4U INTERNAL ADDRESS MAP FIGURE 3 PMC-4U UART ADDRESS MAP FIGURE 4 PMC-4U BASE CONTROL REGISTER BIT MAP FIGURE 5 PMC-4U TX CONTROL REGISTER BIT MAP FIGURE 6 PMC-4U INTERRUPT MASK REGISTER BIT MAP FIGURE 7 PMC-4U DIRECTION TERMINATION CONTROL BIT MAP FIGURE 8... -
Page 6: Product Description
Product Description PMC-4U-CACI is part of the PMC Module family of modular I/O components by Dynamic Engineering. The PMC-4U is capable of providing multiple serial protocols both synchronous and asynchronous with a wide range of baud rates. The CACI interface uses an RS-423 driver, an RS-422 driver, and an RS-422 receiver for each UART channel. - Page 7 An EXAR XR16C854 implements the UART interface. This quad UART device is compatible with the industry standard 16550 UART, but is equipped with 128 byte FIFOs, independent Tx and Rx FIFO counters, automatic hardware/software flow control, and many other enhanced features.
- Page 8 There is also a master interrupt enable that can be set to gate the interrupt onto the PCI bus. The interrupt status is still available in a status register even when the master interrupt enable is off. This facilitates polled operation of interrupt conditions.
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Page 9: Theory Of Operation
Theory of Operation The PMC-4U is designed for transferring data from one point to another with a variety of serial protocols. The PMC-4U features a Xilinx FPGA. The FPGA contains the general control and status registers as well as the interface to the quad UART, SCC, and IO drivers and receivers. -
Page 10: Address Map
Address Map REGISTER OFFSET FUNCTION PMC4U_BASE PMC4U_STAT PMC4U_MSK PMC4U_SCC_IVEC PMC4U_DIR_TERM PMC4U_SW_IN PMC4U_SCC_A_CNTL PMC4U_SCC_A_DATA PMC4U_SCC_B_CNTL PMC4U_SCC_B_DATA PMC4U_UART_A PMC4U_UART_B PMC4U_UART_C PMC4U_UART_D PMC4U_IRUPT PMC4U_IRUPT_CLR FIGURE 2 Each UART channel has a number of registers associated with it. These register offsets and their general functions are given in figure 3. For details of the bits and functions of each register consult the documentation for the XR16C854. - Page 11 REGISTER OFFSET PMC4U_UART_DATA PMC4U_UART_IEN PMC4U_UART_ISTAT PMC4U_UART_FCNTL PMC4U_UART_LCNTL PMC4U_UART_MCNTL PMC4U_UART_LSTAT PMC4U_UART_MSTAT PMC4U_UART_SPAD UART baud rate register defines (enabled when *LCNTL bit-7 = 1) PMC4U_UART_DLL PMC4U_UART_DLM UART enhanced register offsets (enabled when *LCNTL = 0xbf) PMC4U_UART_FTC PMC4U_UART_FEAT PMC4U_UART_ENF PMC4U_UART_XON1 PMC4U_UART_XON2 PMC4U_UART_XOFF1 PMC4U_UART_XOFF2 UART EMS registers (enabled when feature control bit-6 = 1) PMC4U_UART_EMS FIGURE 3...
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Page 12: Programming
Programming Programming the PMC-4U requires only the ability to read and write data from the host. The base address is determined by the PMC Carrier board. The base address refers to the first user address for the slot in which the PMC is installed. -
Page 13: Register Definitions
Register Definitions PMC4U_BASE [0X00] PMC-4U Control Register Port read/write DATA BIT 31-22 21-20 15-0 FIGURE 4 All bits are active high and are reset on power-up or reset command. Test mode select is used to enable different drivers and receivers to allow thorough testing of the IO circuitry. - Page 14 SCC Tx A OUT_4 (188) SCC Rx A AUX_IN_0 (enhanced hysteresis 188) SCC Rx Clk AUX_IN_1 (enhanced hysteresis 188) SCC RTS A AUX_OUT_0 (open drain) SCC Tx B IO_15 (RS422) SCC Rx B IO_13 (RS422) When test mode select is “10” the following changes are made (if a signal is not listed here, its connection remains the same): Signal Function Driver/Receiver...
- Page 15 UART Tx C OUT_6 (RS423) UART Rx C IN_6 (RS232) UART Tx D OUT_7 (RS423) UART Rx D IN_7 (RS232) Master interrupt enable when ‘1’ gates all interrupts through to the PCI host. When ‘0’ the interrupts can be used for status without interrupting the host.
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Page 16: Pmc4U_Stat
PMC4U_STAT [0X04] PMC-4U Status Port read only DATA BIT 31-2 FIGURE 5 Interrupt out indicates that an interrupt is asserted on the PCI bus. Interrupt status indicates that an interrupt condition exists, however if the master interrupt enable is not asserted, then the interrupt will not be asserted on the PCI bus. -
Page 17: Pmc4U_Scc_Ivec
PMC4U_SCC_IVEC [0X0C] PMC-4U SCC Interrupt Acknowledge/Vector Read A read from this address causes the SCC interrupt acknowledge signal to be asserted. If an interrupt condition exists in the SCC, it will respond by placing an interrupt vector on the local data bus. This vector is specified by the user and, depending on the state set in the SCC registers, may contain status information about the cause of the interrupt. -
Page 18: Pmc4U_Sw_In
Parallel termination resistors are supplied on each differential pair along with a switch to allow the user to select which lines are terminated and where. In some systems it will make sense to terminate the lines in the cable and in others it will make sense to use the onboard terminations. CONTROL CORRESPONDING IO BITS TERM0... -
Page 19: Pmc4U_Scc_A_Cntl
PMC4U_SCC_A_CNTL [0X18] PMC-4U SCC Channel A Control Register read/write This address is used to access all of the channel A registers. In order to access a register other than this base register, the register number is first written to this address. A subsequent read or write will read from or write to the desired register. -
Page 20: Pmc4U_Uart_A
PMC4U_UART_A [0X40] PMC-4U UART A Base Address This is the base address for the eight register addresses associated with UART A. Figure 3 gives an overview of these registers and their functions. For more details on the access and functions of these registers see the XR16C854 documentation. -
Page 21: Pmc4U_Irupt/Pmc4U_Irupt_Clr
PMC4U_IRUPT/PMC4U_IRUPT_CLR [0XE0] PMC-4U Interrupt Latch read status/write clear DATA BIT FIGURE 9 The bits in this register indicate that an interrupt has been received from the corresponding device. These bits are latched and once set will remain set until a one is written to the bit to be cleared. INTERRUPT STATUS DESCRIPTION SCC interrupt... -
Page 22: Interrupts
Interrupts PMC-4U interrupts are treated as auto-vectored. When the software enters into an exception handler to deal with a PMC-4U interrupt the software must read the interrupt register to determine the cause(s) of the interrupt, change the interrupt mask, process accordingly to clear the interrupt condition, and then clear the associated bit in the interrupt register. -
Page 23: Loop-Back
Loop-back The Engineering kit has reference software, which includes external loop- back tests for the SCC and the UART. These tests require an external cable with the following pins connected. SIGNAL OUTPUT U_TxA+ PIN-11 U_TxA- PIN-45 U_TxB+ PIN-12 U_TxB- PIN-46 U_TxC+ PIN-13 U_TxC-... -
Page 24: Pmc Pci Pn1 Interface Pin Assignment
PMC PCI Pn1 Interface Pin Assignment The figure below gives the pin assignments for the PMC Module PCI Pn1 Interface on the PMC-4U-IO. See the User Manual for your carrier board for more information. Unused pins may be assigned by the specification and not needed by this design. -
Page 25: Pmc Pci Pn2 Interface Pin Assignment
PMC PCI Pn2 Interface Pin Assignment The figure below gives the pin assignments for the PMC Module PCI Pn2 Interface on the PMC-4U-IO. See the User Manual for your carrier board for more information. Unused pins may be assigned by the specification and not needed by this design. -
Page 26: Pmc-4U Front Panel Io Pin Assignment
PMC-4U Front Panel IO Pin Assignment The figure below gives the pin assignments for the PMC Module IO Interface on the PMC-4U. Also, see the User Manual for your carrier board for more information. GND* is a plane which is tied to GND through a 1206 0Ω... -
Page 27: Pmc Pn4 User Interface Pin Assignment
PMC Pn4 User Interface Pin Assignment The figure provides the pin assignments for the PMC-4U Module routed to Pn4. Also, see the User Manual for your carrier board for more information. IO_0+ (UART Rx A) IO_1+ IO_2+ (UART Rx B) IO_3+ IO_4+ (UART Rx C) IO_5+... -
Page 28: Applications Guide
Applications Guide Interfacing The pin-out tables are displayed with the pins in the same relative order as the actual connectors. The pin definitions are defined with noise immunity in mind. The pairs are chosen to match standard SCSI II/III cable pairing to allow a low cost commercial cable to be used for the interface. -
Page 29: Construction And Reliability
Construction and Reliability PMC Modules were conceived and engineered for rugged industrial environments. The PMC-4U is constructed out of 0.062 inch thick FR4 material. Through hole and surface mounting of components are used. IC sockets use gold plated screw machine pins. High insertion and removal forces are required, which assists in the retention of components. -
Page 30: Warranty And Repair
Warranty and Repair Dynamic Engineering warrants this product to be free from defects in workmanship and materials under normal use and service and in its original, unmodified condition, for a period of one year from the time of purchase. If the product is found to be defective within the terms of this warranty, Dynamic Engineering's sole responsibility shall be to repair, or at Dynamic Engineering's sole option to replace, the defective product. -
Page 31: Service Policy
Service Policy Before returning a product for repair, verify as well as possible that the suspected unit is at fault. Then call the Customer Service Department for a RETURN MATERIAL AUTHORIZATION (RMA) number. Carefully package the unit, in the original shipping carton if this is available, and ship prepaid and insured with the RMA number clearly written on the outside of the package. -
Page 32: Specifications
Specifications Host Interface: PCI Mezzanine Card Serial Interfaces: Four UART channels each with an RS422 driver and receiver and an RS423 driver. One synchronous channel with Mil. Std. 188- 114A Type 1 enhanced hysteresis receivers for clock and data, a 188 driver for Tx data, and an open drain PTT interface on the RTS line. -
Page 33: Order Information
Order Information PMC-4U Eng Kit–PMC-4U Note: The Engineering Kit is strongly recommended for first time PMC-4U buys. Schematics Schematics are provided as part of the engineering kit for customer reference only. This information was current at the time the printed circuit board was last revised.
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