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Dynamic Engineering PMC-PARALLEL-TTL User Manual

Digital parallel interface
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DYNAMIC ENGINEERING
150 DuBois St. Suite 3, Santa Cruz, Ca 95060
831-457-8891
Fax 831-457-4793
http://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
PMC-PARALLEL-TTL
Digital Parallel Interface
PMC Module
Revision A1
Corresponding Hardware: Revision 1
10-2007-0101
FLASH 0101
Embedded Solutions
Page 1

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  • Page 1 DYNAMIC ENGINEERING 150 DuBois St. Suite 3, Santa Cruz, Ca 95060 831-457-8891 Fax 831-457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual PMC-PARALLEL-TTL Digital Parallel Interface PMC Module Revision A1 Corresponding Hardware: Revision 1 10-2007-0101 FLASH 0101 Embedded Solutions Page 1...
  • Page 2 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to make improvements or changes in the product described in this document at any time and without notice.

  • Page 3: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION THEORY OF OPERATION ADDRESS MAP PROGRAMMING Register Definitions pmcparttl_BASE pmcparttl_ID pmcparttl_STATUS pmcparttl_DirL pmcparttl_DirU pmcparttl_DatL pmcparttl_DatU pmcparttl_DatLreg pmcparttl_DatUreg pmcparttl_COSclk pmcparttl_RisLreg pmcparttl_RisUreg pmcparttl_FallLreg pmcparttl_FallUreg pmcparttl_IntRisLreg pmcparttl_IntRisUreg pmcparttl_IntFallLreg pmcparttl_IntFallUreg pmcparttl_IntRisLstat pmcparttl_IntRisUstat pmcparttl_IntRisLstat pmcparttl_IntRisUstat PMC MODULE LOGIC INTERFACE PIN ASSIGNMENT PMC MODULE LOGIC INTERFACE PIN ASSIGNMENT PMC MODULE FRONT PANEL IO INTERFACE PIN ASSIGNMENT PMC MODULE BACKPLANE IO INTERFACE PIN ASSIGNMENT...
  • Page 4 APPLICATIONS GUIDE Interfacing Construction and Reliability Thermal Considerations Service Policy Out of Warranty Repairs SPECIFICATIONS ORDER INFORMATION Embedded Solutions Page 4...
  • Page 5 PMC-PARALLEL-TTL REAR VIEW FIGURE 2 PMC-PARALLEL-TTL BLOCK DIAGRAM FIGURE 3 PMC-PARALLEL-TTL INTERNAL ADDRESS MAP FIGURE 4 PMC-PARALLEL-TTL CONTROL PORT 0 BIT MAP FIGURE 5 PMC-PARALLEL-TTL ID AND SWITCH BIT MAP FIGURE 6 PMC-PARALLEL-TTL STATUS PORT BIT MAP FIGURE 7 PMC-PARALLEL-TTL DIRECTION LOWER BIT MAP...

  • Page 6: Product Description

    Usually the choice is based on other system constraints as both the PMC and IP can provide the IO you require. Dynamic Engineering would be happy to assist in your decision regarding architecture and other trade-offs with the PMC / IP decision.
  • Page 7 The multiple packs also allow for parallel combinations to create more options of specific pull-up values. For custom models with additional pull-ups or alternate values please contact Dynamic Engineering. The two columns of pull-up resistor locations are visible on the rear of the card.
  • Page 8 => to prevent updates from conflicting with existing software. The FLASH on the current boards will be able to be updated to use the new features in most cases. PMC-PARALLEL-TTL is part of the PMC Module family of modular I/O components. The PMC-PARALLEL-TTL conforms to the PMC standard. This guarantees compatibility with multiple PMC Carrier boards.

  • Page 9: Theory Of Operation

    Theory of Operation The PMC-PARALLEL-TTL can be used for multiple purposes with applications in telecommunications, control, sensors, IO, test; anywhere multiple independent IO are useful. The PMC-PARALLEL-TTL features a Xilinx FPGA, and high current LVTH driver devices. The FPGA contains the PCI interface and control required for the parallel interface.
  • Page 10 IO registers is written to. The custom pulse will be more accurate for delay and duration than a SW timing solution. The number of accesses to the card can be reduced as well having the effect of greater through-put. Please contact Dynamic Engineering with your requirements.

  • Page 11: Address Map

    The map is presented with the #define style to allow cutting and pasting into many compilers “include” files. The host system will search the PCI bus to find the assets installed during power-on initialization. The VendorId = 0x10EE and the CardId = 0x2C for the PMC-Parallel-TTL. Embedded Solutions Page 11...

  • Page 12: Programming

    PCI interface [BAR0]. The offsets in the address table are relative to the system assigned BAR0 base address. The next step is to initialize the PMC-Parallel-TTL. If the basic mode of direct read and write operations is to be used then the default settings can be used except for setting the master output enable and the direction bits corresponding to the channels to transmit on.

  • Page 13: Register Definitions

    Master Interrupt Enable Figure 4 PMC-PARALLEL-TTL Control port 0 Bit Map This is the base control register for the PMC Parallel TTL. The features common to all channels are controlled from this port. Unused bits are reserved for additional new features.

  • Page 14: Pmcparttl_Id

    DIP switch Figure 5 PMC-PARALLEL-TTL ID and Switch Bit Map The DIP Switch is labeled for bit number and ‘1’ ‘0’ in the silk screen. The DIP Switch can be read from this port and used to determine which PMC Parallel TTL is which in a system with multiple cards installed.

  • Page 15: Pmcparttl_Status

    Figure 6 PMC-PARALLEL-TTL Status Port Bit Map Local Interrupt for the base design this bit is the same as the Intforce bit – unmasked. PLL SDAT - The PLL serial data read-back is through this bit. Reserved for future use.

  • Page 16: Pmcparttl_Dirl

    DIR31-0 Figure 7 PMC-PARALLEL-TTL Direction Lower Bit Map The lower 32 bits of the parallel port direction are controlled with this port. When reset this port is cleared 0x00000000. All IO are set to read [inputs]. To use one or more of the IO for outputs;...

  • Page 17: Pmcparttl_Datl

    [$14 Data IO Port read/write] DATA BIT DESCRIPTION 31-0 Data IO 31-0 Figure 9 PMC-PARALLEL-TTL Data IO Lower Bit Map pmcparttl_DatU [$18 Data IO Port read/write] DATA BIT DESCRIPTION 31-0 Data IO 63-32 Figure 10 PMC-PARALLEL-TTL Data IO Upper Bit Map This port is really a combined Data Output port and a Data Input port.

  • Page 18: Pmcparttl_Datlreg

    [$1C Data Reg Port read only] DATA BIT DESCRIPTION 31-0 Data IO 31-0 Figure 11 PMC-PARALLEL-TTL Data Reg Lower Bit Map pmcparttl_DatUreg [$20 Data Reg Port read only] DATA BIT DESCRIPTION 31-0 Data IO 63-32 Figure 12 PMC-PARALLEL-TTL Data Reg Upper Bit Map Data written to the Data IO registers can be read back through this port.

  • Page 19: Pmcparttl_Cosclk

    DIVISOR Figure 13 PMC-PARALLEL-TTL COS Clk Control Bit Map Data Out 0 Enable when set and the corresponding Direction bit is set will drive the COS clock out on Data bit 0. An oscilloscope can be used to verify the frequency setting that is programmed with the COSclk register.

  • Page 20: Pmcparttl_Rislreg

    $2C Rising Lower Control Register Port read/write DATA BIT DESCRIPTION 31-0 Rising 31-0 Figure 14 PMC-PARALLEL-TTL Rising Lower Bit Map pmcparttl_RisUreg $30 Rising Upper Control Register Port read/write DATA BIT DESCRIPTION 31-0 Rising 63-32 Figure 15 PMC-PARALLEL-TTL Rising Upper Bit Map The Rising control register bits correspond to the input data bits.

  • Page 21: Pmcparttl_Falllreg

    $34 Rising Lower Control Register Port read/write DATA BIT DESCRIPTION 31-0 Falling 31-0 Figure 16 PMC-PARALLEL-TTL Falling Lower Bit Map pmcparttl_FallUreg $38 Rising Upper Control Register Port read/write DATA BIT DESCRIPTION 31-0 Falling 63-32 Figure 17 PMC-PARALLEL-TTL Falling Upper Bit Map The Falling control register bits correspond to the input data bits.

  • Page 22: Pmcparttl_Intrislreg

    $3C Rising Interrupt Lower Control Register Port read/write DATA BIT DESCRIPTION 31-0 Rising Int En 31-0 Figure 18 PMC-PARALLEL-TTL Int rising Lower Bit Map pmcparttl_IntRisUreg $40 Rising Interrupt Upper Control Register Port read/write DATA BIT DESCRIPTION 31-0 Rising Int En 63-32...

  • Page 23: Pmcparttl_Intfalllreg

    $44 Falling Interrupt Lower Control Register Port read/write DATA BIT DESCRIPTION 31-0 Falling Int En 31-0 Figure 20 PMC-PARALLEL-TTL Int Falling Lower Bit Map pmcparttl_IntFallUreg $48 Falling Interrupt Upper Control Register Port read/write DATA BIT DESCRIPTION 31-0 Falling Int En 63-32...

  • Page 24: Pmcparttl_Intrislstat

    $4C Rising Status Lower Control Register Port read/write DATA BIT DESCRIPTION 31-0 Rising COS bits 31-0 Figure 22 PMC-PARALLEL-TTL Rising COS Status Lower pmcparttl_IntRisUstat $50 Rising Status Upper Control Register Port read/write DATA BIT DESCRIPTION 31-0 Rising COS bits 63-32...

  • Page 25: Pmcparttl_Intrislstat

    $54 Falling Status Lower Control Register Port read/write DATA BIT DESCRIPTION 31-0 Falling COS Status bits 31-0 Figure 24 PMC-PARALLEL-TTL Falling COS Status Lower pmcparttl_IntRisUstat $58 Falling Status Upper Control Register Port read/write DATA BIT DESCRIPTION 31-0 Falling COS Status bits 63-32...

  • Page 26: Pmc Module Logic Interface Pin Assignment

    The figure below gives the pin assignments for the PMC Module PCI Pn1 Interface on the PMC-Parallel-TTL. See the User Manual for your carrier board for more information. Unused pins may be assigned by the specification and not needed by this design.

  • Page 27: Pmc Module Logic Interface Pin Assignment

    The figure below gives the pin assignments for the PMC Module PCI Pn2 Interface on the PMC-Parallel-TTL. See the User Manual for your carrier board for more information. Unused pins may be assigned by the specification and not needed by this design.

  • Page 28: Pmc Module Front Panel Io Interface Pin Assignment

    PMC Module Front Panel IO Interface Pin Assignment The figure below gives the pin assignments for the PMC Module IO Interface on the PMC-Parallel-TTL. Installed for –FP and –FRP models. Also see the User Manual for your carrier board for more information.

  • Page 29: Pmc Module Backplane Io Interface Pin Assignment

    PMC Module Backplane IO Interface Pin Assignment The figure below gives the pin assignments for the PMC Module IO Interface on the PMC-Parallel-TTL and routed to Pn4. Pn4 installed for –RP and –FRP models. Also see the User Manual for your carrier board for more information.
  • Page 30 Keep cables short. Flat cables, even with alternate ground lines, are not suitable for long distances. The PMC-Parallel-TTL has transorbs for input protection. The connector is pinned out for a standard SCSI II/III cable to be used. It is suggested that this standard cable be used for most of the cable run.
  • Page 31 Construction and Reliability PMC Modules were conceived and engineered for rugged industrial environments. The PMC-Parallel-TTL is constructed out of 0.062 inch thick high temperature ROHS compliant FR4 material. The traces are matched length from the FPGA ball to the IO pin. The options for front panel and rear panel are isolated with series resistor packs to eliminate bus stubs when one of the connectors is not in use.
  • Page 32 Thermal Considerations The PMC-PARALLEL-TTL design consists of CMOS circuits. The power dissipation due to internal circuitry is very low. It is possible to create a higher power dissipation with the externally connected logic. If more than one Watt is required to be dissipated due to external loading then forced air cooling is recommended.

  • Page 33: Service Policy

    For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty.

  • Page 34: Specifications

    Specifications Logic Interface: PMC Logic Interface [PCI] 32/33 Digital Parallel IO: 64 discrete IO channels. Each has a separate enable to control output. Inputs are maskable and always available. CLK rates supported: Osc, PLL, PCI, External reference rates coupled with 12 bit divider to allow user programmed sample rate for COS.

  • Page 35: Order Information

    -TS to add thumbscrew option – standard is latch block -3V to change from 5V IO reference to 3.3V IO reference Related: PCI2PMC: PMC to PCI adapter to allow installation of PMC-Parallel-TTL into a PCI system. http://www.dyneng.com/pci2pmc.html HDEterm68: 68 position terminal block with two SCSI II/III connectors. PMC-Parallel- TTL compatible.

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