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Dynamic Engineering PMC-XM-DIFF User Manual

Interface module with re-configurable i/o logic rs-485 or lvds or mixed 34 differential pairs at bezel, 32 differential pairs at pn4
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DYNAMIC ENGINEERING
Interface Module with Re-configurable I/O logic
RS-485 or LVDS or mixed
34 Differential Pairs at Bezel
32 Differential Pairs at Pn4
150 DuBois, Suite C
Santa Cruz, CA 95060
(831) 457-8891 Fax (831) 457-4793
http://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
PMC-XM-DIFF
Revision A
Corresponding Hardware: Revision A
10-2007-0201
Corresponding Firmware: Revision A

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  • Page 1 DYNAMIC ENGINEERING 150 DuBois, Suite C Santa Cruz, CA 95060 (831) 457-8891 Fax (831) 457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual PMC-XM-DIFF Interface Module with Re-configurable I/O logic RS-485 or LVDS or mixed 34 Differential Pairs at Bezel 32 Differential Pairs at Pn4...
  • Page 2 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to...

  • Page 3: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION THEORY OF OPERATION PROGRAMMING ADDRESS MAP SPARTAN3 Register Definitions PMC_XM_BASE PMC_XM_USER_SWITCH XM_CHAN0/1_CNTRL XM_CHAN0/1_STATUS XM_CHAN0/1_WR/RD_DMA_PNTR XM_CHAN0/1_FIFO XM_CHAN0/1_TX_AMT_LVL XM_CHAN0/1_RX_AFL_LVL XM_CHAN0/1_TX/RX_FIFO_COUNT ADDRESS MAP: VIRTEX ATP DESIGN Register Definitions XM_VATP_BASE XM_VATP_STATUS XM_VATP_CHAN0/1_CNTRL XM_VATP_CHAN0/1_STATUS XM_VATP_TX0/1_FIFO XM_VATP_RX0/1_FIFO XM_VATP_TX0/1_DCOUNT XM_VATP_RX0/1_DCOUNT VIRTEX PIN OUT TRANSITION MODULE MECHANICAL DRAWING MEZZANINE MODULE CONNECTOR J1 Embedded Solutions...
  • Page 4 MEZZANINE MODULE CONNECTOR J2 APPLICATIONS GUIDE Interfacing Construction and Reliability Thermal Considerations WARRANTY AND REPAIR Service Policy Out of Warranty Repairs For Service Contact: SPECIFICATIONS ORDER INFORMATION Embedded Solutions Page 4 of 46...
  • Page 5 List of Figures FIGURE 1 PMC-XM BLOCK DIAGRAM FIGURE 2 PMC-XM SPARTAN3 XILINX ADDRESS MAP FIGURE 3 PMC-XM SPARTAN3 BASE CONTROL REGISTER FIGURE 4 PMC-XM SPARTAN3 USER SWITCH PORT FIGURE 5 PMC-XM SPARTAN3 STATUS PORT FIGURE 6 PMC-XM SPARTAN3 CHANNEL CONTROL REGISTER FIGURE 7 PMC-XM SPARTAN3 CHANNEL STATUS PORT FIGURE 8...

  • Page 6: Product Description

    Product Description The PMC-XM-DIFF features a Xilinx Spartan3-1500 676 pin FPGA to implement the PCI interface and two independent I/O channels each with a separate input and output scatter-gather DMA engine to move data to/from host memory over the local 32-bit 33 MHz PCI bus.
  • Page 7 user modified to do whatever you want. The package includes an auto design detection feature to automatically load menus corresponding to different designs loaded into the Virtex. The user can change the design number and use the generic driver to access new features added to the clients implementation.

  • Page 8: Theory Of Operation

    The transfers are independently enabled from the Channel Control Registers in the Spartan3. In the Virtex ATP design used by Dynamic Engineering to test the PMC-XM hardware, there are also four corresponding 4K x 32-bit FIFOs to buffer the bursted data.

  • Page 9: Programming

    To use DMA it will be necessary to acquire a block of non-paged memory that is accessible from the PCI bus in which to store chaining descriptor list entries. At Dynamic Engineering the PMC-XM-DIFF is tested in a Windows environment and we use the Dynamic Engineering Drivers to do the hardware accesses and manage the DMA’s.

  • Page 10: Address Map Spartan3

    The VendorId = 0x10EE and the CardId = 0x0024 for the PMC-XM. Interrupts are requested by the configuration space. PCIView and other third party utilities can be useful to see how your system is configured. Dynamic Engineering recommends using the Dynamic Engineering Drivers to take care of initialization and device registration.

  • Page 11: Register Definitions Pmc_Xm_Base

    Register Definitions PMC_XM_BASE [0x0000] Base Control Register (read/write) Base Control Register Data Bit Description 31-17 Spare Load Virtex 15-10 Spare Virtex Init Virtex Reset Virtex Flash Enable Slave Serial Mode Enable Virtex Program Init Virtex Program Select Flash Select Flash Control Force Interrupt Master Interrupt Enable FIGURE 3...
  • Page 12 Virtex Program Select: When this bit is ‘1’, the Virtex Flash is controlled by the Virtex Flash Enable bit. When this bit is ‘0’, the Virtex Flash is controlled by the Virtex done bit. Virtex Program Init: When this bit is set to ‘1’ it forces the Virtex to re-configure from the Flash Prom.

  • Page 13: Pmc_Xm_User_Switch

    PMC_XM_USER_SWITCH [0x0004] User Switch Port (read only) Dip-Switch Port Data Bit Description 31-16 Spare 15-8 Xilinx Design Revision Number Sw7-0 FIGURE 4 PMC-XM SPARTAN3 USER SWITCH PORT Sw7-0: The user switch is read through this read-only port. The bits are read as the lowest byte.
  • Page 14 PMC_XM_STATUS [0x0008] Status Register Read / Latch Clear Write Status Register Data Bit Description Interrupt Status 30-24 Spare Virtex Status 3 Virtex Status 2 Virtex Status 1 Virtex Status 0 19-10 Spare Virtex Init Status Virtex Configuration Done Spare Local Interrupt Active FIGURE 5 PMC-XM SPARTAN3 STATUS REGISTER Local Interrupt Active: When read as a ‘1’, a local interrupt condition is active.

  • Page 15: Xm_Chan0/1_Cntrl

    XM_CHAN0/1_CNTRL [0x0010, 0x0040] Channel Control Register (read/write] Control Register Data Bit Description 31-9 Spare DMA Read Arbitration Priority Enable DMA Write Arbitration Priority Enable Virtex Interrupt Enable Receive Enable Transmit Enable Force Interrupt Master Interrupt Enable DMA Read Enable DMA Write Enable FIFO Bypass RX FIFO Reset TX FIFO Reset...
  • Page 16 occur. This bit is useful for software development and debugging. Transmit Enable: When this bit is ‘1’, the transfer state machine is enabled to move data from the referenced channel’s transmit FIFO to the corresponding Virtex transmit FIFO. When this bit is ‘0’, the transmit transfer state machine is disabled. Receive Enable: When this bit is ‘1’, the transfer state machine is enabled to move data from the referenced channel’s Virtex receive FIFO to the corresponding local receive FIFO.

  • Page 17: Xm_Chan0/1_Status

    XM_CHAN0/1_STATUS [0x0014, 0x0044] Channel Status Read / Latch Clear Write Status Register Data Bit Description INT_STAT 30-18 Spare Virtex Interrupt Active Local Interrupt Active Read DMA Interrupt Active Write DMA Interrupt Active Read DMA Error Write DMA Error 11-8 Spare Receive FIFO Valid Receive FIFO Full Receive FIFO Almost Full...
  • Page 18 Receive FIFO Full: When read as a ‘1’, the corresponding receive FIFO is full. When read as a ‘0’, there is room for at least one more word in the FIFO. Receive FIFO Valid: When read as a ‘1’, there is valid receive data to read. When read as a ‘0’, there is no valid receive data.

  • Page 19: Xm_Chan0/1_Fifo

    XM_CHAN0/1_WR/RD_DMA_PNTR [0x0018, 0x001C, 0x0048, 0x004C] DMA Address Register (Write only) DMA Pointer Address Register Data Bit Description 31-0 First Chaining Descriptor Physical Address FIGURE 8 PMC-XM SPARTAN3 CHANNEL DMA POINTER REGISTER These write-only ports are used to initiate scatter-gather DMAs. When the physical address of the first chaining descriptor is written to one of these ports, the corresponding DMA engine reads three successive long words beginning at that address.

  • Page 20: Xm_Chan0/1_Tx_Amt_Lvl

    XM_CHAN0/1_TX_AMT_LVL [0x0024, 0x0054] TX Almost Empty Level Register (read/write) TX Almost Empty Level Register Data Bit Description 31-16 Spare 15-0 TX FIFO Almost Empty Level FIGURE 10 PMC-XM SPARTAN3 CHANNEL TX ALMOST EMPTY REGISTER This register specifies the level at which the transmit FIFO almost empty level will be asserted.

  • Page 21: Xm_Chan0/1_Tx/Rx_Fifo_Count

    XM_CHAN0/1_TX/RX_FIFO_COUNT [0x002C, 0x0030, 0x005C, 0x0060] TX/RX FIFO Data Count Port (read only) FIFO Data Count Data Bit Description 31-16 Spare 15-0 FIFO Data Words Stored FIGURE 12 PMC-XM SPARTAN3 CHANNEL TX/RX FIFO COUNT PORT These read-only register ports report the number of 32-bit data words in the corresponding transmit/receive FIFO and data pipeline (currently a maximum of 0x1000 for the transmit and 0x1003 for the receive).

  • Page 22: Address Map: Virtex Atp Design

    FIGURE 13 PMC-XM VIRTEX (ATP) XILINX ADDRESS MAP This address map is only valid for the ATP design supplied by Dynamic Engineering. The addresses are offset from the PCI address assigned to the card by the system PCI configuration utility.

  • Page 23: Register Definitions

    Register Definitions XM_VATP_BASE [0x0400] Base Control Register (read/write) Base Control Register Data Bit Description 31–20 Spare PLL SDAT Output PLL S2/Suspend PLL SCLK PLL Enable 15–9 Spare Reset DCM Force Interrupt 1 Master Interrupt 1 Enable Force Interrupt 0 Master Interrupt 0 Enable 3–0 LED 4–1 FIGURE 14...
  • Page 24 PLL SDAT Output: This is where the PLL data state is specified when data is being written to the PLL. When the PLL is driving the data line this bit must be set to a ‘1’. The PMC-XM has a PLL device which is programmed over an I C bus to produce the desired frequencies.

  • Page 25: Xm_Vatp_Status

    XM_VATP_STATUS [0x0404] Status Register (read only) Base Status Register Data Bit Description 31-20 Spare PLL SDAT Input Intstat1 Intstat0 DCM Locked 15-8 Design ID Design Rev. FIGURE 15 PMC-XM VIRTEX (ATP) BASE STATUS REGISTER Design ID/Rev.: These fields are read to determine which design and revision is programmed into the Virtex.

  • Page 26: Xm_Vatp_Chan0/1_Cntrl

    XM_VATP_CHAN0/1_CNTRL [0x0408, 0x0420] Channel Control Register (read/write) Channel Control Register Data Bit Description Receive FIFO Reset Transmit FIFO Reset 29-28 Spare 27-16 Receive FIFO Almost Full Level 15-4 Transmit FIFO Almost Empty Level Spare Force Interrupt Master Interrupt Enable FIFO Bypass FIGURE 16 PMC-XM VIRTEX (ATP) CHANNEL CONTROL REGISTER FIFO Bypass: When this bit is ‘1’, any data written to the transmit FIFO will be...

  • Page 27: Xm_Vatp_Chan0/1_Status

    XM_VATP_CHAN0/1_STATUS [0x040C, 0x0424] Channel Status Register (read only) Channel Status Register Data Bit Description 31-16 Spare INT_STAT 14-8 Spare Receive FIFO Full Receive FIFO Almost Full Receive FIFO Almost Empty Receive FIFO Empty Transmit FIFO Full Transmit FIFO Almost Full Transmit FIFO Almost Empty Transmit FIFO Empty FIGURE 17...

  • Page 28: Xm_Vatp_Tx0/1_Fifo

    ‘0’, there is less data in the FIFO than specified in the control register. Receive FIFO Full: When read as a ‘1’, the corresponding receive FIFO is full. When read as a ‘0’, there is room for at least one more word in the FIFO. INT_STAT: When read as a ‘1’, the corresponding interrupt is active (VINT0 for channel 0 or VINT1 for channel 1).

  • Page 29: Xm_Vatp_Tx0/1_Dcount

    XM_VATP_TX0/1_DCOUNT [0x0418, 0x0430] TX FIFO Data Count Port (read only) TX FIFO Data Count Data Bit Description 31-12 Spare 11-0 FIFO Data Words Stored FIGURE 20 PMC-XM VIRTEX (ATP) CHANNEL TX FIFO COUNT PORT These read-only register ports report the number of 32-bit data words in the corresponding transmit FIFO (currently a maximum of 0xFFF).

  • Page 30: Virtex Pin Out

    Virtex Pin Out The Virtex FPGA pin definitions are contained in the engineering kit and repeated here as a reference. The hardwired pins for power and ground are not shown. Signal Name Direction I/O Standard Input LVCMOS 3.3 V VCLK66 Input LVCMOS 3.3 V CLK66FB...
  • Page 31 VADD<0> Input LVCMOS 3.3 V VADD<1> Input LVCMOS 3.3 V VADD<2> Input LVCMOS 3.3 V VADD<3> Input LVCMOS 3.3 V VADD<4> Input LVCMOS 3.3 V VADD<5> Input LVCMOS 3.3 V VADD<6> Input LVCMOS 3.3 V VADD<7> Input LVCMOS 3.3 V Input LVCMOS 3.3 V Input...
  • Page 32 LED<0> AE18 Bidir LVCMOS 3.3 V LED<1> AF18 Bidir LVCMOS 3.3 V LED<2> AC19 Bidir LVCMOS 3.3 V LED<3> AF19 Bidir LVCMOS 3.3 V RX_SW_CTRL<0> Output LVCMOS 2.5 V RX_SW_CTRL<1> Output LVCMOS 2.5 V RX_SW_CTRL<2> Output LVCMOS 2.5 V RX_SW_CTRL<3> Output LVCMOS 2.5 V MISO...
  • Page 33 TX_DAC_I<5> Output LVCMOS 3.3 V TX_DAC_I<6> AB22 Output LVCMOS 3.3 V TX_DAC_I<7> AC22 Output LVCMOS 3.3 V TX_DAC_I<8> AD22 Output LVCMOS 3.3 V TX_DAC_I<9> AF22 Output LVCMOS 3.3 V TX_DAC_Q<0> AA26 Output LVCMOS 3.3 V TX_DAC_Q<1> AD26 Output LVCMOS 3.3 V TX_DAC_Q<2>...
  • Page 34 RX_ADC_I<11> Input LVCMOS 3.3 V RX_ADC_I<12> Input LVCMOS 3.3 V RX_ADC_I<13> Input LVCMOS 3.3 V RX_ADC_Q<0> Input LVCMOS 3.3 V RX_ADC_Q<1> Input LVCMOS 3.3 V RX_ADC_Q<2> Input LVCMOS 3.3 V RX_ADC_Q<3> Input LVCMOS 3.3 V RX_ADC_Q<4> Input LVCMOS 3.3 V RX_ADC_Q<5>...
  • Page 35 QDR_IN<13> Input HSTL_I_DCI 1.8 V QDR_IN<14> Input HSTL_I_DCI 1.8 V QDR_IN<15> Input HSTL_I_DCI 1.8 V QDR_IN<16> Input HSTL_I_DCI 1.8 V QDR_IN<17> Input HSTL_I_DCI 1.8 V QDR_IN<18> Input HSTL_I_DCI 1.8 V QDR_IN<19> Input HSTL_I_DCI 1.8 V QDR_IN<20> Input HSTL_I_DCI 1.8 V QDR_IN<21>...
  • Page 36 QDR_OUT<19> Output HSTL_I 1.8 V QDR_OUT<20> Output HSTL_I 1.8 V QDR_OUT<21> Output HSTL_I 1.8 V QDR_OUT<22> Output HSTL_I 1.8 V QDR_OUT<23> Output HSTL_I 1.8 V QDR_OUT<24> Output HSTL_I 1.8 V QDR_OUT<25> Output HSTL_I 1.8 V QDR_OUT<26> Output HSTL_I 1.8 V QDR_OUT<27>...
  • Page 37 PLL_SDAT Bidir LVCMOS 3.3 V PLL_CLKA Input LVCMOS 3.3 V PLL_CLKB Input LVCMOS 3.3 V D7_0 AF20 Output LVCMOS 3.3 V D7_1 AB20 Output LVCMOS 3.3 V D7_2 Output LVCMOS 3.3 V Embedded Solutions Page 37 of 46...
  • Page 38 D9_0 Output LVCMOS 2.5 V D9_1 Output LVCMOS 2.5 V D9_2 Output LVCMOS 2.5 V D9_3 Output LVCMOS 2.5 V D9_4 Output LVCMOS 2.5 V D9_5 Output LVCMOS 2.5 V D9_6 Output LVCMOS 2.5 V D9_7 Output LVCMOS 2.5 V D9_8 Output LVCMOS 2.5 V...

  • Page 39: Transition Module Mechanical Drawing

    Transition Module Mechanical Drawing Embedded Solutions Page 39 of 46...

  • Page 40: Mezzanine Module Connector J1

    Mezzanine Module Connector J1 RX_SW_CTRL3 D9_24 RX_SW_CTRL0 D9_25 RX_SW_CTRL2 D9_26 RX_SW_CTRL1 ADC_CLK0 ADC_REFSEL D9_27 ADC_MUXSEL D9_28 ADC_PDWN0 D9_29 ADC_OEB0 D9_30 ADC_OTR0 RX_ADC_I13 D9_23 RX_ADC_I12 D9_22 RX_ADC_I11 D9_21 RX_ADC_I10 D9_20 RX_ADC_I9 D9_19 RX_ADC_I8 D9_18 RX_ADC_I7 D9_17 RX_ADC_I6 D9_16 RX_ADC_I5 D9_15 RX_ADC_I4 D9_14 RX_ADC_I3 D9_13...

  • Page 41: Mezzanine Module Connector J2

    Mezzanine Module Connector J2 D7_2 DAC_MUXSEL TX_DAC_I9 TX_DAC_I8 TX_DAC_I7 TX_DAC_I6 TX_DAC_I5 TX_DAC_I4 TX_DAC_I3 TX_DAC_I2 TX_DAC_I1 TX_DAC_I0 DAC_WRT0 DAC_CLK0 D7_1 GPIO4 GPIO3 GPIO2 GPIO1 D7_0 DAC_CLK1 DAC_WRT1 TX_DAC_Q9 TX_DAC_Q8 TX_DAC_Q7 TX_DAC_Q6 TX_DAC_Q5 TX_DAC_Q4 TX_DAC_Q3 TX_DAC_Q2 TX_DAC_Q1 TX_DAC_Q0 DAC_PDWN filtered +5v filtered +5v filtered +5v filtered +5v filtered +5v...

  • Page 42: Applications Guide

    Applications Guide Interfacing Some general interfacing guidelines are presented below. Do not hesitate to contact the factory if you need more assistance. Proper ESD handling procedures must be followed when handling the PMC-XM. The card is shipped in an anti-static, shielded bag. The card should remain in the bag until ready for use.

  • Page 43: Construction And Reliability

    Construction and Reliability PMC Modules were conceived and engineered for rugged industrial environments. The PMC-XM is constructed out of 0.062-inch thick FR4 material. Surface-mount components are used. The PMC connectors are rated at 1 Amp per pin, 100 insertion cycles minimum. These connectors make consistent, correct insertion easy and reliable.

  • Page 44: Warranty And Repair

    For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty.

  • Page 45: Specifications

    Specifications Host Interface: 33 MHz/32-bit PCI Mezzanine Card Access types: Configuration and Memory space utilized Clock rates supported: 33 MHz. PMC, 33 MHz data transfer between Spartan3 and Virtex Local 40 MHz oscillator for PLL reference to provide two programmable frequencies Memory FIFO memory is provided to support DMA Four 4K x 32-bit FIFOs on Spartan3...

  • Page 46: Order Information

    Board-level schematics (PDF) and Sample Virtex design (VHDL) PMC-XM-Eng-2 Engineering Kit for the PMC-XM Board-level schematics [PDF], Sample Virtex Design (VHDL), Software Drivers and Sample Test Application All information provided is Copyright Dynamic Engineering Embedded Solutions Page 46 of 46...

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