Xm_Vatp_Chan0/1_Cntrl - Dynamic Engineering PMC-XM-DIFF User Manual

XM_VATP_CHAN0/1_CNTRL

[0x0408, 0x0420] Channel Control Register (read/write)
Data Bit
29-28
27-16
15-4
FIGURE 16
FIFO Bypass: When this bit is '1', any data written to the transmit FIFO will be
transferred to the receive FIFO as long as there is room in the FIFO. This facilitates
FIFO loop-back testing. When this bit is '0', data written to the transmit FIFO will remain
in the FIFO until explicitly read.
Master Interrupt Enable: When this bit is '1', the corresponding interrupt is enabled
(VINT0 for channel 0 or VINT1 for channel 1). When this bit is '0', the interrupt is
disabled. This bit has a parallel function with the interrupt enable bits in the base
control register.
Force Interrupt: When this bit is '1', and the corresponding interrupt enable is set, that
interrupt will be asserted from the Virtex. This bit has a parallel function with the force
interrupt bits in the base control register.
Transmit FIFO Almost Empty Level: This field specifies the level at which the transmit
FIFO almost empty level will be asserted. When the number of data words in the
transmit FIFO is less than or equal to this count the almost empty status will be
asserted.
Receive FIFO Almost Full Level: This field specifies the level at which the receive FIFO
almost full level will be asserted. When the number of data words in the receive FIFO is
greater than or equal to this count the almost full status will be asserted.
Transmit/Receive FIFO Reset: When this bit is '1', the corresponding FIFO is placed in
a reset state. When this bit is '0', the FIFO will function normally.
Channel Control Register
31
30
3
2
1
0
PMC-XM VIRTEX (ATP) CHANNEL CONTROL REGISTER
Embedded Solutions
Description
Receive FIFO Reset
Transmit FIFO Reset
Spare
Receive FIFO Almost Full Level
Transmit FIFO Almost Empty Level
Spare
Force Interrupt
Master Interrupt Enable
FIFO Bypass
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