Xm_Vatp_Chan0/1_Status - Dynamic Engineering PMC-XM-DIFF User Manual

Interface module with re-configurable i/o logic rs-485 or lvds or mixed 34 differential pairs at bezel, 32 differential pairs at pn4
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XM_VATP_CHAN0/1_STATUS

[0x040C, 0x0424] Channel Status Register (read only)
Data Bit
31-16
14-8
FIGURE 17
Transmit FIFO Empty: When read as a '1', the corresponding transmit FIFO is empty.
When read as a '0', the FIFO has at least one word in it.
Transmit FIFO Almost Empty: When read as a '1', the corresponding transmit FIFO is
almost empty as determined by the almost empty field in the control register. When
read as a '0', there is more data in the FIFO than specified in the control register.
Transmit FIFO Almost Full: When read as a '1', the corresponding transmit FIFO is
almost full. The almost full level is hard-coded to 4080 words. When read as a '0',
there are less than this number of words in the FIFO.
Transmit FIFO Full: When read as a '1', the corresponding transmit FIFO is full. When
read as a '0', there is room for at least one more word in the FIFO.
Receive FIFO Empty: When read as a '1', the corresponding receive FIFO is empty.
When read as a '0', the FIFO has at least one word in it.
Receive FIFO Almost Empty: When read as a '1', the corresponding receive FIFO is
almost empty. The almost empty level is hard-coded to 16 words. When read as a '0',
there are more than this number of words in the FIFO.
Receive FIFO Almost Full: When read as a '1', the corresponding receive FIFO is
almost full as determined by the almost full field in the control register. When read as a
Channel Status Register
15
7
6
5
4
3
2
1
0
PMC-XM VIRTEX (ATP) CHANNEL STATUS REGISTER
Embedded Solutions
Description
Spare
INT_STAT
Spare
Receive FIFO Full
Receive FIFO Almost Full
Receive FIFO Almost Empty
Receive FIFO Empty
Transmit FIFO Full
Transmit FIFO Almost Full
Transmit FIFO Almost Empty
Transmit FIFO Empty
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