Dynamic Engineering PMC-XM-DIFF User Manual page 18

Receive FIFO Full: When read as a '1', the corresponding receive FIFO is full. When
read as a '0', there is room for at least one more word in the FIFO.
Receive FIFO Valid: When read as a '1', there is valid receive data to read. When read
as a '0', there is no valid receive data. There is a four-deep pipeline on the output of the
RX FIFO that will be filled before data is retained in the FIFO. Therefore even though
the FIFO is empty there may actually be up to four long-words of valid receive data.
This status bit indicates when there is valid data even though the FIFO is empty.
Write DMA Error: When read as a '1', a write DMA error has been detected. This will
occur if there is a target or master abort or if the direction bit in the next pointer of one of
the chaining descriptors is a one. When read as a '0', no error has occurred.
Read DMA Error: When read as a '1', a read DMA error has been detected. This will
occur if there is a target or master abort or if the direction bit in the next pointer of one of
the chaining descriptors is a zero. When read as a '0', no error has occurred.
Write DMA Interrupt Active: When read as a '1', a write DMA interrupt is latched. This
indicates that the scatter-gather list for the current write DMA has completed, but the
associated interrupt has yet to be completely processed. When read as a '0', no write
DMA interrupt is pending.
Read DMA Interrupt Active: When read as a '1', a read DMA interrupt is latched. This
indicates that the scatter-gather list for the current read DMA has completed, but the
associated interrupt has yet to be completely processed. When read as a '0', no read
DMA interrupt is pending
Local Interrupt Active: When read as a '1', a local interrupt condition is active for the
referenced channel. Currently, the only such condition is the Force Interrupt bit in the
Channel Control Register. A system interrupt will not occur unless the Master Interrupt
Enable bit in the Channel Control Register is also set. When read as a '0', no local
interrupt conditions are active.
Virtex Interrupt Active: When read as a '1', the corresponding Virtex interrupt (VINT0 for
channel 0 or VINT1 for channel 1) is active. A system interrupt will not occur unless the
Virtex Interrupt Enable in the Channel Control Register is set. When read as a '0', the
Virtex interrupt is inactive.
INT_STAT: When read as a '1', an enabled channel interrupt condition is active and a
system interrupt should be asserted. When read as a '0', no enabled channel interrupt
is active.
Embedded Solutions
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