General Wiring Restrictions; Resistance - Fujitsu MB86R12 Design Manualline

MB86R12 Application Note
DDR3 Interface PCB Design Guideline
4.2.

General wiring restrictions

This section describes the general wiring restrictions.
• It is recommended that signal wiring be designed to have the following characteristic impedance.
Single impedance: 50Ω±10%
Differential impedance: 100Ω±10%
• Signal wiring on power layer and GND layer should be sufficient width to guarantee the flow of
return current. (Signal line should be wired on the same power group or GND group. It must not cross
over other power and GND groups.)
• Please use parallel wiring for the positive and negative signals of the differential MCK_Group and
MDQSx_Group signals. In addition, also take care that the position and number of layer vias is the
same.
• The following groups must wire the same layer respectively, and the number of layer transfer vias
must become the same, too.
MDQS0_Group and MDQ0_Group
MDQS1_Group and MDQ1_Group
MDQS2_Group and MDQ2_Group
MDQS3_Group and MDQ3_Group
There are no restrictions to the number of layer transfer vias for other signals, but use a minimum
possible.
• When using meander wiring layouts for signal delay, crosstalk may occur and the delay value reduced,
therefore having wider spacing between wirings is recommended. The recommended wire spacing is
about five times the wiring width.
The recommended conditions and the simulation waveform which are described further on in this
document are valid under the above conditions.
If your design greatly differs from the above conditions, then please run a simulation on your wiring.
4.3.

Resistance

• Resistors described in this guideline should be generally selected from the E12 series.
E12 series: 10, 12, 15, 18, 22, 27, 33, 39, 47, 56, 68, 82
• The following resistance tolerance values should be used (according to the resistance type):
Terminal resistance: under ±5%
Divider resistance for VREF: under ±1%
FUJITSU SEMICONDUCTOR CONFIDENTIAL
Bevelled corners used in order to reduce signal reflections
Figure 4-1 Meander wiring
Wire spacing
5