Mode-Specific Guidelines - Dell EMC PowerEdge MX840c Installation And Service Manual

Configuration
Configuration 12
Configuration 13
Configuration 14
Configuration 15

Mode-specific guidelines

The configurations allowed depend on the memory mode selected in the System BIOS.
Table 11. Memory operating modes
Memory Operating Mode
Optimizer Mode
Mirror Mode
82 Installing and removing sled components
Description
42x 32GB RDIMMs, 6x
NVDIMM-Ns
24x 16GB RDIMMs, 12x
NVDIMM-Ns
24x 32GB RDIMMs, 12x
NVDIMM-Ns
36x 32GB RDIMMs, 12x
NVDIMM-Ns
Memory population rules
RDIMMs
Processor3 {C1, 2, 3, 4, 5, 6}
Processor4 {D1, 2, 3, 4, 5, 6}
Processor1 {A1, 2, 3, 4, 5, 6, 7, 8,
9},
Processor2 {B1, 2, 3, 4, 5, 6, 7, 8,
9}
Processor3 {C1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12}
Processor4 {D1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12}
Processor1 {A1, 2, 3, 4, 5, 6},
Processor2 {B1, 2, 3, 4, 5, 6},
Processor3 {C1, 2, 3, 4, 5, 6}
Processor4 {D1, 2, 3, 4, 5, 6}
Processor1 {A1, 2, 3, 4, 5, 6},
Processor2 {B1, 2, 3, 4, 5, 6},
Processor3 {C1, 2, 3, 4, 5, 6}
Processor4 {D1, 2, 3, 4, 5, 6}
Processor1 {A1, 2, 3, 4, 5, 6},
Processor2 {B1, 2, 3, 4, 5, 6},
Processor3 {C1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12}
Processor 4 {D1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12}
Description
The Optimizer Mode if enabled, the DRAM controllers operate
independently in the 64-bit mode and provide optimized memory
performance.
The Mirror Mode if enabled, the system maintains two identical
copies of data in memory, and the total available system memory is
one half of the total installed physical memory. Half of the installed
memory is used to mirror the active memory modules. This feature
provides maximum reliability and enables the system to continue
running even during a catastrophic memory failure by switching
over to the mirrored copy. The installation guidelines to enable
Mirror Mode require that the memory modules be identical in size,
NVDIMM-N
Processor1 {A10,11,12}
Processor2 {B10, 11, 12}
Processor1 {A7, 8, 9, 10, 11, 12},
Processor2 {B7, 8, 9, 10, 11, 12}
Processor1 {A7, 8, 9, 10, 11, 12},
Processor2 {B7, 8, 9, 10, 11, 12}
Processor1 {A7, 8, 9, 10, 11, 12},
Processor2 {B7, 8, 9, 10, 11, 12}