NXP Semiconductors S32K116 Reference Manual

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S32K1xx Series Reference Manual

Supports S32K116, S32K118, S32K142, S32K144, S32K146, and

S32K148

Document Number: S32K1XXRM

Rev. 4, 06/2017

Preliminary

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Summary of Contents for NXP Semiconductors S32K116

Page 1 S32K1xx Series Reference Manual Supports S32K116, S32K118, S32K142, S32K144, S32K146, and S32K148 Document Number: S32K1XXRM Rev. 4, 06/2017 Preliminary...
Page 2 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 3 Feature summary................................57 Block diagram................................60 Feature comparison...............................62 Applications.................................. 63 Module functional categories............................64 2.7.1 ARM Cortex-M4F Core Modules........................66 2.7.2 ARM Cortex-M0+ Core Modules........................66 2.7.3 System modules............................. 67 2.7.4 Memories and memory interfaces........................68 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 4 Functional description..............................79 Pad description................................80 Default pad state................................81 Signal Multiplexing sheet............................. 82 4.5.1 IO Signal Table ............................. 82 4.5.2 Input muxing table............................83 Pinout diagrams................................84 Chapter 5 Security Overview Introduction...................................85 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 5 Operational interference protection....................... 99 6.2.7 CRC................................101 6.2.8 Diversity of system resources........................101 Chapter 7 Core Overview ARM Cortex-M4F core configuration.......................... 103 7.1.1 Buses, interconnects, and interfaces......................104 7.1.2 System Tick Timer............................104 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 6 8.3.9 LMEM Parity and ECC Control Register (MCM_LMPECR)...............130 8.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR)..............130 8.3.11 LMEM Fault Address Register (MCM_LMFAR)..................132 8.3.12 LMEM Fault Attribute Register (MCM_LMFATR)..................133 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 7 Memory map and register definition..........................170 10.6.1 Pin Control Register n (PORT_PCRn)......................172 10.6.2 Global Pin Control Low Register (PORT_GPCLR)..................175 10.6.3 Global Pin Control High Register (PORT_GPCHR)..................175 10.6.4 Global Interrupt Control Low Register (PORT_GICLR)................176 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 8 11.3.1 GPIO register descriptions..........................186 11.4 Functional description..............................193 11.4.1 General-purpose input............................193 11.4.2 General-purpose output..........................193 Chapter 12 Crossbar Switch Lite (AXBS-Lite) 12.1 Chip-specific AXBS-Lite information..........................195 12.1.1 Crossbar Switch master assignments......................195 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 9 Region Descriptor 0, Word 2 (RGD0_WORD2)...................215 13.4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)...................218 13.4.9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)............219 13.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)............220 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 10 Direct Memory Access Multiplexer (DMAMUX) 15.1 Chip-specific DMAMUX information......................... 285 15.1.1 Number of channels ............................285 15.1.2 DMA transfers via TRGMUX trigger......................285 15.2 Introduction...................................286 15.2.1 Overview................................ 286 15.2.2 Features................................286 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 11 TCD initialization............................301 16.4.3 TCD structure..............................302 16.4.4 Reserved memory and bit fields........................302 16.4.5 DMA register descriptions..........................302 16.5 Functional description..............................360 16.5.1 eDMA basic data flow........................... 360 16.5.2 Fault reporting and handling.......................... 363 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 12 Chip-specific EWM information ..........................427 18.1.1 EWM_OUT signal configuration........................427 18.1.2 EWM Memory Map access..........................427 18.1.3 EWM low-power modes..........................427 18.2 Introduction...................................427 18.2.1 Features................................428 18.2.2 Modes of Operation............................428 18.2.3 Block Diagram............................... 429 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 13 Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 - EICHD1_WORD0)......448 19.3.5 Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)......450 19.4 Functional description..............................451 19.4.1 Error injection scenarios..........................451 Chapter 20 Error Reporting Module (ERM) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 14 21.2.2 Block diagram..............................465 21.3 Memory map and register definition..........................465 21.3.1 WDOG register descriptions.......................... 465 21.4 Functional description..............................472 21.4.1 Clock source..............................472 21.4.2 Watchdog refresh mechanism........................473 21.4.3 Configuring the Watchdog..........................475 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 15 CRC calculations............................487 22.4.3 Transpose feature............................488 22.4.4 CRC result complement..........................490 Chapter 23 Reset and Boot 23.1 Introduction...................................491 23.2 Reset....................................491 23.2.1 Power-on reset (POR)............................ 492 23.2.2 System reset sources............................492 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 16 High level clocking diagram............................515 25.3 Clock definitions................................516 25.4 Internal clocking requirements............................. 518 25.4.1 Clock divider values after reset........................521 25.4.2 HSRUN mode clocking..........................521 25.4.3 VLPR mode clocking.............................521 25.4.4 VLPR/VLPS mode entry..........................522 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 17 26.3.13 Slow IRC Configuration Register (SCG_SIRCCFG)..................558 26.3.14 Fast IRC Control Status Register (SCG_FIRCCSR)..................559 26.3.15 Fast IRC Divide Register (SCG_FIRCDIV)....................561 26.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................562 26.3.17 System PLL Control Status Register (SCG_SPLLCSR)................563 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 18 27.6.11 PCC LPSPI2 Register (PCC_LPSPI2)......................588 27.6.12 PCC PDB1 Register (PCC_PDB1)........................ 589 27.6.13 PCC CRC Register (PCC_CRC)........................591 27.6.14 PCC PDB0 Register (PCC_PDB0)........................ 592 27.6.15 PCC LPIT Register (PCC_LPIT)........................594 27.6.16 PCC FTM0 Register (PCC_FTM0)....................... 595 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 19 27.6.39 PCC FTM7 Register (PCC_FTM7)....................... 632 27.6.40 PCC CMP0 Register (PCC_CMP0).......................633 27.6.41 PCC QSPI Register (PCC_QSPI)........................635 27.6.42 PCC ENET Register (PCC_ENET)....................... 636 Chapter 28 Clock Monitoring Unit (CMU) 28.1 Introduction...................................639 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 20 Chip-specific LMEM information ..........................655 30.1.1 LMEM region description..........................655 30.1.2 LMEM SRAM sizes............................655 30.2 Introduction...................................655 30.2.1 Block Diagram............................... 655 30.2.2 Cache features..............................657 30.3 Memory Map/Register Definition..........................659 30.3.1 LMEM register descriptions.......................... 659 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 21 32.3 Modes of operation............................... 713 32.4 External signal description............................713 32.5 Functional description..............................713 32.5.1 Default configuration............................. 713 32.5.2 Speculative reads............................714 32.6 Initialization and application information........................715 Chapter 33 Flash Memory Module (FTFC) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 22 Flash operation in low-power modes......................757 33.5.5 Functional modes of operation........................758 33.5.6 Flash memory reads and ignored writes......................758 33.5.7 Read while write (RWW)..........................758 33.5.8 Flash program and erase..........................759 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 23 QuadSPI Modes of Operation........................843 34.2.4 Acronyms and Abbreviations.........................844 34.2.5 Glossary for QuadSPI module........................844 34.3 External Signal Description............................846 34.3.1 Driving External Signals..........................847 34.4 Memory Map and Register Definition..........................849 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 24 Reading Flash Data into the AHB Buffer...................... 932 34.10 Driving Flash Control Signals in Single and Dual Mode..................... 932 34.11 Serial Flash Devices..............................933 34.11.1 Example Sequences............................933 34.12 Sampling of Serial Flash Input Data..........................939 34.12.1 Basic Description............................939 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 25 Memory map and register descriptions.........................961 36.3.1 SMC Version ID Register (SMC_VERID)....................961 36.3.2 SMC Parameter Register (SMC_PARAM)....................962 36.3.3 Power Mode Protection register (SMC_PMPROT)..................963 36.3.4 Power Mode Control register (SMC_PMCTRL)...................965 36.3.5 Stop Control Register (SMC_STOPCTRL)....................967 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 26 PMC register descriptions..........................979 Chapter 38 ADC Configuration 38.1 Instantiation information...............................987 38.1.1 Number of ADC channels..........................987 38.1.2 ADC Connections/Channel Assignment......................988 38.2 Register implementation............................... 989 38.3 DMA Support on ADC..............................989 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 27 ADC Configuration Register 1 (CFG1)......................1012 39.4.4 ADC Configuration Register 2 (CFG2)......................1013 39.4.5 ADC Data Result Registers (RA - aRP)......................1014 39.4.6 Compare Value Registers (CV1 - CV2)......................1016 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 28 39.4.31 ADC Data Result Registers (RQ - RAF)....................... 1045 39.5 Functional description..............................1046 39.5.1 Clock select and divide control........................1046 39.5.2 Voltage reference selection..........................1047 39.5.3 Hardware trigger and channel selects......................1047 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 29 Continuous mode (#s 2A & 2B)........................1066 40.7.3 Sampled, Non-Filtered mode (#s 3A & 3B)....................1067 40.7.4 Sampled, Filtered mode (#s 4A & 4B)......................1069 40.7.5 Windowed mode (#s 5A & 5B)........................1071 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 30 PDB trigger interconnections with ADC and TRGMUX................1094 41.1.3 Back-to-back acknowledgement connections....................1094 41.1.4 Pulse-Out Enable Register Implementation....................1101 41.2 Introduction...................................1101 41.2.1 Features................................1101 41.2.2 Implementation.............................. 1102 41.2.3 Back-to-back acknowledgment connections....................1102 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 31 Pulse-Out's..............................1121 41.4.4 Updating the delay registers...........................1122 41.4.5 Interrupts................................ 1124 41.4.6 DMA................................1124 41.5 Application information..............................1124 41.5.1 Impact of using the prescaler and multiplication factor on timing resolution..........1124 Chapter 42 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 32 Functional Description..............................1201 42.5.1 Clock source..............................1201 42.5.2 Prescaler................................. 1201 42.5.3 Counter................................1202 42.5.4 Channel Modes.............................. 1208 42.5.5 Input Capture Mode............................1210 42.5.6 Output Compare mode........................... 1215 42.5.7 Edge-Aligned PWM (EPWM) mode......................1216 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 33 42.5.29 Reload Points..............................1284 42.5.30 Global Load..............................1287 42.5.31 Global time base (GTB)..........................1288 42.5.32 Channel trigger output........................... 1289 42.5.33 External Control of Channels Output......................1290 42.5.34 Dithering................................ 1290 42.6 Reset Overview................................1301 42.7 FTM Interrupts................................1303 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 34 Trigger Control for Timers..........................1327 43.5.4 Channel Chaining............................1328 43.5.5 Detailed timing...............................1328 Chapter 44 Low Power Timer (LPTMR) 44.1 Chip-specific LPTMR information..........................1341 44.1.1 Instantiation Information..........................1341 44.1.2 LPTMR pulse counter input options......................1341 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 35 Introduction...................................1355 45.2.1 Features................................1356 45.2.2 Modes of operation............................1356 45.2.3 RTC signal descriptions..........................1356 45.3 Register definition.................................1357 45.3.1 RTC register descriptions..........................1357 45.4 Functional description..............................1367 45.4.1 Power, clocking, and reset..........................1367 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 36 Master Mode..............................1397 46.4.3 Slave Mode..............................1402 46.4.4 Interrupts and DMA Requests........................1404 46.4.5 Peripheral Triggers............................1405 Chapter 47 Low Power Inter-Integrated Circuit (LPI2C) 47.1 Chip-specific LPI2C information..........................1407 47.1.1 Instantiation information..........................1407 47.2 Introduction...................................1408 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 37 48.3 Register definition.................................1469 48.3.1 LPUART register descriptions........................1469 48.4 Functional description..............................1494 48.4.1 Baud rate generation............................1494 48.4.2 Transmitter functional description......................... 1495 48.4.3 Receiver functional description........................1498 48.4.4 Additional LPUART functions........................1505 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 38 Interrupts and DMA Requests........................1545 49.4.6 Peripheral Triggers............................1545 49.5 Application Information..............................1545 49.5.1 UART Transmit............................. 1546 49.5.2 UART Receive............................... 1547 49.5.3 SPI Master..............................1548 49.5.4 SPI Slave................................ 1550 49.5.5 I2C Master..............................1552 49.5.6 I2S Master..............................1554 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 39 FlexCAN Memory Partition for CAN FD..................... 1641 50.4.5 FlexCAN message buffer memory map......................1642 50.4.6 Rx FIFO structure............................1645 50.5 Functional description..............................1647 50.5.1 Transmit process............................1648 50.5.2 Arbitration process............................1649 50.5.3 Receive process..............................1652 50.5.4 Matching process............................1655 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 40 Memory map and register definition..........................1708 51.4.1 I2S register descriptions..........................1708 51.5 Functional description..............................1738 51.5.1 SAI clocking..............................1738 51.5.2 SAI resets............................... 1740 51.5.3 Synchronous modes............................1740 51.5.4 Frame sync configuration..........................1741 51.5.5 Data FIFO..............................1742 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 41 52.5.14 Descriptor Individual Upper Address Register (ENET_IAUR)..............1779 52.5.15 Descriptor Individual Lower Address Register (ENET_IALR)..............1780 52.5.16 Descriptor Group Upper Address Register (ENET_GAUR)................. 1780 52.5.17 Descriptor Group Lower Address Register (ENET_GALR)................. 1781 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 42 52.5.44 Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127)..........1796 52.5.45 Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)........1796 52.5.46 Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)........1797 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 43 52.5.71 Reserved Statistic Register (ENET_RMON_R_RESVD_0)................. 1807 52.5.72 Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64)..............1807 52.5.73 Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127)........... 1808 52.5.74 Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255)........1808 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 44 Ethernet MAC frame formats........................1821 52.6.2 IP and higher layers frame format........................1824 52.6.3 IEEE 1588 message formats.......................... 1828 52.6.4 MAC receive..............................1832 52.6.5 MAC transmit..............................1838 52.6.6 Full-duplex flow control operation........................ 1842 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 45 IR codes................................1885 53.6 JTAG status and control registers..........................1886 53.6.1 MDM-AP Control Register..........................1887 53.6.2 MDM-AP Status Register..........................1888 53.7 Debug resets..................................1889 53.8 AHB-AP..................................1890 53.9 ITM....................................1890 53.10 Core trace connectivity..............................1891 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 46 Functional description..............................1901 54.5.1 JTAGC reset configuration..........................1901 54.5.2 IEEE 1149.1-2001 (JTAG) Test Access Port....................1901 54.5.3 TAP controller state machine.........................1901 54.5.4 JTAGC block instructions..........................1904 54.5.5 Boundary scan..............................1907 54.6 Initialization/Application information.......................... 1907 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 47 • Examples of these groupings are clocking, timers, and communication interfaces. • Each grouping includes chapters that provide a technical description of individual modules. 1.3 Module descriptions Each module chapter has two main parts: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 48 The example below shows chip-specific information that clarifies general module information presented later in the chapter. In this case, the chip-specific register reset values supercede the reset values that appear in the register diagram. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 49 1.3.2 Example: chip-specific information that refers to a different chapter The chip-specific information below refers to another chapter's chip-specific information. In this case, read both sets of chip-specific information before reading further in the chapter. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 50 • The page number on which each register is described • Register figures • Field-description tables • Associated text The register figures show the field structure using the conventions in the following figure. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 51 WARNING Warning notices inform readers about actions that could result in unwanted consequences, especially those that may cause bodily injury. 1.5.2 Numbering systems The following suffixes identify different numbering systems: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 52 • An active-high signal is deasserted when low (0). • An active-low signal is deasserted when high (1). In some cases, deasserted signals are described as negated. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 53 • Consider undefined locations in memory to be reserved. Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 54 Conventions S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 55 DSP and FPU support, with up to 2 MB Flash and up to 256 KB SRAM. Overview of device features: • 32-bit ARM Cortex-M4F core with FPU, up to 112 MHz (HSRUN) and 80 MHz (Normal RUN) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 56 1. This refers to region addressable by ARM CM4 Code bus and is used to cache code as well as data in this region. See S32K1xx_memory_map.xlsx for more details on cacheability of different regions. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 57 176-pin LQFP, 24*24 mm, 0.5 mm pitch 100-pin MAPBGA, 11*11 mm, 1 mm ball pitch Voltage range 2.7 V to 5.5 V Temperature range (T -40 °C to 125 °C Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 58 Cyclic redundancy check (CRC) 16- or 32-bit CRC with programmable generator polynomial Clocks System clock generator (SCG) OSC, FIRC, SIRC, PLL OSC, FIRC, SIRC Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 59 32-bit Low-power programmable 4 independent channels interrupt timer (LPIT) Real-time clock (RTC) Low-power timer (LPTMR) LPTMR 1-channel, 16-bit pulse counter or Periodic interrupt Communication Interfaces Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 60 ARM Core MPU, which would concurrently monitor only core-initiated memory accesses. In this document, the term MPU refers to NXP’s system MPU. 2.4 Block diagram The following figure shows block diagram of the S32K14x product series. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 61 S32K devices (see the "Feature Comparison" section in the RM) Figure 2-1. S32K14x product series block diagram The following figure shows block diagram of the S32K11x product series. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 62 The following figure summarizes the memory and package options for the S32K product series and demonstrates where this device fits within the overall series. All devices which share a common package are pin-to-pin compatible. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 63 4 Only for BSR Figure 2-3. S32K1xx product series comparison 2.6 Applications The S32K1xx product series are the ideal choices for general purpose automotive applications, which include but not limited to: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 64 TDM, and I2S) on S32K148 make it fit perfectly for Ethernet connected edge nodes in vehicle, and the audio streaming application. The S32K116 and S32K118 offer small packages: 5*5 mm 32 QFN, 7*7 mm 48 LQFP, and 10*10 mm 64 LQFP, which are suitable for broad range of size sensitive applications in vehicle, such as various sensor controllers.
Page 65 • Low-power Serial peripheral interface (LPSPI) • Low-power Inter-integrated circuit (LPI2C) • Low-power UART (LPUART) • Synchronous Audio Interface (SAI)/Integrated interchip sound (I2S) • FlexIO • FlexCAN Debug • JTAG Controller (JTAGC) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 66 • Serial Wire Viewer (SWV): A trace capability providing displays of reads, writes, exceptions, PC Samples and printf. • Supports 4 pin trace interface 2.7.2 ARM Cortex-M0+ Core Modules The following core modules are available on this device. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 67 Direct memory access multiplexer The DMAMUX selects from many DMA requests down to a smaller number for the (DMAMUX) DMA controller. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 68 It supports SDR and HyperRAM modes up to 4 and 8 bidirectional data lines respectively. Flash memory controller Manages the interface between the device and the on-chip flash memory. SRAM Internal system RAM. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 69 Compares two analog input voltages across the full range of the supply voltage. 8-bit digital-to-analog converters (DAC) 256-tap resistor ladder network which provides a selectable voltage reference for within CMP applications where a voltage reference is needed. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 70 • Hardware trigger generated on Timer Compare Real-time clock (RTC) • 32-bit seconds counter with 32-bit alarm • 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 71 Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 72 Module functional categories S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 73 In S32K11x on-chip RAM can be used in following applications: • Safety critical applications: SRAM_U can be used, which starts from 2000_0000 • Non-safety critical applications: SRAM_U along with 1 KB MTB can be used S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 74 3.4 Peripheral bridge (AIPS-Lite) memory map The peripheral memory map is accessible via a crossbar slave port. There are three regions associated with peripheral space, as shown in the following table. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 75 Table 3-2. Read-after-write sequence to guarantee required serialization of memory operations Step Action Write the peripheral register. Read the written peripheral register to verify the write. Continue with subsequent operations. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 76 1. The ARM Core ROM table is optionally required by ARM CoreSight debug infrastructure to discover the components on the chip. This ROM table has no any relationship with the MCU Boot ROM. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 77 A 32-bit read in the alias region returns either: • a value of 0x0000_0000 to indicate the target bit is clear • a value of 0x0000_0001 to indicate the target bit is set S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 78 Do not use bit banding for w1c status bits. CAUTION The S32K product series and the software drivers support bit- banding, but ARM no longer promotes its usage. Therefore, we recommend that bit-banding should not be used. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 79 Reference Manual. 4.2 Functional description The signal multiplexing architectural implementation is as shown in the following figure. GPIO Pad controls Functional Signal Padring Modules/ Multiplexing Peripherals Unit Figure 4-1. Signal Multiplexing S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 80 0: Enable internal pulldown resistor if pue is set 1: Enable internal pullup resistor if pue is set Enable input receiver Data coming out of the pad into the core S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 81 1. While in reset, the pin behavior is same apart from reset pin. Chip drives pad low via obe=1, pue=0, till reset sequence is complete to indicate reset to off-chip connected devices. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 82 • 000: Alternative 0 (Signal path disabled) • 001: Alternative 1 (GPIO) • 010: Alternative 2 (chip-specific) • 011: Alternative 3 (chip-specific) • 100: Alternative 4 (chip-specific) • 101: Alternative 5 (chip-specific) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 83 • GPIO-HD: General Purpose IO Pad that support high drive functionality NOTE If oscillator is enabled then enabling the GPIO or LPI2C function for EXTAL/XTAL pins can lead to device damage. This must be avoided by software. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 84 4.6 Pinout diagrams See IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual for pinout diagrams corresponding to available packages. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 85 FSEC[SEC] field. The MCU, in turn, confirms the security request and limits access to flash memory resources. During reset, the flash memory module initializes the FSEC register using data read from the security byte of the flash memory configuration field. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 86 • If the debugger has switched to SWD mode, the FTFC_FCSESTAT[EDB] bit is reset on POR. • If the debugger remains in JTAG mode, the FTFC_FCSESTAT[EDB] bit is reset on pin_reset if correct debugger disconnection takes place. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 87 Security use case examples 5.3.1 Secure boot: check bootloader for integrity and authenticity The following diagram illustrates a use case for detecting and preventing bootloader modification. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 88 • Part-by-part checking of flash memory ensures each part's integrity and authenticity before executing it. Critical parts of flash memory (for example, MCU configuration/IRQ table) are checked and then executed as soon as possible. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 89 This use case demonstrates how to prevent illegal messages sent by ECUs. • Random number generation and checking protect against replay attacks. • Encryption protects against eavesdropping. • Random number generation/checking and encryption ensure data integrity and authenticity. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 90 5.3.4 Component protection The replacement or modification of ECU <n> will change its unique ID and/or keys. This use case shows how both changes are detected. Figure 5-4. Component protection S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 91 3. Transfer data to CSEc memory (maximum 12 CAN messages of 8 bytes + 16-byte CMAC) 4. Trigger CSEc CMAC calculation/verification 5. CSEc triggers interrupt to core 6. Core reads processed message data S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 92 Before returning a device to NXP for failure analysis, the user must run the CMD_DBG_CHAL CMD_DBG_AUTH commands and ensure that all user keys are deleted. This is a mandatory step to enable failure analysis at NXP. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 93 4. CMD_BOOT_DEFINE to select the flavor of boot and size of data to validate in Pflash Then optionally reset the part to "auto calculate" and program the BOOT_MAC or the user loads the BOOT_MAC by external calculation. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 94 Security programming flow example (Secure Boot) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 95 FMEDA, including source of failure rates, failure modes, and assumptions during the analysis The S32K1xx series is a SafeAssure™ solution. For more information regarding functional safety at NXP, visit http://www.nxp.com/safeassure. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 96 ASIL-B safety integrity level. In general, safety integrity is achieved by using and applying S32K1xx safety features as described in the Safety Manual. The following diagram provides an overview of integrated S32K1xx architecture and safety features. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 97 In this document, the term MPU refers to NXP’s system MPU Feature Comparison. 2: See Memories and Memory Interfaces chapter in S32K14x Series Reference Manual: On-chip SRAM sizes table for Device specific sizes Figure 6-2. S32K1xx safety block diagram S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 98 • Power-on reset (POR) • Low-voltage detection (LVD) References: • Functional description: in this Reference Manual, see Power Management • Power supply monitoring in safety concept: see Safety Manual chapter S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 99 • prevent non-safety masters from interfering with the operation of the Safety Core • manage the concurrent execution of software with different (lower) ASIL A hierarchical memory protection scheme, which includes the following, protects against interference: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 100 The ARM M4 core version in this family does not integrate the ARM Core MPU, which would concurrently monitor only core-initiated memory accesses. In this document, the term MPU refers to NXP’s system MPU. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 101 • For cases of communication-channel redundancy for safety reasons, S32K14x offers redundant instances of communication peripherals: • Synchronous Serial Communication Controller (LPSPI) modules S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 102 • UART modules: support UART and LIN communication References: • Functional description: in this Reference Manual, see SIM, LPSPI, LPI2C, FlexIO, LPUART • Diversity of system resources in safety concept: see Safety Manual S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 103 Crossbar switch bus module Debug IEEE 1149.1 JTAG Debug Serial Wire Debug (SWD) ARM Real-Time Trace Interface Interrupts Nested Vectored NVIC Interrupt Controller (NVIC) Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 104 CORE_CLK is the only available source of reference timing. 7.1.3 Debug facilities This chip has extensive debug capabilities including run control and tracing capabilities. This is a standard ARM debug port that supports JTAG and SWD interfaces. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 105 The ARM documentation uses different terms than this document to distinguish between privilege levels. Table 7-3. Terms used If you see this term... it also means this term... Privileged Supervisor Unprivileged or user User S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 106 The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. The pin on which the NMI signal is multiplexed must be configured for the NMI function in order to generate the non-maskable interrupt request. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 107 Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR14 bitfield range is 20-23 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: • NVICISER1[26] • NVICICER1[26] • NVICISPR1[26] • NVICICPR1[26] S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 108 Interrupt for wake up LPI2C0 (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 LPUART (1) Async Interrupt in STOP1 (2) Sync Interrupt in STOP2 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 109 Refer to the S32K1xx_memory_map.xlsx attached to this document. Clocking — Clock Distribution Power Management — Power Management Transfers ARM Cortex M4 core ARM Cortex-M4 Technical Reference Manual - Private Peripheral Bus Private Peripheral Bus (PPB) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 110 Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control See IO Signal Description Input Multiplexing sheet(s) attached to the Reference Manual attached to this document for details. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 111 Miscellaneous Control Module (MCM) 8.1 Chip-specific MCM information The following table summarizes the chip-specific register reset values of this module for each chip in the product series. Table 8-1. MCM register reset values Register S32K116 S32K118 S32K142 S32K144 S32K146 S32K148...
Page 112 LMEM Fault Address Register (MCM_LMFAR) 0000_0000h 8.3.11/132 LMEM Fault Attribute Register (MCM_LMFATR) 0000_0000h 8.3.12/133 LMEM Fault Data High Register (MCM_LMFDHR) 0000_0000h 8.3.13/134 LMEM Fault Data Low Register (MCM_LMFDLR) 0000_0000h 8.3.14/134 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 113 This read-only field is reserved and always has the value 0. Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 114 Memory map/register descriptions MCM_PLAMC field descriptions (continued) Field Description A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 115 8.3.3 Core Platform Control Register (MCM_CPCR) CPCR defines the arbitration and protection schemes for the two system RAM arrays. Address: 0h base + Ch offset = Ch SRAMLAP SRAMUAP Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 116 Fixed priority. Backdoor has highest, processor has lowest This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 117 AXBS is not receiving halt request AXBS is receiving halt request HLT_FSM_ST AXBS Halt State Machine Status This field indicates the state of an AXBS halt. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 118 After the flags are set, they remain asserted until software clears the corresponding FPSCR field. Address: 0h base + 10h offset = 10h Reset Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 119 This field is a copy of the core’s FPSCR[IXC] field and signals an inexact number has been detected in the processor’s FPU. Once set, this field remains set until software clears FPSCR[IXC]. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 120 This read-only field is reserved and always has the value 0. This field is reserved. Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 121 This field is reserved. Reserved This read-only field is reserved and always has the value 0. M0_PID and M1_PID for MPU Drives the M0_PID and M1_PID values in the MPU. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 122 Compute operation entry has completed or compute operation exit has not completed. Compute Operation Request CPOREQ This field is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 123 Privileged writes from other bus masters are ignored. Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 124 Memory map/register descriptions Address: 0h base + 400h offset + (4d × i), where i=0d to 1d LMSZ Reset Reserved Reserved Reset * Notes: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 125 0010 2-Way Set Associative 0100 4-Way Set Associative 19–17 LMEM Data Path Width. This field defines the width of the local memory. 000-001 Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 126 This section of the programming model is an array of 32-bit generic on-chip memory descriptor registers that provide static information on the attached memories as well as configurable controls (where appropriate). S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 127 Privileged writes from other bus masters are ignored. Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error. Address: 0h base + 408h offset = 408h LMSZ Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 128 This field provides an encoded value of the local memory size; a LMSZ = 0 indicates the memory is not present. 0100 4 KB LMEMn 23–20 Level 1 Cache Ways 0000 No Cache 0010 2-Way Set Associative 0100 4-Way Set Associative Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 129 This field is used for cache parity control functions. • CF1[3]-PCPFE = PC Parity Fault Enable • CF1[2]-Reserved • CF1[1]-PCPME = PC Parity Miss Enable • CF1[0]-Reserved Reserved This field is reserved. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 130 Reserved This read-only field is reserved and always has the value 0. Enable RAM ECC Noncorrectable Reporting ERNCR Reporting disabled Reporting enabled 8.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 131 • PEIR[8] - 1-bit Error detected on SRAM_L ENCn = ECC Noncorrectable Error n • PEIR[7:2] - Reserved • PEIR[1] - Noncorrectable Error detected on SRAM_U • PEIR[0] - Noncorrectable Error detected on SRAM_L S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 132 Memory map/register descriptions 8.3.11 LMEM Fault Address Register (MCM_LMFAR) Address: 0h base + 490h offset = 490h EFADD Reset MCM_LMFAR field descriptions Field Description EFADD ECC Fault Address S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 133 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–8 Parity/ECC Fault Master Number PEFMST Parity/ECC Fault Write PEFW Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 134 Reset MCM_LMFDHR field descriptions Field Description PEFDH Parity or ECC Fault Data High 8.3.14 LMEM Fault Data Low Register (MCM_LMFDLR) Address: 0h base + 4A4h offset = 4A4h PEFDL Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 135 ISCR[31:16] and ISCR[15:0]. 2. Search the result for asserted bits which indicate the exact interrupt sources. NOTE ECC and Parity interrupts are determined by LMPECR (interrupt enable) and LMPEIR (interrupt source). S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 136 Functional description S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 137 • Flash memory and system RAM size configuration • FlexTimer clock channel and configuration • ADC trigger selection • LPO clock source selection • ENET clock control • Flash memory configuration • System device identification (ID) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 138 Platform Clock Gating Control Register (PLATCGC) 0000_001Fh Flash Configuration Register 1 (FCFG1) description. Unique Identification Register High (UIDH) description. Unique Identification Register Mid-High (UIDMH) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 139 9.3.1.2.2 Function SIM_CHIPCTL contains the controls for selecting ADC COCO trigger, trace clock, clock out source, PDB back-to-back mode, and ADC interleave channel. NOTE Bits 31:16 are reset on POR. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 140 Enable for internal supply monitoring on ADC0 internal channel 0 (configured by selecting ADC0_SC1n[ADCH] as 010101b). 0b - Disable internal supply monitoring 1b - Enable internal supply monitoring 18-16 ADC_SUPPLY ADC_SUPPLY Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 141 111b - Divide by 8 CLKOUT Select CLKOUTSEL NOTE: The below sequence should be followed while CLKOUT configuration: 1. Configure SIM_CHIPCTL[CLKOUTSEL] 2. Configure SIM_CHIPCTL[CLKOUTDIV] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 142 - PTB13 to ADC1_SE8 and ADC0_SE8 xx1xb - PTB1 to ADC0_SE5 and ADC1_SE15 xxx1b - PTB0 to ADC0_SE4 and ADC1_SE14 9.3.1.3 FTM Option Register 0 (FTMOPT0) 9.3.1.3.1 Offset Register Offset FTMOPT0 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 143 01b - FTM1 external clock driven by TCLK1 pin. 10b - FTM1 external clock driven by TCLK2 pin. 11b - No clock input 25-24 FTM0 External Clock Pin Select Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 144 NOTE: The pin source of the fault must be configured for FTM3 fault function through the appropriate PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM3 SELx corresponds to the FTM3 Fault x input. 000b - FTM3_FLTx pin Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 145 PORT_PCRn field when the fault comes from an external pin. TRGMUX_FTM0 SELx corresponds to the FTM0 Fault x input. 000b - FTM0_FLTx pin 001b - TRGMUX_FTM0 out 9.3.1.4 LPO Clock Select Register (LPOCLKS) 9.3.1.4.1 Offset Register Offset LPOCLKS S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 146 0b - Disable 32 kHz LPO_CLK output LPO32KCLKEN 1b - Enable 32 kHz LPO_CLK output 1 kHz LPO_CLK enable 0b - Disable 1 kHz LPO_CLK output LPO1KCLKEN 1b - Enable 1 kHz LPO_CLK output S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 147 11b - Reserved 11-9 ADC1 software pretrigger sources 000b - Software pretrigger disabled ADC1SWPRET 001b - Reserved (do not use) 010b - Reserved (do not use) Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 148 ADC channels are OR'ed together to support up to 16 pretriggers. 0b - PDB output 1b - TRGMUX output 9.3.1.6 FTM Option Register 1 (FTMOPT1) 9.3.1.6.1 Offset Register Offset FTMOPT1 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 149 This is used as trigger source for FTM4. See section FTM Hardware Triggers and Synchronization for details on FTM hardware triggering. 10-9 Reserved — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 150 This is used as trigger source for FTM0. See section FTM Hardware Triggers and Synchronization for details on FTM hardware triggering. 9.3.1.7 Miscellaneous control register 0 (MISCTRL0) 9.3.1.7.1 Offset Register Offset MISCTRL0 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 151 1b - The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. FTM6 OBE CTRL bit Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 152 1b - The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 153 1b - STOP1 entry successful Reserved — 9.3.1.8 System Device Identification Register (SDID) 9.3.1.8.1 Offset Register Offset SDID 9.3.1.8.2 Function NOTE This register's reset value is loaded during system reset from flash memory IFR. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 154 23-20 Derivate DERIVATE Specifies the derivate of the chip. The value is 8 (S32K148), 6 (S32K146), 4 (S32K144), 2 (S32K142), 8 (S32118), or 6 (S32K116). 19-16 RAM size RAMSIZE This field specifies the total amount of system RAM available on the chip, including FlexRAM.
Page 155 • Bit 4: QuadSPI • Bit 3: ENET • Bit 2: Reserved • Bit 1: SAI • Bit 0: Reserved 9.3.1.9 Platform Clock Gating Control Register (PLATCGC) 9.3.1.9.1 Offset Register Offset PLATCGC S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 156 Controls the clock gating to the MPU module. 0b - Clock disabled 1b - Clock enabled MSCM Clock Gating Control CGCMSCM Controls the clock gating to the MSCM. 0b - Clock disabled 1b - Clock enabled S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 157 Attempted writes to this register may result in unpredictable behavior. 9.3.1.10.3 Diagram Bits Reserved Reserved EEERAMSIZE Reset Bits Reset 9.3.1.10.4 Fields Field Function 31-28 Reserved — 27-24 Reserved — 23-20 Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 158 NOTE • UID127_96, UID95_64, UID63_32, and UID31_0 together represents 128-bit unique identification number for this device. • This register's reset value is loaded during system reset from flash memory IFR. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 159 Unique identification for the chip. 9.3.1.12 Unique Identification Register Mid-High (UIDMH) 9.3.1.12.1 Offset Register Offset UIDMH 9.3.1.12.2 Function NOTE This register's reset value is loaded during system reset from flash memory IFR. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 160 Unique identification for the chip. 9.3.1.13 Unique Identification Register Mid Low (UIDML) 9.3.1.13.1 Offset Register Offset UIDML 9.3.1.13.2 Function NOTE This register's reset value is loaded during system reset from flash memory IFR. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 161 Unique identification for the chip. 9.3.1.14 Unique Identification Register Low (UIDL) 9.3.1.14.1 Offset Register Offset UIDL 9.3.1.14.2 Function NOTE This register's reset value is loaded during system reset from flash memory IFR. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 162 UID31_0 Reset Bits UID31_0 Reset 9.3.1.14.4 Fields Field Function 31-0 Unique Identification UID31_0 Unique identification for the chip. 9.3.1.15 System Clock Divider Register 4 (CLKDIV4) 9.3.1.15.1 Offset Register Offset CLKDIV4 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 163 This field sets the divide value for the fractional clock divider used as a source for trace clock. The source clock for the trace clock is set by the SIM_CHIPCTL[TRACECLK_SEL]. Divider output clock = Divider input clock * [(TRACEFRAC+1)/(TRACEDIV+1)]. 9.3.1.16 Miscellaneous Control register 1 (MISCTRL1) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 164 Bits Reset 9.3.1.16.3 Fields Field Function 31-1 Reserved — Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity). SW_TRG S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 165 Any pad configuration done in RUN/VLPR mode is retained in low power modes(STOP1,STOP2/VLPS). Wait mode is not supported on this device. Module operation in available low power modes for details on available power modes. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 166 The following table shows the number of PCRs for each PORT on each product. Memory map and register definition documents the superset number of implemented ports. Table 10-1. PCRs on each product PORT Number of PCRs S32K116 S32K118 S32K142 S32K144 S32K146 S32K148 PORT A...
Page 167 (Sufficient delay should be added in ISR, if required, to achieve the above) 10.2 Introduction 10.3 Overview The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 168 • Pad configuration fields are functional in all digital pin muxing modes. 10.3.2 Modes of operation 10.3.2.1 Run mode In Run mode, the PORT operates normally. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 169 The table found here contains the detailed signal description for the PORT interface. Table 10-3. PORT interface—detailed signal description Signal Description PORTx[31:0] External interrupt. State meaning Asserted—pin is logic 1. Negated—pin is logic 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 170 Pin Control Register n (PORT_PCR22) See section 10.6.1/172 Pin Control Register n (PORT_PCR23) See section 10.6.1/172 Pin Control Register n (PORT_PCR24) See section 10.6.1/172 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 171 0) Interrupt Status Flag Register (PORT_ISFR) 0000_0000h 10.6.6/177 Digital Filter Enable Register (PORT_DFER) 0000_0000h 10.6.7/178 Digital Filter Clock Register (PORT_DFCR) 0000_0000h 10.6.8/178 Digital Filter Width Register (PORT_DFWR) 0000_0000h 10.6.9/179 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 172 PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. • PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 173 The corresponding pin is configured in the following pin muxing slot as follows: Pin disabled (Alternative 0) (analog). Alternative 1 (GPIO). Alternative 2 (chip-specific). Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 174 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 175 Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD. GPWD Global Pin Write Data Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 176 Description 31–16 Global Interrupt Write Data GIWD Write value that is written to all Pin Control Registers bits [31:16] that are selected by GIWE. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 177 Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 178 PORT_DFCR field descriptions Field Description 31–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Clock Source Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 179 CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a logic level occurring on the port pin. It also includes a flag to indicate that an interrupt has occurred. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 180 The two global pin control registers allow a single register write to update the lower half of the pin control register on up to 16 pins, all with the same value. Registers that are locked cannot be written using the global pin control registers. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 181 When not in Stop mode, the input is first synchronized to the bus clock to detect the configured level or edge transition. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 182 The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration register. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 183 Table 11-1. GPIO ports memory map Start address Port Base + 0h Port A Base + 40h Port B Base + 80h Port C Base + C0h Port D Base + 100h Port E S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 184 The GPIO module is clocked by system clock. 11.2.2 Modes of operation The following table depicts different modes of operation and the behavior of the GPIO module in these modes. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 185 Deassertion: When output, this signal occurs on the rising-edge of the system clock. For input, it may occur at any time and input may be asserted asynchronously to the system clock. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 186 Port Set Output Register (PSOR) WORZ 0000_0000h Port Clear Output Register (PCOR) WORZ 0000_0000h Port Toggle Output Register (PTOR) WORZ 0000_0000h Port Data Input Register (PDIR) 0000_0000h Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 187 Do not modify pin configuration registers associated with pins not available in your selected package. All unbonded pins not available in your package will default to DISABLE state for lowest power consumption. 11.3.1.2.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 188 Writing to this register updates the contents of the corresponding bit in the PDOR as follows: 0b - Corresponding bit in PDORn does not change. 1b - Corresponding bit in PDORn is set to logic 1. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 189 Writing to this register updates the contents of the corresponding bit in the Port Data Output Register (PDOR) as follows: 0b - Corresponding bit in PDORn does not change. 1b - Corresponding bit in PDORn is cleared to logic 0. 11.3.1.5 Port Toggle Output Register (PTOR) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 190 0b - Corresponding bit in PDORn does not change. 1b - Corresponding bit in PDORn is set to the inverse of its existing logic state. 11.3.1.6 Port Data Input Register (PDIR) 11.3.1.6.1 Offset Register Offset PDIR S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 191 0b - Pin logic level is logic 0, or is not configured for use by digital function. 1b - Pin logic level is logic 1. 11.3.1.7 Port Data Direction Register (PDDR) 11.3.1.7.1 Offset Register Offset PDDR S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 192 1b - Pin is configured as general-purpose output, for the GPIO function. 11.3.1.8 Port Input Disable Register (PIDR) 11.3.1.8.1 Offset Register Offset PIDR 11.3.1.8.2 Function This register disables each general-purpose pin from acting as an input. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 193 The logic state of each pin can be controlled via the port data output registers and port data direction registers, provided the pin is configured for the GPIO function. The following table depicts the conditions for a pin to be configured as input/output. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 194 The corresponding Port Control and Interrupt module does not need to be enabled to update the state of the port data direction registers and port data output registers including the set/clear/toggle registers. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 195 ARM core system bus S32K142 ARM core code bus ARM core system bus S32K116 ARM core master bus S32K118 ARM core master bus 1. Priority in fixed-priority mode. MCM controls mode selection for global slave port arbitration. For fixed priority, set MCM_CPCR[CBRR] to 0.
Page 196 S32K144 Flash memory SRAM controllers Peripheral Bridge 0/ controller GPIO S32K142 Flash memory SRAM controllers Peripheral Bridge 0/ controller GPIO S32K116 Flash memory SRAM controllers Peripheral Bridge 0/ controller GPIO S32K118 Flash memory SRAM controllers Peripheral Bridge 0/ controller GPIO 1.
Page 197 12.3.2 Arbitration The crossbar switch supports two arbitration algorithms: • Fixed priority • Round-robin S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 198 The requesting master's priority level is lower than the current At the conclusion of one of the following cycles: master. • An IDLE cycle • A non-IDLE cycle to a location other than the current slave port S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 199 The round-robin arbitration mode generally provides a more fair allocation of the available slave-port bandwidth (compared to fixed priority) as the fixed master priority does not affect the master selection. 12.4 Initialization/application information No initialization is required for the crossbar switch. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 200 Initialization/application information S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 201 Table 13-2. MPU Slave Port Assignments for S32K11x series Source MPU Slave Port Assignment Destination Crossbar slave port 0 MPU slave port 0 Flash Controller Crossbar slave port 1 MPU slave port 1 SRAM controller/MTB/DWT/MCM S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 202 Control/Error Status Register (CESR) that reflects those numbers. Table 13-4. MPU configurations Chips Region descriptors Slave ports CESR reset value S32K116 0081_2001 S32K118 0081_2001 S32K142 0081_4001h S32K144 0081_4001h S32K146...
Page 203 For details of the access evaluation macro, see Access evaluation macro. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 204 • Error registers, per slave port, capture the last faulting address, attributes, and other information • Global MPU enable/disable control bit 13.4 MPU register descriptions The programming model is partitioned into three groups: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 205 41Ch Region Descriptor 1, Word 3 (RGD1_WORD3) 0000_0000h 420h Region Descriptor 2, Word 0 (RGD2_WORD0) 0000_0000h 424h Region Descriptor 2, Word 1 (RGD2_WORD1) 0000_001Fh Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 206 4BCh Region Descriptor 11, Word 3 (RGD11_WORD3) 0000_0000h 4C0h Region Descriptor 12, Word 0 (RGD12_WORD0) 0000_0000h 4C4h Region Descriptor 12, Word 1 (RGD12_WORD1) 0000_001Fh Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 207 Region Descriptor Alternate Access Control 13 (RGDAAC13) 0000_0000h 838h Region Descriptor Alternate Access Control 14 (RGDAAC14) 0000_0000h 83Ch Region Descriptor Alternate Access Control 15 (RGDAAC15) 0000_0000h 13.4.2 Control/Error Status Register (CESR) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 208 0b - No error has occurred for slave port 1. 1b - An error has occurred for slave port 1. Slave Port 2 Error SPERR2 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 209 0001b - 12 region descriptors 0010b - 16 region descriptors Reserved — Valid Global enable/disable for the MPU. 0b - MPU is disabled. All accesses from all bus masters are allowed. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 210 CESR[SPERRn], as the error registers are always loaded upon the occurrence of each protection violation. 13.4.3.3 Diagram Bits EADDR Reset Bits EADDR Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 211 This register and the corresponding EARn register contain the most recent access error; there are no hardware interlocks with CESR[SPERRn] as the error registers are always loaded upon the occurrence of each protection violation. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 212 001b - User mode, data access 010b - Supervisor mode, instruction access 011b - Supervisor mode, data access Error Read/Write Indicates the access type of the faulting reference. 0b - Read 1b - Write S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 213 SRTADDR Reset Bits SRTADDR Reset 13.4.5.4 Fields Field Function 31-5 Start Address SRTADDR Defines the most significant bits of the 0-modulo-32 byte start address of the memory region. Reserved — S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 214 End Address ENDADDR Defines the most significant bits of the 31-modulo-32 byte end address of the memory region. NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR. Reserved — S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 215 Writes to RGDn_WORD2 clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn instead because stores to these locations do not affect the descriptor’s valid bit. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 216 1b - Bus master 4 writes allowed Reserved — This bit must be written with a zero. 22-21 Bus Master 3 Supervisor Mode Access Control Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 217 0b - Do not include the process identifier in the evaluation M0PE 1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation Bus Master 0 Supervisor Mode Access Control Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 218 40Ch 13.4.8.2 Function The fourth word of the region descriptor contains the optional process identifier and mask, plus the region descriptor’s valid bit. 13.4.8.3 Diagram Bits PIDMASK Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 219 13.4.9.2 Function The second word of the region descriptor defines the 31-modulo-32 byte end address of the memory region. Writes to this register clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 220 NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR. Reserved — 13.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_ WORD2) 13.4.10.1 Offset For n = 1 to 15: Register Offset RGDn_WORD2 408h + (n × 10h) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 221 Writes to RGDn_WORD2 clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn instead because stores to these locations do not affect the descriptor’s valid bit. 13.4.10.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 222 Defines the access controls for bus master 2 in Supervisor mode. 00b - r/w/x; read, write and execute allowed 01b - r/x; read and execute allowed, but no write Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 223 0b - An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed 1b - Allows the given access type to occur S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 224 Provides a masking capability so that multiple process identifiers can be included as part of the region hit determination. If a bit in PIDMASK is set, then the corresponding PID bit is ignored in the comparison. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 225 Because software may adjust only the access controls within a region descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of this 32- bit entity is available. Writing to this register does not affect the descriptor’s valid bit. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 226 0b - Bus master 4 writes terminate with an access error and the write is not performed M4WE 1b - Bus master 4 writes allowed Reserved — This bit must be written with a zero. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 227 0b - An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 228 Because software may adjust only the access controls within a region descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of this 32- bit entity is available. Writing to this register does not affect the descriptor’s valid bit. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 229 0b - Bus master 4 writes terminate with an access error and the write is not performed M4WE 1b - Bus master 4 writes allowed Reserved — This bit must be written with a zero. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 230 0b - An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 231 (RGDn) and performs two major functions: • Region hit determination • Detection of an access protection violation The following figure shows a functional block diagram. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 232 RGDn_Word3[PID] and RGDn_Word3[PIDMASK] are the process identifier fields from region descriptor n. For bus masters that do not output a process identifier, the MPU forces the pid_hit term to assert. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 233 As shown in the third condition, granting permission is a higher priority than denying access for overlapping regions. This approach is more flexible to system software in region descriptor assignments. For an example of the use of overlapping region descriptors, see Application information. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 234 (RGDn_Word{0,1,3}). Word 0 and 1 redefine the start and end addresses, respectively. Word 3 re-enables the region descriptor valid bit. In most situations, all four words of the region descriptor are rewritten. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 235 Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 236 • The remaining peripheral region accessible to both processors and the traditional DMA1 master This example shows one possible application of the capabilities of the MPU in a typical system. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 237 Peripheral bridge slot numbers from 0 -31. AIPS_OPACR0 – OPACR95 refer to off platform peripherals with corresponding AIPS Peripheral bridge slot numbers from 32 -127. 14.1.2.1 Register reset values The following table shows chip-specific reset values for AIPS registers: Table 14-1. Register reset values Register S32K116 S32K142 S32K144 S32K146 S32K148 MPRA 7770_0000...
Page 238 Introduction Table 14-1. Register reset values (continued) Register S32K116 S32K142 S32K144 S32K146 S32K148 OPACRA 4400_4444 4400_4444 4400_4444 4400_4444 OPACRB 0000_4400 0000_4400 0000_4400 0004_4440 OPACRC 0440_0044 0440_0044 0440_0044 0440_0044 OPACRD 4444_0400 4444_0400 4444_0400 4444_0400 OPACRE 4000_0040 4000_0040 4000_0040 4000_0040 OPACRF 4444_4400...
Page 239 Off-Platform Peripheral Access Control Register (OPACRH) 0040_0000h Off-Platform Peripheral Access Control Register (OPACRI) 0404_4444h Off-Platform Peripheral Access Control Register (OPACRJ) 0044_4044h Off-Platform Peripheral Access Control Register (OPACRK) 4404_0040h Off-Platform Peripheral Access Control Register (OPACRL) 0400_0444h S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 240 Determines whether the master is trusted for read accesses. 0b - This master is not trusted for read accesses. 1b - This master is trusted for read accesses. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 241 1b - This master is trusted for read accesses. Master 3 Trusted For Writes MTW3 Determines whether the master is trusted for write accesses. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 242 AIPS information for the field assignment of a particular peripheral. Every PACR field to which no peripheral is assigned is reserved. Reads to reserved locations return zeros, and writes are ignored. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 243 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Write Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 244 AIPS information for the field assignment of a particular peripheral. Every PACR field to which no peripheral is assigned is reserved. Reads to reserved locations return zeros, and writes are ignored. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 245 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 246 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — Reserved — S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 247 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 248 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 23-20 Reserved — 19-16 Reserved — 15-12 Reserved — 11-8 Reserved — Reserved — Reserved — S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 249 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 250 Determines whether the peripheral allows write accesses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 251 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 252 The peripheral assignment to each OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 253 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — Supervisor Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 254 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Write Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 255 OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. 14.3.1.8.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 256 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. 19-16 Reserved — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 257 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 258 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 259 0b - This peripheral allows write accesses. 1b - This peripheral is write protected. Trusted Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 260 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 261 OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. 14.3.1.10.3 Diagram Bits Reset Bits Reset 14.3.1.10.4 Fields Field Function Reserved — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 262 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 263 OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. 14.3.1.11.3 Diagram Bits Reset Bits Reset 14.3.1.11.4 Fields Field Function Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 264 If not, access terminates with an error response and no peripheral access initiates. 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 265 0b - This peripheral allows write accesses. 1b - This peripheral is write protected. Trusted Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 266 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — Reserved — 14.3.1.12 Off-Platform Peripheral Access Control Register (OPACRG) 14.3.1.12.1 Offset Register Offset OPACRG S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 267 0b - This peripheral allows write accesses. 1b - This peripheral is write protected. Trusted Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 268 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 269 AIPS information for the field assignment of a particular peripheral. 14.3.1.13.3 Diagram Bits Reset Bits Reset 14.3.1.13.4 Fields Field Function 31-28 Reserved — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 270 1b - Accesses from an untrusted master are not allowed. 19-16 Reserved — 15-12 Reserved — 11-8 Reserved — Reserved — Reserved — 14.3.1.14 Off-Platform Peripheral Access Control Register (OPACRI) 14.3.1.14.1 Offset Register Offset OPACRI S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 271 Determines whether the peripheral allows accesses from an untrusted master. When this field is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 272 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — Supervisor Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 273 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Write Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 274 OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. 14.3.1.15.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 275 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 276 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. Reserved — Supervisor Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 277 The peripheral assignment to each OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 278 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Write Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 279 0b - This peripheral does not require supervisor privilege level for accesses. 1b - This peripheral requires supervisor privilege level for accesses. Write Protect Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 280 OPACR field is defined by the memory map slot of the peripheral. See the chip- specific AIPS information for the field assignment of a particular peripheral. 14.3.1.17.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 281 0b - This peripheral allows write accesses. 1b - This peripheral is write protected. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 282 0b - Accesses from an untrusted master are allowed. 1b - Accesses from an untrusted master are not allowed. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 283 All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 284 Functional description S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 285 15.1.1 Number of channels The number of channels across S32K1xx series varies across variants. See below table for the same. Table 15-1. Number of channles Chips Number of channels S32K116 S32K118 S32K142 S32K144 S32K146 S32K148 15.1.2 DMA transfers via TRGMUX trigger The triggers from TRGMUX module can trigger a DMA transfer on the first four DMA channels, for example, the LPIT can trigger DMA via TRGMUX.
Page 286 The DMAMUX module provides these features: • Up to 61 peripheral slots and up to 2 always-on slots can be routed to 16 channels. • 16 independently selectable DMA channel routers. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 287 PIT). This mode is available only for channels 0–3. 15.3 External signal description The DMAMUX has no external pins. 15.4 Memory map/register definition This section provides a detailed description of all memory-mapped registers in the DMAMUX. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 288 This is true, even if a channel is disabled (ENBL==0). Before changing the trigger or source settings, a DMA channel must be disabled via CHCFGn[ENBL]. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 289 Functionally, the DMAMUX channels may be divided into two classes: • Channels that implement the normal routing functionality plus periodic triggering capability • Channels that implement only the normal routing functionality S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 290 DMA transfer cannot be guaranteed. Source #1 Source #2 Source #3 DMA channel #0 Trigger #1 Source #x DMA channel #m-1 Trigger #m Always #1 Always #y Figure 15-2. DMAMUX triggered channels S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 291 • Using the GPIO ports to drive or sample waveforms S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 292 This can either be a new software activation, or a transfer request from the DMA channel MUX. The options for doing this are: • Transfer all data in a single minor loop. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 293 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 294 DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with no periodic triggering capability: 1. Write 0x00 to CHCFG1. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 295 2. Write 0x00 to CHCFG8. 3. Write 0x87 to CHCFG8. (In this example, setting CHCFG[TRIG] would have no effect due to the assumption that channel 8 does not support the periodic triggering functionality.) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 296 *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 297 16.1.1 Number of channels The number of channels across S32K1xx series varies across variants. See below table for the same. Table 16-1. Number of channles Chips Number of channels S32K116 S32K118 S32K142 S32K144 S32K146 S32K148 16.2 Introduction...
Page 298 16.2.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. The eDMA engine is further partitioned into four submodules: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 299 As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage for each channel's transfer profile. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 300 • Programmable error terminations per channel and logically summed together to form one error interrupt to the interrupt controller • Programmable support for scatter/gather DMA processing • Support for complex data structures S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 301 The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 302 • Writes to reserved bits in a register are ignored. • Reading or writing a reserved memory location generates a bus error. 16.4.5 DMA register descriptions 16.4.5.1 DMA Memory map DMA base address: 4000_8000h S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 303 TCD Signed Source Address Offset (TCD0_SOFF) description. 1006h TCD Transfer Attributes (TCD0_ATTR) description. 1008h TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBY TES_MLNO) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 304 1036h TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD1_CITER_ELINKYES) description. 1038h TCD Last Destination Address Adjustment/Scatter Gather Address (TCD1_DLASTSGA) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 305 TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD3_NBY TES_MLNO) description. 1068h TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD3_NBYTES_MLOFFNO) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 306 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD4_CITER_ELINKYES) description. 1098h TCD Last Destination Address Adjustment/Scatter Gather Address (TCD4_DLASTSGA) description. 109Ch TCD Control and Status (TCD4_CSR) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 307 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD6_NBYTES_MLOFFNO) description. 10C8h TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD6_NBYTES_MLOFFYES) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 308 TCD Last Destination Address Adjustment/Scatter Gather Address (TCD7_DLASTSGA) description. 10FCh TCD Control and Status (TCD7_CSR) description. 10FEh TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD7_BITER_ELINKNO) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 309 Offset Disabled) (TCD9_NBYTES_MLOFFNO) description. 1128h TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD9_NBYTES_MLOFFYES) description. 112Ch TCD Last Source Address Adjustment (TCD9_SLAST) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 310 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD10_BITER_ELINKNO) description. 115Eh TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD10_BITER_ELINKYES) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 311 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD12_NBYTES_MLOFFYES) description. 118Ch TCD Last Source Address Adjustment (TCD12_SLAST) description. 1190h TCD Destination Address (TCD12_DADDR) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 312 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD13_BITER_ELINKNO) description. 11BEh TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD13_BITER_ELINKYES) description. 11C0h TCD Source Address (TCD14_SADDR) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 313 Enabled) (TCD15_NBYTES_MLOFFYES) description. 11ECh TCD Last Source Address Adjustment (TCD15_SLAST) description. 11F0h TCD Destination Address (TCD15_DADDR) description. 11F4h TCD Signed Destination Address Offset (TCD15_DOFF) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 314 (TCDn_SADDR) or destination address (TCDn_DADDR) upon minor loop completion. When minor loop offsets are enabled, the minor loop offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final destination address (TCDn_DADDR), S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 315 1b - Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 316 1b - When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. Reserved — Reserved S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 317 Fault reporting and handling for more details. 16.4.5.3.3 Diagram Bits Reset Bits ERRCHN Reset 16.4.5.3.4 Fields Field Function Logical OR of all ERR status bits Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 318 Source Bus Error 0b - No source bus error 1b - The last recorded error was a bus error on a source read Destination Bus Error 0b - No destination bus error S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 319 NOTE Disable a channel's hardware service request at the source before clearing the channel's ERQ bit. 16.4.5.4.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 320 1b - The DMA request signal for the corresponding channel is enabled Enable DMA Request 1 0b - The DMA request signal for the corresponding channel is disabled Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 321 The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. 16.4.5.5.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 322 0b - The error signal for corresponding channel does not generate an error interrupt EEI1 1b - The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 0 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 323 Reads of this register return all zeroes. 16.4.5.6.3 Diagram Bits Reset 16.4.5.6.4 Fields Field Function No Op enable 0b - Normal operation Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 324 In such a case the other three bytes of the word would all have their NOP bit set so that that these register will not be affected by the write. Reads of this register return all zeroes. 16.4.5.7.3 Diagram Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 325 Reads of this register return all zeroes. NOTE Disable a channel's hardware service request at the source before clearing the channel's ERQ bit. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 326 DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire contents of ERQ to be set. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 327 1b - Set all bits in ERQ Reserved — Set Enable Request SERQ Sets the corresponding bit in ERQ. 16.4.5.10 Clear DONE Status Bit Register (CDNE) 16.4.5.10.1 Offset Register Offset CDNE S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 328 0b - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field CADN 1b - Clears all bits in TCDn_CSR[DONE] Reserved — Clear DONE Bit CDNE Clears the corresponding bit in TCDn_CSR[DONE] 16.4.5.11 Set START Bit Register (SSRT) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 329 0b - Set only the TCDn_CSR[START] bit specified in the SSRT field SAST 1b - Set all bits in TCDn_CSR[START] Reserved — Set START Bit SSRT Sets the corresponding bit in TCDn_CSR[START] S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 330 0b - Clear only the ERR bit specified in the CERR field CAEI 1b - Clear all bits in ERR Reserved — Clear Error Indicator CERR Clears the corresponding bit in ERR S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 331 Clear All Interrupt Requests 0b - Clear only the INT bit specified in the CINT field CAIR 1b - Clear all bits in INT Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 332 The CINT register is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the INT register. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 333 Interrupt Request 7 0b - The interrupt request for corresponding channel is cleared INT7 1b - The interrupt request for corresponding channel is active Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 334 CERR in the interrupt-service routine is used for this purpose. The normal DMA channel completion indicators (setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request) are not affected when an error is detected. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 335 0b - An error in this channel has not occurred ERR11 1b - An error in this channel has occurred Error In Channel 10 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 336 0b - An error in this channel has not occurred ERR0 1b - An error in this channel has occurred 16.4.5.16 Hardware Request Status Register (HRS) 16.4.5.16.1 Offset Register Offset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 337 0b - A hardware service request for channel 14 is not present 1b - A hardware service request for channel 14 is present Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 338 0b - A hardware service request for channel 6 is not present 1b - A hardware service request for channel 6 is present Hardware Request Status Channel 5 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 339 0b - A hardware service request for channel 0 is not present 1b - A hardware service request for channel 0 is present 16.4.5.17 Enable Asynchronous Request in Stop Register (EARS) 16.4.5.17.1 Offset Register Offset EARS S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 340 0b - Disable asynchronous DMA request for channel 9. EDREQ_9 1b - Enable asynchronous DMA request for channel 9. Enable asynchronous DMA request in stop mode for channel 8 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 341 When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel. The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next higher S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 342 1b - Channel n can be temporarily suspended by the service request of a higher priority channel. Disable Preempt Ability. This field resets to 0. 0b - Channel n can suspend a lower priority channel. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 343 Offset TCDn_SADDR 1000h + (n × 20h) 16.4.5.19.2 Diagram Bits SADDR Reset Bits SADDR Reset 16.4.5.19.3 Fields Field Function 31-0 Source Address SADDR Memory address pointing to the source data. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 344 Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. 16.4.5.21 TCD Transfer Attributes (TCD0_ATTR - TCD15_ATTR) 16.4.5.21.1 Offset For n = 0 to 15: Register Offset TCDn_ATTR 1006h + (n × 20h) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 345 Destination data transfer size DSIZE See the SSIZE definition 16.4.5.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD0_NBYTES_MLOFFNO - TCD15_NBYTES_MLOFFNO) 16.4.5.22.1 Offset For n = 0 to 15: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 346 0b - The minor loop offset is not applied to the SADDR 1b - The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 347 If minor loop mapping is enabled and SMLOE and DMLOE are cleared, then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 348 TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. 16.4.5.24 TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBYTES_MLNO - TCD15_NBYTES_MLNO) 16.4.5.24.1 Offset For n = 0 to 15: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 349 TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 350 This register uses two's complement notation; the overflow bit is discarded. 16.4.5.26 TCD Destination Address (TCD0_DADDR - TCD15_DADDR) 16.4.5.26.1 Offset For n = 0 to 15: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 351 Memory address pointing to the destination data. 16.4.5.27 TCD Signed Destination Address Offset (TCD0_DOFF - TCD15_DOFF) 16.4.5.27.1 Offset For n = 0 to 15: Register Offset TCDn_DOFF 1014h + (n × 20h) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 352 Loop Count (Channel Linking Enabled) (TCD0_CITER_ELINKYES - TCD15_CITER_ ELINKYES), but its fields are defined differently based on the state of the ELINK field. If the ELINK field is cleared, this register is defined as follows. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 353 16.4.5.29 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_CITER_ELINKYES - TCD15_CI TER_ELINKYES) 16.4.5.29.1 Offset For n = 0 to 15: Register Offset TCDn_CITER_ELINKYE 1016h + (n × 20h) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 354 CITER field from the Beginning Iteration Count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 355 This value can apply to restore the destination address to the initial value or adjust the address to reference the next data structure. • This field uses two's complement notation for the final destination address adjustment. Otherwise: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 356 01b - Reserved 10b - eDMA engine stalls for 4 cycles after each R/W. 11b - eDMA engine stalls for 8 cycles after each R/W. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 357 NOTE: If BITER = 1, do not use INTHALF. Use INTMAJOR instead. 0b - The half-point interrupt is disabled. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 358 For n = 0 to 15: Register Offset TCDn_BITER_ELINKYE 101Eh + (n × 20h) 16.4.5.32.2 Function If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as follows. 16.4.5.32.3 Diagram Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 359 16.4.5.33 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_BITER_ELINKNO - TCD1 5_BITER_ELINKNO) 16.4.5.33.1 Offset For n = 0 to 15: Register Offset TCDn_BITER_ELINKNO 101Eh + (n × 20h) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 360 16.5 Functional description The operation of the eDMA is described in the following subsections. 16.5.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 361 The following diagram illustrates the second part of the basic data flow: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 362 (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 363 Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 364 Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 365 If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 366 3. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the ERQ register. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 367 CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 368 The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 369 (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 370 Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 371 Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 372 Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 373 There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 374 NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 375 TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done → set TCD12_CSR[START] bit S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 376 This section provides recommended methods to change the programming model during channel execution. 16.6.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 377 TCD.done bit is set, indicating the major loop is complete. NOTE The user must clear the The TCDn_CSR[DONE] bit before writing the TCDn_CSR[MAJORELINK] bit. The TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after a channel begins execution. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 378 1. When the descriptors are built, write a unique TCD ID in the TCDn_CSR[MAJORLINKCH] field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCDn_CSR[DREQ] bit. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 379 If ESG = 0b, read the 32 bit TCDn_DLASTSGA field. If ESG = 0b and the TCDn_DLASTSGA did not change, the attempted dynamic link did not succeed (the channel was already retiring). S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 380 TXFIFO upon the request. If the user needs to suspend the DMA/DSPI transfer loop, perform the following steps: 1. Disable the DMA service request at the source by writing 0 to DSPI_RSER[TFFF_RE]. Confirm that DSPI_RSER[TFFF_RE] is 0. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 381 DMA_HRS[HRSn] is 0 for the appropriate channel. If no service request is present, disable the DMA channel by clearing the channel's ERQ bit. If a service request is present, wait until the request has been processed and the HRS bit reads zero. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 382 Initialization/application information S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 383 32-bit trigger control register. Each control register supports up to four triggers, and each trigger can be selected from the available input triggers. The following figure shows the main structure of TRGMUX, using Module_A as an example. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 384 The following figures show the superset of trigger inputs, outputs, and control registers for the S32K1xx series. See attached S32K1xx_Trigger_Muxing.xlsx for details on recommendations which must be adhered while using the triggering scheme. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 385 1 In the ADC Configuration chapter, see the "Trigger Latching and Arbitration" section for details. 2 Interrupt enable needs to be configured before expecting RTC_alarm and RTC_second trigger from TRGMUX. Figure 17-2. Trigger interconnectivity (part 1 of 2: outputs 0-63) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 386 1 Interrupt enable needs to be configured before expecting RTC_alarm and RTC_second trigger from TRGMUX. Note: Above figure shows all the connections. Slots for an absent instance in a particular part are Reserved. Figure 17-3. Trigger interconnectivity (part 2 of 2: outputs 64-127) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 387 17.3 Features The TRGMUX module allows software to select the trigger source for peripherals. The block diagram below shows the trigger selection logic of the TRGMUX module. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 388 Table 17-1. Select Bit Fields Field Function SELx This read/write field is used to configure the MUX select for the peripheral trigger inputs. 000_0000 - (0x00) - 000_0001 - (0x01) VDD S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 389 010_0000 - (0x20) ADC1_SC1A[COCO] 010_0001 - (0x21) ADC1_SC1B[COCO] 010_0010 - (0x22) PDB0_CH0_TRIG 010_0011 - (0x23) Reserved 010_0100 - (0x24) PDB0_PULSE_OUT 010_0101 - (0x25) PDB1_CH0_TRIG 010_0110 - (0x26) Reserved 010_0111 - (0x27) PDB1_PULSE_OUT S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 390 100_0110 - (0x46) FTM4_EXT_TRIG 100_0111 - (0x47) FTM5_INIT_TRIG 100_1000 - (0x48) FTM5_EXT_TRIG 100_1001 - (0x49) FTM6_INIT_TRIG 100_1010 - (0x4A) FTM6_EXT_TRIG 100_1011 - (0x4B) FTM7_INIT_TRIG 100_1100 - (0x4C) FTM7_EXT_TRIG 100_1101 - (0x4D) Reserved S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 391 110_1100 - (0x6C) Reserved 110_1101 - (0x6D) Reserved 110_1110 - (0x6E) Reserved 110_1111 - (0x6F) Reserved 111_0000 - (0x70) Reserved 111_0001 - (0x71) Reserved 111_0010 - (0x72) Reserved 111_0011 - (0x73) Reserved S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 392 TRGMUX LPI2C0 Register (LPI2C0) 0000_0000h TRGMUX LPSPI0 Register (LPSPI0) 0000_0000h TRGMUX LPSPI1 Register (LPSPI1) 0000_0000h TRGMUX LPTMR0 Register (LPTMR0) 0000_0000h TRGMUX LPI2C1 Register (LPI2C1) 0000_0000h Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 393 Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK. 0b - Register can be written. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 394 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.3 TRGMUX EXTOUT0 Register (EXTOUT0) 17.4.1.3.1 Offset Register Offset EXTOUT0 17.4.1.3.2 Function TRGMUX Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 395 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 396 This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field setting definitions, see Memory map and register definition. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 397 Memory map and register definition. 17.4.1.5 TRGMUX ADC0 Register (ADC0) 17.4.1.5.1 Offset Register Offset ADC0 17.4.1.5.2 Function TRGMUX Register 17.4.1.5.3 Diagram Bits SEL3 SEL2 Reset Bits SEL1 SEL0 Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 398 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.6 TRGMUX ADC1 Register (ADC1) 17.4.1.6.1 Offset Register Offset ADC1 17.4.1.6.2 Function TRGMUX Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 399 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 400 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 401 Register Offset FTM0 17.4.1.8.2 Function TRGMUX Register 17.4.1.8.3 Diagram Bits SEL3 SEL2 Reset Bits SEL1 SEL0 Reset 17.4.1.8.4 Fields Field Function TRGMUX register lock. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 402 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.9 TRGMUX FTM1 Register (FTM1) 17.4.1.9.1 Offset Register Offset FTM1 17.4.1.9.2 Function TRGMUX Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 403 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 404 This read/write bit field is used to configure the MUX select for peripheral trigger input 2. For the field setting definitions, see Memory map and register definition. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 405 Memory map and register definition. 17.4.1.11 TRGMUX FTM3 Register (FTM3) 17.4.1.11.1 Offset Register Offset FTM3 17.4.1.11.2 Function TRGMUX Register 17.4.1.11.3 Diagram Bits SEL3 SEL2 Reset Bits SEL1 SEL0 Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 406 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.12 TRGMUX PDB0 Register (PDB0) 17.4.1.12.1 Offset Register Offset PDB0 17.4.1.12.2 Function TRGMUX Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 407 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.13 TRGMUX PDB1 Register (PDB1) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 408 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 409 Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK. 0b - Register can be written. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 410 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.15 TRGMUX LPIT0 Register (LPIT0) 17.4.1.15.1 Offset Register Offset LPIT0 17.4.1.15.2 Function TRGMUX Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 411 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 412 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 413 17.4.1.17 TRGMUX LPUART1 Register (LPUART1) 17.4.1.17.1 Offset Register Offset LPUART1 17.4.1.17.2 Function TRGMUX Register 17.4.1.17.3 Diagram Bits Reset Bits SEL0 Reset 17.4.1.17.4 Fields Field Function TRGMUX register lock. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 414 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.18 TRGMUX LPI2C0 Register (LPI2C0) 17.4.1.18.1 Offset Register Offset LPI2C0 17.4.1.18.2 Function TRGMUX Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 415 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.19 TRGMUX LPSPI0 Register (LPSPI0) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 416 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 417 Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK. 0b - Register can be written. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 418 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.21 TRGMUX LPTMR0 Register (LPTMR0) 17.4.1.21.1 Offset Register Offset LPTMR0 17.4.1.21.2 Function TRGMUX Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 419 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.22 TRGMUX LPI2C1 Register (LPI2C1) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 420 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 421 Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK. 0b - Register can be written. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 422 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.24 TRGMUX FTM5 Register (FTM5) 17.4.1.24.1 Offset Register Offset FTM5 17.4.1.24.2 Function TRGMUX Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 423 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. 17.4.1.25 TRGMUX FTM6 Register (FTM6) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 424 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 425 Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next system reset clears LK. 0b - Register can be written. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 426 Trigger MUX Input 0 Source Select SEL0 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field setting definitions, see Memory map and register definition. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 427 For safety, a redundant watchdog system, External Watchdog Monitor (EWM), is designed to monitor external circuits, as well as the MCU software flow. This provides a back-up mechanism to the internal watchdog that resets the MCU's CPU and peripherals. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 428 • One Input port, EWM_in, allows an external circuit to control the assertion of the EWM_OUT_b signal. 18.2.2 Modes of Operation This section describes the module's operating modes. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 429 • If the EWM is enabled prior to entry of debug mode, it remains enabled. • If the EWM is disabled prior to entry of debug mode, it remains disabled. 18.2.3 Block Diagram This figure shows the EWM block diagram. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 430 EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active low. EWM_OUT_b EWM reset out signal S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 431 RWONC Compare High Register (CMPH) RWONC Clock Prescaler Register (CLKPRESCALER) RWONC 18.4.1.2 Control Register (CTRL) 18.4.1.2.1 Offset Register Offset CTRL 18.4.1.2.2 Function The CTRL register is cleared by any reset. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 432 EWM_OUT_b signal. This bit when unset, keeps the EWM module disabled. It cannot be re-enabled until a next reset, due to the write-once nature of this bit. 18.4.1.3 Service Register (SERV) 18.4.1.3.1 Offset Register Offset SERV S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 433 18.4.1.4.1 Offset Register Offset CMPL 18.4.1.4.2 Function The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to refresh the EWM counter. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 434 CPU to refresh the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 435 This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. NOTE Write the required prescaler value before enabling the EWM. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 436 The EWM_OUT_b signal remains deasserted when the EWM is being regularly refreshed by the CPU within the programmable refresh window, indicating that the application code is executed as expected. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 437 EWM_OUT_b signal that controls the gating circuit. The EWM_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register is cleared, as after any reset. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 438 EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers for correct EWM refresh operation. Therefore, three possible conditions can occur: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 439 CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 440 Functional Description S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 441 The Error Injection Module (EIM) provides support for inducing single-bit and multi-bit inversions on read data when accessing peripheral RAMs. Injecting faults on memory accesses can be used to exercise the SEC-DED ECC function of the related system. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 442 Array rdata[0](LSB) chkbit[7] chkbit[0] EIMCR[GEIEN] EICHEN[EICHnEN] EICHDn_WORD0 EICHDn_WORD1 EICHDn_WORD2 Figure 19-1. EIM functional block diagram (64-bit read data bus and 8-bit checkbit bus) 19.2.2 Features The EIM includes these features: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 443 Word2 and Word3 are used only when required by the total width of the channel's data mask. See Error injection channel descriptor: DATA_MASK details and the individual registers' descriptions. The multiple channel descriptors are organized sequentially. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 444 Error Injection Channel Descriptor n, Word1 (EICHD1_WORD1) 0000_0000h 19.3.2 Error Injection Module Configuration Register (EIMCR) 19.3.2.1 Offset Register Offset EIMCR 19.3.2.2 Function The EIM Configuration Register is used to globally enable/disable the error injection function. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 445 19.3.3 Error Injection Channel Enable register (EICHEN) 19.3.3.1 Offset Register Offset EICHEN 19.3.3.2 Function Each field of the Error Injection Channel Enable register (EICHEN) is used to enable or disable the corresponding error injection channel. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 446 0b - Error injection is disabled on Error Injection Channel 1 1b - Error injection is enabled on Error Injection Channel 1 Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 447 — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 448 — Reserved — Reserved — Reserved — Reserved — Reserved — 19.3.4 Error Injection Channel Descriptor n, Word0 (EICHD0_W ORD0 - EICHD1_WORD0) 19.3.4.1 Offset Register Offset EICHD0_WORD0 100h EICHD1_WORD0 200h S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 449 0b - The corresponding bit of the checkbit bus remains unmodified. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 450 Successful writes to this field clear the corresponding error injection channel valid field, EICHEN[EICHnEN]. 19.3.5.3 Diagram Bits B0_3DATA_MASK Reset Bits B0_3DATA_MASK Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 451 Figure 19-1 depicts the interception and override of a 64-bit read data bus and an 8-bit checkbit data bus for an example memory array. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 452 • To generate a multi-bit error, invert only 2 bits of the CHKBIT_MASK or DATA_MASK in the EICHDn_WORD registers. NOTE An attempt to invert more than 2 bits in one operation might result in undefined behavior. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 453 ERM collects ECC events on memory accesses for platform local memory arrays, such as flash memory, system RAM, or peripheral RAMs. See the chip-specific ERM information for details about supported memory sources and specific memory channel assignments. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 454 • 114h Attempted updates to the programming model while the ERM is in the middle of an operation result in non-deterministic behavior. 20.3.1 ERM Memory map ERM base address: 4001_8000h S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 455 20.3.2.1 Offset Register Offset 20.3.2.2 Function This 32-bit control register configures the interrupt notification capability for each supported memory channel between 0 and 7. 20.3.2.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 456 1b - Interrupt notification of Memory 1 non-correctable error events is enabled. 25-24 Reserved — 23-22 Reserved — 21-20 Reserved — 19-18 Reserved — 17-16 Reserved — 15-14 Reserved — 13-12 Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 457 This 32-bit register signals which types of ECC events have been detected for each memory channel. The register signals the last memory event to be detected for each supported memory channel between 0 and 7. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 458 Write 1 to clear this field. This write also clears the corresponding interrupt notification if CR0[ESCIE1] is enabled. NOTE: Refer to the chip-specific ERM information for details on Memory 1 mapping. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 459 Reserved — 15-12 Reserved — 11-8 Reserved — Reserved — Reserved — 20.3.4 ERM Memory n Error Address Register (EAR0 - EAR1) 20.3.4.1 Offset Register Offset EAR0 100h EAR1 110h S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 460 • Records the event by changing to 1 the value of the applicable Status Register bit: SRx[SBCn] • Records the corresponding access address that initiated the event in the Memory n Error Address Register: EARn (if this register is present for the channel) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 461 Error Address Register: EARn (if this register is present for the channel) The ERM holds event information only for the last reported event. To clear the record of an event, write 1 to SRx[NCEn] to change its value to 0. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 462 SRx[SBCn] or SRx[NCEn] field that stores the record of the event. 3. Program the applicable CRx[ESCIEn] and CRx[ENCIEn] fields to enable ERM interrupts as desired. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 463 This results in the Watchdog timeout being generated after approximately 8 ms, which will force a MCU reset. To avoid this condition, please ensure that the watchdog is configured or refreshed before the 1024 cycles have elapsed. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 464 • Optional timeout interrupt to allow post-processing diagnostics • Interrupt request to CPU with interrupt vector for an interrupt service routine (ISR) • Forced reset occurs 128 bus clocks after the interrupt vector fetch. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 465 Bus Cycle Control Status 16-bit Window Register Disable Protect Bit Write Control 0xD928 UPDATE PRES WIN Figure 21-1. WDOG block diagram 21.3 Memory map and register definition 21.3.1 WDOG register descriptions S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 466 This section describes the function of Watchdog Control and Status Register. NOTE TST is cleared (0:0) on POR only. Any other reset does not affect the value of this field. 21.3.1.2.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 467 11b - ERCLK (external reference clock) Watchdog Enable This write-once bit enables the watchdog counter to start counting. 0b - Watchdog disabled. 1b - Watchdog enabled. Watchdog Interrupt Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 468 This write-once bit enables the watchdog to operate when the chip is in stop mode. 0b - Watchdog disabled in chip stop mode. 1b - Watchdog enabled in chip stop mode. 21.3.1.3 Watchdog Counter Register (CNT) 21.3.1.3.1 Offset Register Offset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 469 21.3.1.3.3 Diagram Bits Reset Bits CNTHIGH CNTLOW Reset 21.3.1.3.4 Fields Field Function 31-16 Reserved — 15-8 High byte of the Watchdog Counter CNTHIGH Low byte of the Watchdog Counter CNTLOW S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 470 21.3.1.4.3 Diagram Bits Reset Bits TOVALHIGH TOVALLOW Reset 21.3.1.4.4 Fields Field Function 31-16 Reserved — 15-8 High byte of the timeout value TOVALHIGH Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 471 The WIN register value must be less than the TOVAL register value. 21.3.1.5.3 Diagram Bits Reset Bits WINHIGH WINLOW Reset 21.3.1.5.4 Fields Field Function 31-16 Reserved — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 472 CS[PRES] is set, the clock source is prescaled by 256 before clocking the watchdog counter. The following table summarizes the different watchdog timeout periods which could be available, as an example. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 473 In addition, if window mode is used, software must not start the refresh sequence until after the time value set in the WIN register. See the following figure. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 474 • either two 16-bit writes ( 0xA602, 0xB480) or four 8-bit writes (0xA6, 0x02, 0xB4, 0x80; applicable to Cortex-M core cases) if WDOG_CS[CMD32EN] is 0; • one 32-bit write (0xB480_A602) if WDOG_CS[CMD32EN] is 1. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 475 • Conversely, if CS[UPDATE] remains 0, the only way to reconfigure the watchdog is by initiating a reset. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 476 WDOG logic loses its clock (the bus clock) and can no longer monitor the counter. If the watchdog counter overflows twice in succession (without an intervening reset), the backup reset function takes effect and generates a reset. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 477 8th bit of the low byte, thus ensuring that the overflow connection from the low byte to the high byte is tested.) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 478 As an ongoing test when using the default LPO clock source, software can periodically read the CNT register to ensure the counter is being incremented. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 479 DisableInterrupts; // disable global interrupt WDOG_CS &= ~WDOG_CS_EN_MASK; // disable watchdog WDOG_TOVAL= 0xFFFF; while(WDOG_CS[ULK]); // waiting for lock while(~WDOG_CS[RCS]); // waiting for new configuration to take effect EnableInterrupts; // enable global interrupt S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 480 To refresh the watchdog and reset the watchdog counter to zero, a refresh sequence is required. The code snippet below shows an example for 32-bit write. DisableInterrupts; // disable global interrupt WDOG_CNT = 0xB480A602; // refresh watchdog EnableInterrupts; // enable global interrupt S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 481 CRC data register via 8-bit accesses. In this case, the user's software must perform the bytewise transpose function. • Option for inversion of final CRC result • 32-bit CPU register programming interface S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 482 It resumes after the clock is enabled or via the system reset for exiting the low-power mode. Clock gating for this module is dependent on the MCU. 22.3 Memory map and register descriptions 22.3.1 CRC register descriptions S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 483 CRC mode, the CRC result is available in the LU and LL fields. In 32-bit CRC mode, all fields contain the result. Reads of this register at any time return the intermediate CRC value, provided the CRC module is configured. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 484 When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. 22.3.1.3 CRC Polynomial register (GPOLY) 22.3.1.3.1 Offset Register Offset GPOLY S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 485 Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not writable in 16-bit CRC mode (CTRL[TCRC] is 0). 15-0 Low Polynominal Half-word Writable and readable in both 32-bit and 16-bit CRC modes. 22.3.1.4 CRC Control register (CTRL) 22.3.1.4.1 Offset Register Offset CTRL S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 486 When asserted, a value written to the CRC data register is considered a seed value. When deasserted, a value written to the CRC data register is taken as data for CRC computation. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 487 1. Clear CRC_CTRL[TCRC] to enable 16-bit CRC mode. 2. Program the transpose and complement options in the CTRL register as required for the CRC calculation. See Transpose feature CRC result complement for details. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 488 The user software has the option to configure each transpose operation separately, as desired by the CRC standard. The data is transposed on the fly while being read or written. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 489 3. CTRL[TOT] or CTRL[TOTR] is 10. Both bits in bytes and bytes are transposed. reg[31:0] becomes = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 22-3. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 490 CRC data register every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the CRC data register accesses the raw checksum value. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 491 This provides software an option to perform a graceful shutdown. The MCU exits reset in RUN mode where the CPU is executing code. See Boot for more details. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 492 During and following a reset, the JTAG pins have their associated input pins configured • TDI as pullup (PU) • TCK as pulldown (PD) • TMS as pullup and associated output pin configured as: • TDO with no pull-down or pull-up S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 493 (VLVR), a system reset will be generated. LVR system is enabled in all modes. LVDRE has effect on LVD operation only. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 494 SPLL also flags LOL in case if the reference to SPLL goes faulty. So while using SPLL, any failure in reference clock source, i.e., SOSC might lead to either LOC or LOL event. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 495 0. Writing 1 to the core hold reset bit in the MDM-AP control register holds the core in reset as the rest of the chip comes out of system reset. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 496 23.2.4 Reset pin For all reset sources, the RESET_B pin is driven low by the MCU for at least 128 bus clock cycles and until flash memory initialization has completed. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 497 CDBGRSTREQ does not reset the debug-related registers within these modules: • CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) • FPB • DWT • ITM • NVIC • Crossbar bus switch • Private peripheral bus S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 498 To configure for alternate settings, program the appropriate bits in the NVM option byte. The new settings take effect on subsequent POR and any system reset. For more details on programming the option byte, see the flash memory chapter. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 499 SCG is enabled in its default clocking mode. 2. Required clocks are enabled (core clock, system clock, flash clock, and any bus clocks that do not have clock gate control reset to disabled). S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 500 FlexNVM data. This data is not available immediately out of reset and the system should not access this data until the flash controller completes this initialization step as indicated by the EEERDY flag. Subsequent system resets follow this same reset flow. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 501 RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on using the RCM. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 502 This read only field returns the major version number for the specification. 23–16 Minor Version Number MINOR This read only field returns the minor version number for the specification. FEATURE Feature Specification Number Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 503 RCM_VERID field descriptions (continued) Field Description This read only field returns the feature set number. 0x0003 Standard feature set. 24.4.2 Parameter Register (RCM_PARAM) Address: 0h base + 4h offset = 4h Reset Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 504 The feature is available. Existence of SRS[POR] status indication feature EPOR This static bit states whether or not the feature is available on the device. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 505 Note that multiple flags can be set if multiple reset events occur at the same time. The reset state of these bits depends on what caused the MCU to reset. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 506 This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Stop Acknowledge Error SACKERR Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 507 Watchdog WDOG Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 508 NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled. Address: 0h base + Ch offset = Ch Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 509 Selects how the reset pin filter is enabled in run and wait modes. All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 510 This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Sticky Stop Acknowledge Error SSACKERR Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 511 Sticky Watchdog SWDOG Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 512 The SRS updates only after the system reset occurs. NOTE The reset delay feature requires the LPO clock to remain active. NOTE This register is reset on Chip POR only, it is unaffected by other reset types. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 513 NOTE: The LOCKUP bit is useful only in devices with more than one core processor. Interrupt disabled. Interrupt enabled. JTAG generated reset JTAG Interrupt disabled. Interrupt enabled. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 514 Reset Delay Time Configures the maximum reset delay time from when the interrupt is asserted and the system reset occurs. 10 LPO cycles 34 LPO cycles 130 LPO cycles 514 LPO cycles S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 515 Clock selection for most modules is controlled by the PCC module. 25.2 High level clocking diagram The following diagram shows the high-level clocking architecture and various clock sources for this device. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 516 2 QSPI clocks are applicable for S32K148 only and Reserved for others. See QuadSPI clicking diagram in table 'Peripheral module clocking' Figure 25-1. Clocking diagram 25.3 Clock definitions The following table describes clocks shown in Figure 25-1 and other sections of this document. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 517 (÷ 1, 2, 4, 8, 16, 32, 64, or This should be configured to 40 MHz output disabled) or less in RUN mode and 56 MHz or less in HSRUN mode. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 518 MHz or less in RUN, and an integer divide of the CORE_CLK. The core clock to flash clock ratio is limited to a max value of 8. The following are a few of the common clock configurations for this chip in the four clocking modes: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 519 Memory Map/Register Definition register settings: • SCG_RCCR[SCS] = 0110b • SCG_RCCR[DIVCORE] = 0001b • SCG_RCCR[DIVBUS] = 0001b • SCG_RCCR[DIVSLOW] = 0010b 1. Default configuration after reset. FIRC_CLK = 48 MHz. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 520 Table 25-6. High Speed RUN 80 example (mode used by QuadSPI only) Clock Frequency CORE_CLK 80 MHz SYS_CLK 80 MHz BUS_CLK 40 MHz FLASH_CLK 26.67 MHz (maximum frequency in RUN mode) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 521 HSRUN mode to guarantee: • CORE_CLK/SYS_CLK is less than or equal to 112MHz • BUS_CLK is less than or equal to 56 MHz • FLASH_CLK is less than or equal to 28 MHz S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 522 Gated by Clocks controlled frequencies [CGC] of PCC by [PCS] of PCC Communications SPLLDIV2_CLK, Maximum FIRCDIV2_CLK, frequency LPUART BUS_CLK — SIRCDIV2_CLK, governed by SOSCDIV2_CLK BUS_CLK Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 523 Maximum frequency SYS_CLK — — governed by SYS_CLK SPLLDIV1_CLK, Maximum RTC_CLK FIRCDIV1_CLK, frequency SYS_CLK, FlexTimer SYS_CLK SIRCDIV1_CLK, governed by TCLKx SOSCDIV1_CLK SYS_CLK System Modules Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 524 BUS_CLK Maximum frequency DMAMUX BUS_CLK — — governed by BUS_CLK Maximum frequency SYS_CLK — — governed by SYS_CLK Maximum SYS_CLK — — frequency Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 525 3. FlexIO peripheral clock should not be more than twice of FlexIO bus interface clock. For fast access to FlexIO register (FLEXIO_CTRL[FASTACC]=1), FlexIO peripheral clock can be twice of FlexIO Bus interface clock. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 526 FIRCDIV2_CLK LPI2C to module LPUART Reserved Reserved SPLLDIV2_CLK Reserved PCC_<module>[PCS] PCC module to module SYS_CLK Clock gate enable PCC_<module>[CGC] (where 1b = clock enabled) Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 527 GPIO bus interface clock PORT PCC module PORT[x] BUS_CLK Clock gate enable bus clock PCC_<module>[CGC] (where 1b = clock enabled) bus clock Filter LPO128K_CLK lpo clock PORT_DFCR[CS] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 528 PCC module EWM module BUS_CLK Clock gate enable Peripheral bus clock PCC_EWM[CGC] (where 1 = clock enabled) LPO128K_CLK LPO_CLK Low power clock LPO32K_CLK LPO1K_CLK SIM_LPOCLKS[LPOCLKSEL] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 529 WDOG clock SOSC_CLK internal clk LPO1K_CLK SIRC_CLK external clk SIM_LPOCLKS[LPOCLKSEL] SIM/PMC/TRGMUX TRGMUX BUS_CLK bus interface clock BUS_CLK bus clock Filter LPO128K_CLK lpo clock Reserved RCM_RPC[RSTFLTSRW] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 530 PCC_ADCx[PCS]. The dividers should be configured such that the ADC conversion clock frequency lies within the valid range as per the ADC requirement (see the Data Sheet). Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 531 The fixed frequency clock and external clocks provide the user more clock options for FTM counter. LPO1K_CLK 1 kHz clock RTC_CLKOUT RTC_CLK RTC_CLK RTC_CLKOUT pin Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 532 The BCLK can either be externally provided through BCLK pin or can be internally generated in internal bit clock mode using SAI internal divider by configuring SAIn_RCR2[MSEL]/ SAIn_TCR2[MSEL] and SAIn_RCR2[DIV]/SAIn_TCR2[DIV]. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 533 Reserved see PCC chapter for details NOTE: SIM_MISCTRL0 bit 24 and 25 are used to control which clock (external or internally generated) is used by MAC in RMII mode only. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 534 Module clocks NOTE While changing peripheral clock source, the corresponding module should be disabled. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 535 • 11 Reserved NOTE Software should not configure the SCG_FIRCCFG[RANGE] to any value other than 00. 3. SCG_SIRCCFG[RANGE] • 0 Reserved • 1 Slow IRC high range clock (8 MHz ) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 536 10 LPO. • Execute the clock switch • Wait/Poll for the clock switch to complete • Configure every reset source back to original intended reset configuration (Interrupt or Reset) via RCM_SRIE S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 537 • Either the slow or the fast clock can be selected as the clock source for the MCU system clocks • 2 programmable post-divider clock outputs for each IRC, which can be used as clock sources for other on-chip peripherals • System Crystal Oscillator: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 538 See section 26.3.8/551 System OSC Divide Register (SCG_SOSCDIV) 0000_0000h 26.3.9/553 26.3.10/ System Oscillator Configuration Register (SCG_SOSCCFG) 0000_0010h 26.3.11/ Slow IRC Control Status Register (SCG_SIRCCSR) 0100_0005h Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 539 Note: Writing to this register will result in a transfer error. Address: 0h base + 0h offset = 0h VERSION Reset SCG_VERID field descriptions Field Description VERSION SCG Version Number S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 540 This register returns the currently configured system clock source and the system clock dividers for the core (DIVCORE) and peripheral interface clock (DIVSLOW). The SCG_CSR reflects the configuration set by one of three clock control registers SCG_RCCR, SCG_VCCR, SCG_HCCR. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 541 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Divide-by-9 1001 Divide-by-10 1010 Divide-by-11 1011 Divide-by-12 1100 Divide-by-13 1101 Divide-by-14 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 542 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 543 This read-only field is reserved and always has the value 0. 19–16 Core Clock Divide Ratio DIVCORE 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 544 Slow Clock Divide Ratio 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Reserved 1001 Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 545 VLPR mode requires that clock source to be enabled first and be valid before system clocks switch to that clock source. 0000 Reserved 0001 Reserved 0010 Slow IRC (SIRC_CLK) 0011 Reserved 0100 Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 546 Divide-by-7 0111 Divide-by-8 1000 Divide-by-9 1001 Divide-by-10 1010 Divide-by-11 1011 Divide-by-12 1100 Divide-by-13 1101 Divide-by-14 1110 Divide-by-15 1111 Divide-by-16 DIVSLOW Slow Clock Divide Ratio Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 547 Selecting a different clock source when in HSRUN mode will enable that clock source and switch to that clock mode when it is valid. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 548 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Divide-by-9 1001 Divide-by-10 1010 Divide-by-11 1011 Divide-by-12 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 549 This read-only field is reserved and always has the value 0. 27–24 SCG Clkout Select CLKOUTSEL Selects the SCG system clock. 0000 SCG SLOW Clock 0001 System OSC (SOSC_CLK) Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 550 Fast IRC (FIRC_CLK) 0100 Reserved 0101 Reserved 0110 System PLL (SPLL_CLK) 0111 Reserved 1111 Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 551 This flag is reset on Chip POR only, software can also clear this flag by writing a logic one. System OSC Clock Monitor is disabled or has not detected an error System OSC Clock Monitor is enabled and detected an error Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 552 This field is reserved. Software should write 0 to these bits to maintain compatibility. System OSC Enable SOSCEN If this bit written during clock switching, it should be read back and confirmed before proceeding. System OSC is disabled System OSC is enabled S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 553 System OSC Clock Divide 1 Clock divider 1 for System OSC. Used to generate the system clock source for modules that need an asynchronous clock source. Output disabled Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 554 Selects the frequency range for the system crystal oscillator (OSC) See chip-specific information for supported crystal oscillator ranges. Reserved Low frequency range selected for the crystal oscillator Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 555 OSC (SOSC) into the SCG, thus either the crystal oscillator or from an external clock input External reference clock selected Internal crystal oscillator of OSC selected. Reserved This field is reserved. This read-only field is reserved and always has the value 0. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 556 Slow IRC is not enabled or clock is not valid Slow IRC is enabled and output clock is valid Lock Register This bit field can be cleared/set at any time. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 557 15–11 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 10–8 Slow IRC Clock Divide 2 SIRCDIV2 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 558 The SIRCCFG register cannot be changed when the slow IRC clock is enabled. When the slow IRC clock is enabled, writes to this register are ignored, and there is no transfer error. Address: 0h base + 208h offset = 208h Reset Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 559 Slow IRC low range clock (2 MHz) Slow IRC high range clock (8 MHz ) 26.3.14 Fast IRC Control Status Register (SCG_FIRCCSR) Address: 0h base + 300h offset = 300h Reset Reserved Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 560 This field is reserved. Fast IRC Enable FIRCEN If this bit written during clock switching, it should be read back and confirmed before proceeding. Fast IRC is disabled Fast IRC is enabled S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 561 Clock divider 1 for Fast IRC. Used to generate the system clock source for modules that need an asynchronous clock source. Output disabled Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 562 See chip-specific information for supported frequency ranges. Fast IRC is trimmed to 48 MHz Fast IRC is trimmed to 52 MHz Fast IRC is trimmed to 56 MHz Fast IRC is trimmed to 60 MHz S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 563 System OSC is selected as its source and SOSCERR has set. System PLL Selected SPLLSEL System PLL is not the system clock source System PLL is the system clock source System PLL Valid SPLLVLD Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 564 As the device exits reset, the SCG_RCCR register should be configured as per the supported frequency ranges of the device BEFORE enabling the SPLL (SPLLEN =1). System PLL is disabled System PLL is enabled S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 565 Clock divider 1 for System PLL. Used to generate the system clock source for modules that need an asynchronous clock source. Clock disabled Divide by 1 Divide by 2 Divide by 4 Divide by 8 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 566 MULT Multiply MULT Multiply MULT Multiply MULT Multiply Factor Factor Factor Factor 00000 01000 10000 11000 00001 01001 10001 11001 00010 01010 10010 11010 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 567 26.4 Functional description 26.4.1 SCG Clock Mode Transitions The following figure shows the valid clock mode transitions supported by SCG. Slow IRC (SIRC) boot mode is not supported on this device. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 568 For example, if a transition from RUN mode to VLRUN is required, first complete any required clock change. Initiate the VLRUN request after the clock change has completed. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 569 Sys PLL (SPLL) mode is entered when all the following conditions occur: • RUN MODE: 0110 is written to RCCR[SCS]. HSRUN MODE: 0110 is written to HCCR[SCS]. • SPLLEN = 1 • SPLLVLD = 1 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 570 SIRCCLK is available in Normal Stop and VLPS mode when all the following conditions become true: • SIRCCSR[SIRCEN] = 1 • SIRCCSR[SIRCSTEN] = 1 • SIRCCSR[SIRCLPEN] = 1 in VLPS S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 571 The Peripheral Clock Control (PCC) module provides clock control and configuration for on-chip peripherals. Each peripheral has its own clock control and configuration register. 27.3 Features The PCC module enables software to configure the following clocking options for each peripheral: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 572 (CGC) for the module's interface clock. Before a module can be used, its interface clock must be enabled (CGC = 1) in the module's PCC register. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 573 PCC ADC1 Register (PCC_ADC1) 8000_0000h PCC FlexCAN2 Register (PCC_FlexCAN2) 8000_0000h PCC LPSPI0 Register (PCC_LPSPI0) 8000_0000h PCC LPSPI1 Register (PCC_LPSPI1) 8000_0000h PCC LPSPI2 Register (PCC_LPSPI2) 8000_0000h Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 574 8000_0000h 1C4h PCC FTM7 Register (PCC_FTM7) 8000_0000h 1CCh PCC CMP0 Register (PCC_CMP0) 8000_0000h 1D8h PCC QSPI Register (PCC_QSPI) 8000_0000h 1E4h PCC ENET Register (PCC_ENET) 8000_0000h 27.6.2 PCC FTFC Register (PCC_FTFC) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 575 This read-only bit field is reserved. This bit can change values but is a don't-care. — 28-27 This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 576 This read-only bit field is reserved and always has the value 0. — 27.6.3 PCC DMAMUX Register (PCC_DMAMUX) 27.6.3.1 Offset Register Offset PCC_DMAMUX 27.6.3.2 Function PCC Register 27.6.3.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 577 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.4 PCC FlexCAN0 Register (PCC_FlexCAN0) 27.6.4.1 Offset Register Offset PCC_FlexCAN0 27.6.4.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 578 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 579 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control This read/write bit enables the clock for the peripheral. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 580 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.6 PCC FTM3 Register (PCC_FTM3) 27.6.6.1 Offset Register Offset PCC_FTM3 27.6.6.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 581 101b - Clock option 5 110b - Clock option 6 111b - Clock option 7 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 582 This read-only bit field is reserved and always has the value 0. — 27.6.7 PCC ADC1 Register (PCC_ADC1) 27.6.7.1 Offset Register Offset PCC_ADC1 27.6.7.2 Function PCC Register 27.6.7.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 583 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.8 PCC FlexCAN2 Register (PCC_FlexCAN2) 27.6.8.1 Offset Register Offset PCC_FlexCAN2 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 584 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 585 27.6.9 PCC LPSPI0 Register (PCC_LPSPI0) 27.6.9.1 Offset Register Offset PCC_LPSPI0 27.6.9.2 Function PCC Register 27.6.9.3 Diagram Bits Reset Bits Reset 27.6.9.4 Fields Field Function Present Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 586 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.10 PCC LPSPI1 Register (PCC_LPSPI1) 27.6.10.1 Offset Register Offset PCC_LPSPI1 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 587 This field can be written only when the clock is disabled (CGC = 0). 000b - Clock is off. 001b - Clock option 1 010b - Clock option 2 011b - Clock option 3 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 588 This read-only bit field is reserved and always has the value 0. — 27.6.11 PCC LPSPI2 Register (PCC_LPSPI2) 27.6.11.1 Offset Register Offset PCC_LPSPI2 27.6.11.2 Function PCC Register 27.6.11.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 589 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.12 PCC PDB1 Register (PCC_PDB1) 27.6.12.1 Offset Register Offset PCC_PDB1 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 590 This read-only bit field is reserved and always has the value 0. — 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 591 This read-only bit field is reserved and always has the value 0. — 27.6.13 PCC CRC Register (PCC_CRC) 27.6.13.1 Offset Register Offset PCC_CRC 27.6.13.2 Function PCC Register 27.6.13.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 592 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.14 PCC PDB0 Register (PCC_PDB0) 27.6.14.1 Offset Register Offset PCC_PDB0 27.6.14.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 593 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 594 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control This read/write bit enables the clock for the peripheral. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 595 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.16 PCC FTM0 Register (PCC_FTM0) 27.6.16.1 Offset Register Offset PCC_FTM0 27.6.16.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 596 101b - Clock option 5 110b - Clock option 6 111b - Clock option 7 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 597 This read-only bit field is reserved and always has the value 0. — 27.6.17 PCC FTM1 Register (PCC_FTM1) 27.6.17.1 Offset Register Offset PCC_FTM1 27.6.17.2 Function PCC Register 27.6.17.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 598 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.18 PCC FTM2 Register (PCC_FTM2) 27.6.18.1 Offset Register Offset PCC_FTM2 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 599 This field can be written only when the clock is disabled (CGC = 0). 000b - Clock is off. An external clock can be enabled for this peripheral. 001b - Clock option 1 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 600 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.19 PCC ADC0 Register (PCC_ADC0) 27.6.19.1 Offset Register Offset PCC_ADC0 27.6.19.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 601 101b - Clock option 5 110b - Clock option 6 111b - Clock option 7 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 602 This read-only bit field is reserved and always has the value 0. — 27.6.20 PCC RTC Register (PCC_RTC) 27.6.20.1 Offset Register Offset PCC_RTC 27.6.20.2 Function PCC Register 27.6.20.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 603 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.21 PCC LPTMR0 Register (PCC_LPTMR0) 27.6.21.1 Offset Register Offset PCC_LPTMR0 100h 27.6.21.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 604 101b - Clock option 5 110b - Clock option 6 111b - Clock option 7 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 605 101b - Divide by 6. 110b - Divide by 7. 111b - Divide by 8. 27.6.22 PCC PORTA Register (PCC_PORTA) 27.6.22.1 Offset Register Offset PCC_PORTA 124h 27.6.22.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 606 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 607 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control This read/write bit enables the clock for the peripheral. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 608 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.24 PCC PORTC Register (PCC_PORTC) 27.6.24.1 Offset Register Offset PCC_PORTC 12Ch 27.6.24.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 609 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 610 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control This read/write bit enables the clock for the peripheral. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 611 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.26 PCC PORTE Register (PCC_PORTE) 27.6.26.1 Offset Register Offset PCC_PORTE 134h 27.6.26.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 612 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 613 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control This read/write bit enables the clock for the peripheral. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 614 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.28 PCC SAI1 Register (PCC_SAI1) 27.6.28.1 Offset Register Offset PCC_SAI1 154h 27.6.28.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 615 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 616 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control This read/write bit enables the clock for the peripheral. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 617 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.30 PCC EWM Register (PCC_EWM) 27.6.30.1 Offset Register Offset PCC_EWM 184h 27.6.30.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 618 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 619 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Gate Control This read/write bit enables the clock for the peripheral. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 620 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.32 PCC LPI2C1 Register (PCC_LPI2C1) 27.6.32.1 Offset Register Offset PCC_LPI2C1 19Ch 27.6.32.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 621 101b - Clock option 5 110b - Clock option 6 111b - Clock option 7 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 622 This read-only bit field is reserved and always has the value 0. — 27.6.33 PCC LPUART0 Register (PCC_LPUART0) 27.6.33.1 Offset Register Offset PCC_LPUART0 1A8h 27.6.33.2 Function PCC Register 27.6.33.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 623 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.34 PCC LPUART1 Register (PCC_LPUART1) 27.6.34.1 Offset Register Offset PCC_LPUART1 1ACh S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 624 This field can be written only when the clock is disabled (CGC = 0). 000b - Clock is off. 001b - Clock option 1 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 625 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.35 PCC LPUART2 Register (PCC_LPUART2) 27.6.35.1 Offset Register Offset PCC_LPUART2 1B0h 27.6.35.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 626 101b - Clock option 5 110b - Clock option 6 111b - Clock option 7 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 627 This read-only bit field is reserved and always has the value 0. — 27.6.36 PCC FTM4 Register (PCC_FTM4) 27.6.36.1 Offset Register Offset PCC_FTM4 1B8h 27.6.36.2 Function PCC Register 27.6.36.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 628 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.37 PCC FTM5 Register (PCC_FTM5) 27.6.37.1 Offset Register Offset PCC_FTM5 1BCh S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 629 This field can be written only when the clock is disabled (CGC = 0). 000b - Clock is off. An external clock can be enabled for this peripheral. 001b - Clock option 1 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 630 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.38 PCC FTM6 Register (PCC_FTM6) 27.6.38.1 Offset Register Offset PCC_FTM6 1C0h 27.6.38.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 631 101b - Clock option 5 110b - Clock option 6 111b - Clock option 7 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 632 This read-only bit field is reserved and always has the value 0. — 27.6.39 PCC FTM7 Register (PCC_FTM7) 27.6.39.1 Offset Register Offset PCC_FTM7 1C4h 27.6.39.2 Function PCC Register 27.6.39.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 633 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.40 PCC CMP0 Register (PCC_CMP0) 27.6.40.1 Offset Register Offset PCC_CMP0 1CCh S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 634 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 635 27.6.41 PCC QSPI Register (PCC_QSPI) 27.6.41.1 Offset Register Offset PCC_QSPI 1D8h 27.6.41.2 Function PCC Register 27.6.41.3 Diagram Bits Reset Bits Reset 27.6.41.4 Fields Field Function Present Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 636 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 27.6.42 PCC ENET Register (PCC_ENET) 27.6.42.1 Offset Register Offset PCC_ENET 1E4h 27.6.42.2 Function PCC Register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 637 101b - Clock option 5 110b - Clock option 6 111b - Clock option 7 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 638 010b - Divide by 3. 011b - Divide by 4. 100b - Divide by 5. 101b - Divide by 6. 110b - Divide by 7. 111b - Divide by 8. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 639 If the final count of monitored clock is less than low threshold, FLL interrupt is generated by the module. Similarly, if the final count of monitored clock is more than high threshold, FHH interrupt is generated by the module. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 640 CMU Frequency Check High Threshold Configuration Register 00FF_FFFFh (CMU_FCHTCR) CMU Frequency Check Low Threshold Configuration Register 0000_0000h (CMU_FCLTCR) CMU Frequency Check Status Register (CMU_FCSR) 0000_0000h CMU Frequency Check Interrupt/Event Enable Register (CMU_FCIE 0000_0000h S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 641 When frequency check is enabled then writing into other configuration registers is disabled. First disable the frequency check to write into other configuration registers. 0b - Frequency Check Disabled 1b - Frequency Check Enabled S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 642 Reserved. — 15-0 Reference Clock Count REF_CNT Total number of counts of reference clock for which frequency check will run. These bits define the duration of one frequency check window. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 643 These bits determine the high reference value for the monitored clock frequency. The reference value is given by: (Freq. of monitored clock/ freq. of reference clock)*REF_CNT + higher threshold margin S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 644 LFREF These bits determine the low reference value for the CLKMN1 frequency. The reference value is given by: (Freq. of monitored clock/ freq. of reference clock)*REF_CNT - lower threshold margin S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 645 (CMU_FCGCR[FCE}=1) it takes 10 Bus clock cycles + 10 reference clock cycles delay before this bit shows running status. 0b - Frequency Check Stopped 1b - Frequency Check Running Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 646 28.2.7 CMU Frequency Check Interrupt/Event Enable Register (CMU_FCIER) 28.2.7.1 Offset Register Offset CMU_FCIER 28.2.7.2 Function This register masks/unmasks the event status of the module. NOTE: This register can be written only when CMU_FCGCR[FCE] = '0'. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 647 • Stage 1: Reference clock counter runs for CMU_FCRCCR[REF_CNT] cycles of reference clock and monitored clock counter runs in parallel for the same time duration as the reference clock counter. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 648 The module has a maximum deviation of +/- 2 monitored clock cycles over the ideal monitored clock cycles expected by the user. Example fReference_Clock = 20 MHz fmonitored_clock = 200 MHz S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 649 5. Once the above steps have been completed, program CMU_FCGCR[FCE]=1 to start frequency check operation. Note: Writing into CMU_FCRCCR, CMU_FCHTCR and CMU_FCLTCR is disabled after CMU_FCGCR[FCE] has been set. NOTE CMU_FCGCR[FCE]=0 can be programmed only when CMU_FCSR[RS] = 1. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 650 Programming Guidelines S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 651 Table 29-1. Reference links to related information Topic Related module Reference System memory map See attached S32K1xx_memory_map.xlsx Clocking System Clock Generator Clock Distribution ARM Cortex-M4 core ARM Cortex-M4F core Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 652 Table 29-2. On-chip SRAM sizes Chip SRAM_L (KB) SRAM_U (KB) FlexRAM (KB) Total SRAM (KB) S32K116 S32K142 S32K142 S32K144 S32K146 S32K148 1. See attached S32K1xx_memory_map.xlsx for specific addresses 2. 1 KB of for MTB. If not used for MTB, can be use as System RAM. Not ECC protected...
Page 653 The following table illustrates these scenarios. Table 29-4. SRAM simultaneous accesses Core code bus access Core system bus access Non-core bus master access SRAM_L SRAM_U — Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 654 During software initialization, ensure that no accesses occur to RAM with retained contents. 4. After exiting reset, read SRAMU_RETEN SRAML_RETEN in the Chip Control register (CHIPCTL) and write 1 to them to allow accesses to SRAM. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 655 For each S32K14x product's SRAM sizes and other details, see SRAM sizes. 30.2 Introduction The Local Memory Controller provides the processor with tightly-coupled processor- local memories and bus paths to all slave memory spaces. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 656 • Two output ports are the CCM (Core Code Master) bus used for PC accesses that do not hit the PC cache or SRAM_L or are non-cacheable and the CSM (Core System Master) bus used for PS references that do not hit the SRAM_U. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 657 • Temporal locality — An access to an area of memory is likely to be repeated within a short time period (for example, execution of a code loop). S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 658 2. Non-cacheable — access to address spaces with this cache mode are not cacheable. These accesses bypass the cache and access the output bus. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 659 Cache line control register (PCCLCR) 0000_0000h Cache search address register (PCCSAR) 0000_0000h Cache read/write value register (PCCCVR) 0000_0000h Cache regions mode register (PCCRMR) AA0F_A000h 30.3.1.2 Cache control register (PCCCR) 30.3.1.2.1 Offset Register Offset PCCCR S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 660 1b - When setting the GO bit, invalidate all lines in way 0. 23-4 Reserved — Forces no allocation on cache misses (must also have PCCR2 asserted) Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 661 If a physical address is specified, both ways of the cache are searched, and the command is only performed on the way which hits. 30.3.1.3.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 662 Selects tag or data for search and read or write commands. 0b - Data 1b - Tag Reserved — Way select WSEL Selects the way for line commands. 0b - Way 0 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 663 The CSAR register is used to define the explicit cache address or the physical address for line-sized commands specified in the CLCR[LADSEL] bit. 30.3.1.4.3 Diagram Bits PHYADDR Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 664 30.3.1.5 Cache read/write value register (PCCCVR) 30.3.1.5.1 Offset Register Offset PCCCVR 30.3.1.5.2 Function The CCVR register is used to source write data or return read data for the commands specified in the CLCR register. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 665 After a region is demoted, its cache mode can only be raised by a reset, which returns it to its default state. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 666 10b - Write-through 11b - Write-back 27-26 Region 2 mode Controls the cache mode for region 2 00b - Non-cacheable 01b - Non-cacheable 10b - Write-through Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 667 00b - Non-cacheable 01b - Non-cacheable 10b - Write-through 11b - Write-back 11-10 Region 10 mode Controls the cache mode for region 10 00b - Non-cacheable Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 668 10b - Write-through 11b - Write-back 30.4 Functional Description 30.4.1 LMEM Function The Local Memory Controller receives the following requests: • Core master bus requests on the Processor Code (PC) bus, S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 669 All LMEM backdoor port accesses are for the SRAM controller. These accesses go to the SRAM_L or the SRAM_U depending on their specific address. 30.4.2 SRAM Function 30.4.2.1 SRAM Configuration The figure below shows how the SRAM controller is configured. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 670 • SRAM_U — Accessible by the system bus of the core and by the backdoor port. The backdoor port makes the SRAM accessible to the non-core bus masters (such as DMA). S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 671 4 KBytes for the Code Cache. The cache has 32-bit address and data paths and a 16-byte line size. The cache tags and data storage use single- port, synchronous RAMs. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 672 30.4.4.1 Cache set commands The cache set commands may operate on: • all of way 0, • all of way 1, or • all of both ways (complete cache). S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 673 After a reset, complete an invalidate cache command before using the cache. It is possible to combine the cache invalidate command with the cache enable. That is, setting CCR to 0x8500_0001 will invalidate the cache and enable the cache. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 674 Search by physical address Invalidate by physical address Push by physical address Clear by physical address Write by cache address and way Reserved, NOP Reserved, NOP Reserved, NOP Reserved, NOP S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 675 For line commands with physical addresses, this information is read on a hit before the line command action is performed from the hit cache line or has initial valid bit S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 676 For line commands, CLCR[TDSEL] selects between tag and data. If the line command used a physical address and missed, the data is don't care. For write commands, the CCVR holds the write data. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 677 31.1.2 Chip-specific register information The reset values of some MSCM registers vary across the products in the S32K1xx series. The following table shows these reset values for each product. Table 31-1. MSCM register reset values Register S32K116 S32K118 S32K142 S32K144 S32K146...
Page 678 31.4 MSCM Memory Map/Register Definition S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 679 Processor X Count Register (CPxCOUNT) 0000_0000h Processor X Configuration Register 0 (CPxCFG0) description. Processor X Configuration Register 1 (CPxCFG1) description. Processor X Configuration Register 2 (CPxCFG2) description. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 680 CPxTYPE value(s) for this device: • If CPU0 is making the access = 0x434D3401 • If the read access is not from a CPU, then the value read is 0x00000000 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 681 The register provides a CPU-specific response indicating the logical processor number of the core making the access. The logical processor number is always 0. If the read access is not from a CPU, then the value read is 0x00000000. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 682 The register provides a CPU-specific response indicating the physical bus master number of the core that is making the access. The 32-bit response defines the physical master number for processor x. • CPxMASTER = 0x00000000 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 683 This read-only field defines the physical bus master number for CPUx. PPMN = 0x00 31.4.2.5 Processor X Count Register (CPxCOUNT) 31.4.2.5.1 Offset Register Offset CPxCOUNT 31.4.2.5.2 Function The register indicates the total number of processor cores in the chip configuration. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 684 The CPxCFG0 register provides a CPU-specific response detailing configuration information, in this case, information on the Level 1 caches (if present). Access: Privileged read-only NOTE Reset values for the Processor X Configuration Register 0: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 685 • if a 4 Kbyte Data Cache, then DCSZ = 0x03 • if an 8 Kbyte Data Cache, then DCSZ = 0x04 • if a 16 Kbyte Data Cache, then DCSZ = 0x05 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 686 • For CPU0 - CPxCFG1 = 0x00000000 • If the read access is not from a CPU, then the value read is 0x00000000 31.4.2.7.3 Diagram Bits L2SZ L2WY Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 687 Reset values for the Processor X Configuration Register 2: • For CPU0 - CPxCFG2 = 0x09010901 • If the read access is not from a CPU, then the value read is 0x00000000 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 688 • if a 64 Kbyte TCMU, then TMUSZ = 0x07 • if a 128 Kbyte TCMU, then TMUSZ = 0x08 • if a 256 Kbyte TCMU, then TMUSZ = 0x09 Reserved. — S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 689 • If the read access is not from a CPU, then the value read is 0x00000000 31.4.2.9.3 Diagram Bits Reset Bits Reset 31.4.2.9.4 Fields Field Function 31-10 Reserved — System Bus Ports Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 690 This field indicates if hardware support for floating point capabilities are supported in the processor. 0b - FPU support is not included. 1b - FPU support is included. 31.4.2.10 Processor 0 Type Register (CP0TYPE) 31.4.2.10.1 Offset Register Offset CP0TYPE S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 691 This read-only field defines the processor revision for CPU0: 0x00 corresponds to the r0p0 core release. 0x01 corresponds to the r0p1 core release. 31.4.2.11 Processor 0 Number Register (CP0NUM) 31.4.2.11.1 Offset Register Offset CP0NUM S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 692 If single core configuration, then CPN = 0 31.4.2.12 Processor 0 Master Register (CP0MASTER) 31.4.2.12.1 Offset Register Offset CP0MASTER 31.4.2.12.2 Function The register provides the physical bus master number of Processor 0. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 693 This read-only field defines the physical bus master number for CPU0 31.4.2.13 Processor 0 Count Register (CP0COUNT) 31.4.2.13.1 Offset Register Offset CP0COUNT 31.4.2.13.2 Function The register indicates the total number of processor cores in the chip configuration. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 694 The CP0CFG0 register provides information on the CPU0 Level 1 caches (if present). Access: Privileged read-only NOTE Reset values for the Processor 0 Configuration Register 0: • CP0CFG0 = 0x04000000 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 695 • if a 128 Kbyte Data Cache, then DCSZ = 0x08 Level 1 Data Cache Ways DCWY This read-only field provides the number of cache ways for the Data Cache. DCWY=0x00 indicates not present. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 696 • if a 2 Kbyte Level 2 Cache, then L2SZ = 0x02 • if a 4 Kbyte Level 2 Cache, then L2SZ = 0x03 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 697 The CP0CFG2 register provides information on CPU0 tightly-coupled local memories (if present). NOTE Reset values for the Processor 0 Configuration Register 2: • CP0CFG2 = 0x09010901 31.4.2.16.3 Diagram Bits TMLSZ Reserved Reset Bits TMUSZ Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 698 • if a 128 Kbyte TCMU, then TMUSZ = 0x08 • if a 256 Kbyte TCMU, then TMUSZ = 0x09 Reserved. — 31.4.2.17 Processor 0 Configuration Register 3 (CP0CFG3) 31.4.2.17.1 Offset Register Offset CP0CFG3 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 699 This field indicates if the Trust Zone capabilities are supported in the processor.. 0b - Trust Zone support is not included. 1b - Trust Zone support is included. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 700 • Privileged writes from other bus masters are ignored. • Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 701 OCMEM Size “Hole”. For on-chip memories that are not fully populated, that is, include a memory “hole” in the upper 25% of the address range, this bit is used. 0b - OCMEMn is a power-of-2 capacity. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 702 110b - OCMEMn is an EEE. 111b - Reserved OCMPU OCMPU OCMEM Memory Protection Unit. This field is reserved for this device. 11-8 OCMEM Control Field 2 OCM2 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 703 (where appropriate). • Privileged 32-bit reads from a processor core or the debugger return the appropriate processor information. • Reads from any other bus master return all zeroes. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 704 OCMEM Valid bit. This read-only field defines the validity (presence) of the on-chip memory 0b - OCMEMn is not present. 1b - OCMEMn is present. Reserved — This Reserved field always has the value of 1. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 705 000b - Reserved 001b - Reserved 010b - Reserved 011b - Reserved 100b - OCMEMn is a Program Flash. 101b - OCMEMn is a Data Flash. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 706 Speculation for Instruction enabled and Speculation for Data disabled Enabled Enabled Speculation for both Instruction and Data enabled Reserved — 31.4.2.20 On-Chip Memory Descriptor Register (OCMDR2) 31.4.2.20.1 Offset Register Offset OCMDR2 408h S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 707 The following table describes the OCMDRn reset values and the associated memory type: OCMDRn Reset Value On-Chip Memory Type OCMDR0 0xDC089000 Program Flash OCMDR1 0xCA08B000 Data Flash OCMDR2 0xC304D000 EEERAM OCMDR3 0x40000000 OCMEM3 not present 31.4.2.20.3 Diagram Bits Reset Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 708 Read-Only. This register bit provides a mechanism to “lock” the configuration state defined by OCMDRn[11:0]. Once asserted, attempted writes to the OCMDRn[11:0] register are ignored until the next reset clears the flag. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 709 101b - OCMEMn is a Data Flash. 110b - OCMEMn is an EEE. 111b - Reserved OCMPU OCMPU OCMEM Memory Protection Unit. This field is reserved for this device. 11-8 Reserved — Reserved — Reserved — S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 710 MSCM Memory Map/Register Definition S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 711 Memory Protection Unit (MPU) Transfers Crossbar Switch Crossbar Switch (AXBS-Lite) Register access Peripheral Bridge Peripheral Bridge (AIPS-Lite) Register controls MSCM OCMC1 field of MSCM registers On-Chip Memory Descriptor Register (OCMDR0) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 712 • Interface between the device and the dual-bank flash memory and FlexMemory: • 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM used as data flash memory. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 713 32.5.1 Default configuration Upon system reset, the FMC is configured to provide a significant level of buffering for transfers from the flash memory or FlexMemory: • For bank 0 and bank 1: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 714 5. Per 64-bit for Data Flash (bank 1), reading the fourth longword, like the second longword, takes only 1 clock due to the 64-bit flash memory data bus. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 715 1 clock each because the data is already available inside the FMC. 32.6 Initialization and application information The FMC does not require user initialization. Flash acceleration features are enabled by default. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 716 Initialization and application information S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 717 System Clock Generator Clock Distribution Transfers Flash Memory Controller Flash Memory Controller (FMC) Register access Peripheral Bridge Peripheral Bridge (AIPS-Lite) 33.1.1 Flash memory types The chip contains these types of flash memory: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 718 FlexRAM is operating as System RAM. 33.1.2 Flash memory sizes The sizes of flash memory types on the chip are: Chips Program Flash FlexNVM FlexRAM S32K116 128 KB 32 KB 2 KB S32K118 256 KB 32 KB 2 KB...
Page 719 • On this chip, the FTFC is always configured in NVM Normal mode. • The chip has no operating conditions in which the FTFC is configured for NVM Special mode. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 720 PFLASH read partition. Below are number of PFLASH read partitions in each device: Table 33-2. PFLASH partitions Chip No. of PFLASH read partitions S32K116 1 (128 KB) S32K118 1 (256 KB) S32K142 1 (256 KB)
Page 721 S32K148) include a separate read partition (see more details below) for the FlexMEM/ DFlash region. The FTFC_2048K_256K6_256K2_4K macro has four read partitions, of which the last partition includes 448kB PFlash and 64kB DFlash/FlexMEM. This last S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 722 448kB PFlash area at the same time as the 64kB DFlash/ FlexNVM area is being access for any reason. The S32K116/FTFC_128K_128K_32K_2K module consists of two NVM read partitions, and one 2kB FlexRAM. One128kB PFlash read partition (non-interleaved 1x128kB), and one 32kB FlexNVM read partition (non-interleaved 1x32kB).
Page 723 • When configured for traditional RAM: • Read and write access possible to the FlexRAM while programming or erasing data in the program or data flash memory S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 724 • ECC Logic to correct single-bit faults and detect multi-bit faults in each NVM flash phrase 33.2.2 Block diagram The block diagram of the FTFC module is shown in the following figure. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 725 512kB PFlash block (interleaved 2x256kB) with one 256kB PFlash block (single 1x256kB non-interleaved block, data path 64-bits) As the FlexNVM is configured for Emulated EEPROM, the associated EFLash disappears from the memory map as shown here: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 726 Block diagram of S32K146/1MB macro showing various FlexNVM DEPART configurations The FlexMEM DEPART rules are the same on the 1MB macro as on the 512kB macro above. The additional read partition in PFlash is shown here: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 727 Block diagram of S32K148/2MB macro showing various FlexNVM DEPART configurations As the FlexNVM is configured for Emulated EEPROM on the 2MB macro, it is a bit different than the other configs. The choice is all 64kB or none: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 728 DEPART configurations As the FlexNVM is configured for Emulated EEPROM, the associated EFLash disappears from the memory map as shown here, same as the other macros (excluding 2MB) but with smaller DFlash. The S32K116/128kB macro is the same as 118, other than the PFlash is reduced to 128kB: S32K1xx Series Reference Manual, Rev.
Page 729 512kB PRAM 512kB PRAM D/EPART configuration command P/D-Flash Memory Mapping (S32K116/128kB) is the same, just switch 256kB with 128 kB 33.2.3 Glossary Command write sequence — A series of MCU writes to the Flash FCCOB register group that initiates and controls the execution of Flash algorithms that are built into the FTFC module.
Page 730 FlexMemory — FTFC configuration that supports data flash, emulated EEPROM, and FlexRAM. FlexNVM Block — The FlexNVM block can be configured to be used as data flash memory, emulated EEPROM backup flash memory, or a combination of both. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 731 Quad-Phrase — 256 bits of data with an aligned quad-phrase having byte-address[4:0] = 00000. RWW— Read-While-Write. The ability to simultaneously read from one memory resource while commanded operations are active in another memory resource. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 732 Data flash protection byte. Refer to the description of the Data Flash Protection Register (FDPROT). 0x0_040E EEPROM protection byte. Refer to the description of the EEPROM Protection Register (FEPROT). Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 733 The contents of the data flash 0 IFR are summarized in the following table and further described in the subsequent paragraphs. The data flash 0 IFR is located within the data flash 0 memory block. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 734 CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 735 Program Flash Protection Registers (FPROT0) description. EEPROM Protection Register (FEPROT) description. Data Flash Protection Register (FDPROT) description. Flash CSEc Status Register (FCSESTAT) Flash Error Status Register (FERSTAT) Flash Error Configuration Register (FERCNFG) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 736 FlexRAM while enabled for EEE, and CCIF stays low until the emulated EEPROM file system has created the associated EEPROM data record. The CCIF flag will also clear upon execution of any CSEc command,and will set upon completion. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 737 CCIF=1 and before the next command has been launched. At some point during the execution of "command-N+1," the previous result is discarded and any previous error is cleared. 33.4.4.1.3 Flash Configuration Register (FCNFG) 33.4.4.1.3.1 Offset Register Offset FCNFG S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 738 FSEC[SEC] field to the unsecure state. Erase Suspend ERSSUSP The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector command while it is executing. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 739 This read-only register holds all bits associated with the security of the MCU and FTFC module. During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 740 01b - MCU security status is secure 10b - MCU security status is unsecure (The standard shipping condition of the FTFC is unsecure.) 11b - MCU security status is secure S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 741 These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details for the definition and use of these bits. 33.4.4.1.6 Flash Common Command Object Registers (FCCOB3 - FCCO S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 742 Some commands return information to the FCCOB registers. Any values returned to FCCOB are available for reading after the FSTAT[CCIF] flag returns to 1 by the memory controller. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 743 1. Refers to FCCOB register name, not register address 33.4.4.1.7 Program Flash Protection Registers (FPROT3 - FPROT0) 33.4.4.1.7.1 Offset For a = 0 to 3: Register Offset FPROTa Dh + (a × 1h) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 744 • A '1' in an FPROT[PROT] bit indicates its corresponding flash protection region is protected Program flash protection register Program flash protection bits FPROT0 PROT[31:24] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 745 In NVM Special mode: All bits of FPROT are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected. Restriction: The user must never write to any FPROT register while a command is running (CCIF=0). S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 746 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 747 FTFC command. Unprotected regions can be changed by both program and erase operations. 33.4.4.1.9.3 Diagram Bits DPROT Reset 33.4.4.1.9.4 Fields Field Function Data Flash Region Protect S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 748 Following is a quick reference mapping CSEc status flags from the FCSESTAT register. Table 33-3. Boot/MAC map to CSEc Status Flags <err code> No Boot Type Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 749 BIN bit is set, an error has been encountered, or the BOOT_MAC value doesn't match. It assumes BOOT_MAC_KEY is present and boot flavor is configured to a secure boot type (serial, parallel, strict). It is cleared upon reset. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 750 This register reports the detection of uncorrected ECC errors during read access to the FTFC module. The DFDIF flag is readable and writable. The unassigned bits read 0 and are not writable. 33.4.4.1.11.3 Diagram Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 751 This register enables the force and interrupt of uncorrected ECC errors detected during read access to the FTFC module. The FDFD and DFDIE bits are readable and writable. The unassigned bits read 0 and are not writable. 33.4.4.1.12.3 Diagram Bits Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 752 Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: • FPROTn — Four registers protect 32 regions of the program flash memory as shown in the following figure S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 753 EEPROM backup Last FlexNVM address Figure 33-5. Data flash protection (2 data flash sizes) • FEPROT — Protects eight regions of the emulated EEPROM memory as shown in the following figure S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 754 When using the CSEc feature set, the EEE Flash configuration must be selected. The user's FlexNVM configuration choice is specified using the Program Partition command described in Program Partition command. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 755 FlexRAM should be limited to maintain the 1:16 ratio of RAM to NVM. The management of total number of records is left to the user. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 756 The user must take appropriate counter measures to prevent data loss in case of an interrupted emulated EEPROM operation. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 757 FTFC Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE] FTFC ECC Error Detection FERSTAT[DFDIF] FERCNFG[DFDIE] Note Vector addresses and their relative interrupt priority are determined at the MCU level. 33.5.4 Flash operation in low-power modes S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 758 (see the FSTAT[RDCOLERR] bit). 33.5.7 Read while write (RWW) The following simultaneous accesses are allowed for devices with FlexNVM: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 759 FTFC command (not related to CSEc) operations are typically used to modify flash memory contents. The next sections describe: • The command write sequence used to set FTFC command parameters and launch execution • A description of all FTFC commands available S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 760 FSTAT are required to initiate the next command: the first write clears the error flags, the second write clears CCIF. 33.5.9.1.3 Command execution and error reporting The command processing has several steps: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 761 FCCOB and FSTAT registers. 4. The FTFC sets the FSTAT[CCIF] bit signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 762 Command Program flash 0 FlexRAM Function 0x00 Read 1s Block × × Verify that a program flash or data flash block is erased. FlexNVM Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 763 IFR are erased then release MCU security. 0x41 Read Once Read 8 bytes of a dedicated 64 byte field in the program flash 0 IFR. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 764 × Program the FlexNVM Partition Code and emulated EEPROM Data Set Size into the data flash IFR. format all emulated EEPROM backup data sectors Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 765 0x49 Erase All Blocks Unsecure × × — × × — 0x80 Program Partition × × × × — — 0x81 Set FlexRAM Function × × × × — — S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 766 Using the preset 'user' and 'factory' margin levels, these commands perform their associated read operations at tighter tolerances than a 'normal' S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 767 This section describes all flash commands that can be launched by a command write sequence. The FTFC sets the FSTAT[ACCERR] bit and aborts the command execution if any of the following illegal conditions occur: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 768 After clearing CCIF to launch the Read 1s Block command, the FTFC sets the read margin for 1s according to Table 33-8 and then reads all locations within the selected program flash or data flash block. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 769 Number of doublephrases to be verified for program flash, phrases for data flash [15:8] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 770 FSTAT[MGSTAT0] 33.5.11.3 Program Check command The Program Check command tests a previously programmed program flash or data flash longword to see if it reads correctly at the specified margin level. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 771 Table 33-14. Margin level choices for Program Check Read Margin Choice Margin Level Description 0x01 Read at 'User' margin-1 and 'User' margin-0 0x02 Read at 'Factory' margin-1 and 'Factory' margin-0 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 772 The protection status is always checked. The targeted flash locations must be currently unprotected (see the description of the FPROT registers) to permit execution of the Program Phrase operation. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 773 Erase Flash Block command aborts setting the FSTAT[ACCERR] bit. The Erase Flash Block command aborts and sets the FSTAT[FPVIOL] bit if any region within the block is protected (see the description of the program flash protection (FPROT) registers and the S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 774 The Erase Flash Sector command aborts if the selected sector is protected (see the description of the S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 775 Erase Flash Sector operation (CCIF is cleared) and the request to suspend the operation again (ERSSUSP is set). This minimum time period is required to ensure that the Erase Flash Sector operation will eventually complete. If the minimum period is continually S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 776 Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 777 ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 33-9. Suspend and resume of Erase Flash Sector operation S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 778 After the Program Section operation has completed, the CCIF flag will set and normal access to the FlexRAM is restored. The contents of the Section Program Buffer is not changed by the Program Section operation. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 779 6. To program additional flash sectors, repeat steps through 4. 7. To restore emulated EEPROM functionality, execute the Set FlexRAM Function command to make the FlexRAM available for emulated EEPROM. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 780 Apply the 'Factory' margin to the normal read-1 level Table 33-26. Read 1s All Blocks command error handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 781 The Read Once command can be executed any number of times. Table 33-28. Read Once command error handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 782 FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] The requested record has already been programmed to a non-erased value FSTAT[ACCERR] Any errors have been encountered during the verify operation. FSTAT[MGSTAT0] S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 783 0x44. When invoked, the erase-all function erases all program flash memory, data flash memory, data flash IFR space, emulated EEPROM backup, and FlexRAM regardless of the state of the FSTAT[ACCERR and FPVIOL] flags or the protection settings. If the S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 784 Verify Backdoor Access Key command are immediately aborted and the FSTAT[ACCERR] bit is (again) set to 1 until a reset of the S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 785 Table 33-36. Erase All Blocks Unsecure command error handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] Any errors have been encountered during erase or program verify operations FSTAT[MGSTAT0] S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 786 2'b10 1 to 10 keys 256 Bytes 2'b11 1 to 20 keys 512 Bytes For non-CSEc enabled parts, the number of User Keys must be configured as 2'b00 (no keys). S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 787 (by configuring SFE as 'enabled' and then using LOAD_KEY to set the new VERIFY_ONLY attribute on that key). The VERIFY_ONLY attribute attribute has no effect if the KEY_USAGE attribute is '0'. See the CMD_LOAD_KEY command for more information on the new attribute. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 788 Table 33-43. Valid FlexNVM partition codes : 256KB, 512kB and 1MB configurations with 64kB FlexNVM FlexNVM Partition Code DEPART Data flash Size (Kbytes) EEPROM-backup Size (Kbytes) (FCCOB5[3:0]) 0000 0011 0100 1000 1010 1011 1100 1. FCCOB5[7:4] = 0000 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 789 Size Code allocates FlexRAM for emulated EEPROM FlexNVM Partition Code allocates space for emulated EEPROM backup, but EEPROM Data FSTAT[ACCERR] Set Size Code allocates no FlexRAM for emulated EEPROM Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 790 • Clear the FCNFG[RAMRDY] and FCNFG[EEERDY] flags 0xFF • Write a background of ones to all FlexRAM locations • Set the FCNFG[RAMRDY] flag 0xAA Complete interrupted EEPROM quick write process Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 791 BO detection code 0x04 will be returned. If the EEPROM quick write activity is interrupted by a reset before writing all quick write records requested with control code S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 792 16, more than 512, or not FSTAT[ACCERR] divisible by 4 (only 32-bit quick writes are allowed) Set if emulated EEPROM system is in quick write mode and writes to the FlexRAM are not FSTAT[ACCERR] 32-bits S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 793 The security state out of reset can be permanently changed by programming the security byte of the flash configuration field. This assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 794 Flash security byte in the Flash Configuration Field. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the program flash protection registers. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 795 (not able to be resumed, also Aborted Erase commands will leave the contents in an indeterminate state). 1. HIS SHE Specification - Secure Hardware Extension Functional Specification; Version 1.0.1; Rev429 from 23.03.2009 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 796 Table 33-51. User keys and RAM_KEY Key Name Key ID Type Size Comments (Bytes) {KBS, Key IDx} SECRET_KEY MASTER_ECU_KEY Non-Volatile BOOT_MAC_KEY Non-Volatile BOOT_MAC Non-Volatile Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 797 (ERC_RNG_SEED) will be set. d. n 2. Run CMD_RND to generate a random number The PRNG uses the PRNG_STATE/KEY and Seed per SHE spec and the AIS20 standard as follows: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 798 2. If any key is write protected then DBG_CHALLANGE/AUTH will not pass due to the write protected key blocking erase of all keys. This also results in negating the capability of S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 799 (128-bits) of data, and by Cipher Block Chaining (CBC) mode for Integer Multiples of 128-bit block sized data. Cipher-based Message Authentication Code (CMAC) generation and verification is also supported by the AES-128 engine, in addition with use of Miyaguchi-Prenell compression function. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 800 ERC_* codes apply to it: • ERC_GENERAL_ERROR. Example: FuncID is not valid • ERC_SEQUENCE_ERROR. Example: CalSeq invalid: continuation a command error - changed command type • ERC_GENERAL_ERROR. Example: Message Length is ==0 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 801 KeyID The FuncID (Function ID) is 8-bits long. Valid values range from 0x01 to 0x16. These are the CSEc commands which follow the same values as the SHE command definition. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 802 NOTE KeyIDx is a 4-bit value. Writing 1's to the upper 4-bits may result in addressing the incorrect key index/slot. Finally the command header also contains 16-bits of Error information. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 803 This is because writing to the command header (any write to any of the bytes 0-3) triggers the macro to lock the PRAM interface so CSEc operation may start. Figure 33-11. Generic PRAM interface S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 804 (blocks of bit length less than the 128-bit block length) for all ENC/DEC commands. While the CSEc module will manage all potential padding for the MAC commands. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 805 PLAIN_TEXT 5 [0:15] PLAIN_TEXT 6 [0:15] PLAIN_TEXT 7 [0:15] Figure 33-13. Encrypt ECB output parameter format 0x01 0x00 0x00 KeyID Error Bits Reserved CIPHER_TEXT 1 [0:15] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 806 Figure 33-14. Encrypt CBC input parameter format 0x02 0x00 0x00 KeyID Error Bits Reserved PAGE_LENG IV [0:15] PLAIN_TEXT 1 [0:15] PLAIN_TEXT 2 [0:15] PLAIN_TEXT 3 [0:15] PLAIN_TEXT 4 [0:15] PLAIN_TEXT 5 [0:15] PLAIN_TEXT 6 [0:15] S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 807 CIPHER_TEXT 8 [0:15] CIPHER_TEXT 9 [0:15] CIPHER_TEXT 10 [0:15] CIPHER_TEXT 11 [0:15] CIPHER_TEXT 12 [0:15] CIPHER_TEXT 13 [0:15] Then continue transferring data in and out until the full CBC operation is complete. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 808 CIPHER_TEXT 7 [0:15] Figure 33-19. Decrypt ECB output parameter format 0x03 0x00 0x00 KeyID Error Bits Reserved PLAIN_TEXT 1 [0:15] PLAIN_TEXT 2 [0:15] PLAIN_TEXT 3 [0:15] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 809 Figure 33-20. Decrypt CBC input parameters 0x04 0x00 0x00 KeyID Error Bits Reserved PAGE_LENG IV [0:15] CIPHER_TEXT 1 [0:15] CIPHER_TEXT 2 [0:15] CIPHER_TEXT 3 [0:15] CIPHER_TEXT 4 [0:15] CIPHER_TEXT 5 [0:15] CIPHER_TEXT 6 [0:15] S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 810 Figure 33-23. Continuation of output parameters 0x04 0x00 0x01 KeyID Error Bits Reserved PLAIN_TEXT 7 [0:15] PLAIN_TEXT 8 [0:15] PLAIN_TEXT 9 [0:15] PLAIN_TEXT 10 [0:15] PLAIN_TEXT 11 [0:15] PLAIN_TEXT 12 [0:15] PLAIN_TEXT 13 [0:15] S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 811 DATA 6 [0:15] DATA 7 [0:15] Figure 33-25. Generate MAC output parameters 0x05 0x00 0x00 KeyID Error Bits Reserved MESSAGE_LENGTH DATA 1 [0:15] DATA 2 [0:15] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 812 For internal NVM space the maximum size of data is limited to be no more that one read partition (512 KB max), or less if the starting address is not the S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 813 MAC being the last entry after all DATA are input, i.e., MAC will be the position of block N+1 for 'N' number of DATA blocks. All padding is to be done according to SHE specification using MESSAGE_LENGTH. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 814 DATA 5 [0:15] DATA 6 [0:15] MAC [0:15] Figure 33-31. Verify MAC output parameters 0x06 0x00 0x00 KeyID Error Bits Reserved MAC Length Reserved MESSAGE_LENGTH Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 815 MESSAGE_LENGTH Verification Data 7 [ 6:15] Status DATA 9 [0:15] DATA 10 [0:15] MAC [0:15] 33.5.13.12 CMD_VERIFY_MAC - CSEc format (pointer method) Figure 33-34. Verify MAC (pointer method) input parameters S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 816 RAM_KEY, the function has to disable the plain key status bit. Table 33-60. LOAD_KEY command details Parameter Direction Width KEY_ID Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_KEY_NOT_AVAILABLE, ERC_KEY_INVALID,ERC_KEY_WRITE_PROTECTED, ERC_KEY_UPDATE_ERROR, ERC_KEY_EMPTY, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 817 DEBUGGER_PROTECTION | KEY_USAGE | WILDCARD } FID (6-bits)|"0...0"94 SFE == 0x01 (VERIFY_ONLY flag is { WRITE_PROTECTION | enabled, enhanced SHE) BOOT_PROGECTION | DEBUGGER_PROTECTION | KEY_USAGE | WILDCARD | VERIFY_ONLY } S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 818 M1 [0:15] M2 [0:15] M3 [0:15] Reserved Figure 33-37. Load key output parameters 0x07 0x00 0x01 KeyID Error Bits Reserved M1 [0:15] M2 [0:15] M3 [0:15] M4 [0:31] M5 [0:15] S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 819 This command is for loading and unloading a RAM_KEY. The reserved fields for security flags and the counter are set to ‘0’. No values other than M1, may leave SHE/CSEc. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 820 Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, , ERC_KEY_INVALID, ERC_KEY_EMPTY, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 33-39. Export RAM_KEY input parameters 0x09 0x00 0x00 KeyID Error Bits Reserved Reserved Figure 33-40. Export RAM_KEY output parameters S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 821 NOTE: The command may need several hundred ms to return Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 33-41. INIT_RNG input parameters 0x0A 0x00 0x00 KeyID Error Bits Reserved Reserved The INIT_RNG command has no return values. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 822 The EXTEND_SEED command has no return values. 33.5.13.18 CMD_RND The CMD_RND command returns a vector of 128 random bits. The random number generator has to be initialized by CMD_INIT_RNG before random numbers can be supplied. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 823 Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_RNG_SEED, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 33-43. CMD_RND input parameters 0x0C 0x00 0x00 KeyID Error Bits Reserved Reserved Table 33-67. CMD_RND Output Parameters 0x0C 0x00 0x00 KeyID Error Bits Reserved RND [0:15] Reserved S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 824 BOOT OK END IF Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_NO_SECURE_BOOT, ERC_BUSY, ERC_GENERAL_ERROR Table 33-69. CMD_BOOT_FAILURE Input Parameters 0x0E 0x00 0x00 KeyID Error Bits Reserved Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 825 BOOT OK BOOT FINISHED SREG BOOT FINISHED END IF Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_NO_SECURE_BOOT, ERC_BUSY, ERC_GENERAL_ERROR Table 33-71. CMD_BOOT_OK Input Parameters 0x0F 0x00 0x00 KeyID Error Bits Reserved Reserved S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 826 KEY_MASTER_ECU_KEY Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_KEY_NOT_AVAILABLE, ERC_MEMORY_FAILURE, ERC_GENERAL_ERROR Figure 33-44. GET_ID input parameters 0x10 0x00 0x00 KeyID Error Bits Reser Reserved CHALLENGE [0:15] Reserved Figure 33-45. GET_ID output parameters S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 827 User BOOT_SIZE (boot code size of data is in the message length in number of bits to run CMAC on each POR), and the ‘flavor’ of boot (strict, serial, parallel, none). The command header fields in Bytes [1:3] are ignored. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 828 Error Codes: ERC_NO_ERROR, ERC_SEQUENCE_ERROR, , ERC_KEY_INVALID,, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 33-46. BOOT DEFINE input parameter format 0x11 0x00 0x00 KeyID Error Bits Reserved Reserved Boot BOOT_SIZE Flavor Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 829 Error Codes : ERC_NO_ERROR, ERC_SEQUENCE_ERROR, ERC_WRITE_PROTECTED, ERC_RNG_SEED, ERC_NO_DEBUGGING, ERC_MEMORY_FAILURE, ERC_BUSY, ERC_GENERAL_ERROR Figure 33-47. DEBUG input parameters 0x12 0x00 0x00 KeyID Error Bits Reserved Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 830 (DFlash), placing the part back into factory status. The command cannot be executed if authentication fails. The command ignores active debugger protection and secure boot protection flags as well as empty keys. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 831 128-bits in length. For this command the PAGE_LENGTH is to be input as the number of 128-bit pages, and the KeyID input is a don't care. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 832 DATA 7 [0:15] Figure 33-52. Continuation of input parameters 0x16 0x00 0x01 KeyID Error Bits Reserved MESSAGE_L ENGTH DATA 8[0:15] DATA 9[0:15] DATA 10 [0:15] Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 833 If a reset occurs while any FTFC command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 834 Functional description S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 835 34.1.3 QuadSPI register reset values Table 34-1. QuadSPI register reset values Register Reset value Module Configuration Register (QuadSPI_MCR) 000F_400C Buffer0 Configuration Register (QuadSPI_BUF0CR) 0000_0003 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 836 Internal sampling (N/1) (Flash B) DQS sampling Internally method generated DQS External DQS Loopback DQS HyperRAM Internal sampling (4x method) (DDR) DQS sampling Internally method generated DQS External DQS Loopback DQS S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 837 34.1.7 Recommended software configuration • QuadSPI operation is restricted to system clock as SPLL. • When switching the system modes between HSRUN and RUN, QuadSPI should be disabled and then re-enabled. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 838 Table 34-2. QuadSPI_MCR[SCLKCFG] bit field description Bit field name Bit field description SCLKCFG[7] Enables input buffer of QSPI pads for SDR and HyperRAM modes Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 839 34.1.11 QuadSPI_SOCCR[SOCCFG] implementation Table 34-3. QuadSPI_SOCCR[SOCCFG] bit field description Bit field name Bit field description SOCCFG[7:0] SOC configuration: Fine delay chain configuration for Flash A Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 840 1: Burst writes are optimized for best system performance. Note this setting treats writes as “imprecise” such that an error response on any beat of the burst is reported on the last beat. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 841 • Support for flash data strobe signal for data sampling in DDR and Single data rate (SDR) mode. • Support for HyperRAM. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 842 • Supports all types of addressing. 34.2.2 Block Diagram The following figure is a block diagram of the Quad Serial Peripheral Interface (QuadSPI) module. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 843 Figure 34-2. QuadSPI Block Diagram 34.2.3 QuadSPI Modes of Operation For power management through IPS interface access and correct config register programming sequences, QuadSPI supports three modes: normal, module disable and stop mode. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 844 Quad Serial Peripheral Interface Serial Communications Clock Write 1 to clear, writing a 1 to this field resets the flag Input output. In this document, I/O lines are also referred as pads. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 845 • Single pad: Single line I/O with one data out and one data in line to/from the serial flash device. • Dual pad: Dual line I/O with two bidirectional I/O lines, driven alternatively by the serial flash device or the QuadSPI module Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 846 Single and Dual Instructions are executed. The module supports driving these inputs to dedicated values. In single I/O mode, QuadSPI drives data on IOFB[0] and expects data on IOFB[1]. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 847 DDR mode. It is also provided as an output signal during write data phase. 34.3.1 Driving External Signals The different phases of the serial flash access scheme are shown in the following figure. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 848 • IDLE: Serial flash device not selected. No interaction with the serial flash device. All IOFx signals driven. • INSTRUCTION: Serial flash device selected. The instruction is sent to the serial flash device. All IOFx signals are driven. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 849 The values of the bits or fields are not changed. The condition term [A or B] indicates that the register or field can be written to if at least one of the conditions is fulfilled. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 850 Buffer1 Configuration Register (QuadSPI_BUF1CR) See section 34.4.2.6/ Buffer2 Configuration Register (QuadSPI_BUF2CR) See section 34.4.2.7/ Buffer3 Configuration Register (QuadSPI_BUF3CR) See section Buffer Generic Configuration Register 34.4.2.8/ 0000_0000h (QuadSPI_BFGENCR) Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 851 Serial Flash B1 Top Address (QuadSPI_SFB1AD) See section 34.4.2.29/ Serial Flash B2 Top Address (QuadSPI_SFB2AD) See section 34.4.2.30/ RX Buffer Data Register (QuadSPI_RBDR0) 0000_0000h Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 852 RX Buffer Data Register (QuadSPI_RBDR19) 0000_0000h 34.4.2.30/ RX Buffer Data Register (QuadSPI_RBDR20) 0000_0000h 34.4.2.30/ RX Buffer Data Register (QuadSPI_RBDR21) 0000_0000h 34.4.2.30/ RX Buffer Data Register (QuadSPI_RBDR22) 0000_0000h Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 853 Look-up Table register (QuadSPI_LUT7) See section 34.4.2.33/ Look-up Table register (QuadSPI_LUT8) See section 34.4.2.33/ Look-up Table register (QuadSPI_LUT9) See section 34.4.2.33/ Look-up Table register (QuadSPI_LUT10) See section Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 854 Look-up Table register (QuadSPI_LUT29) See section 34.4.2.33/ Look-up Table register (QuadSPI_LUT30) See section 34.4.2.33/ Look-up Table register (QuadSPI_LUT31) See section 34.4.2.33/ Look-up Table register (QuadSPI_LUT32) See section Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 855 Look-up Table register (QuadSPI_LUT51) See section 34.4.2.33/ Look-up Table register (QuadSPI_LUT52) See section 34.4.2.33/ Look-up Table register (QuadSPI_LUT53) See section 34.4.2.33/ Look-up Table register (QuadSPI_LUT54) See section Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 856 34.4.2.1 Module Configuration Register (QuadSPI_MCR) The QuadSPI_MCR holds configuration data associated with QuadSPI operation. Write: • SCLKCFG: Disabled Mode • ISD3FB, ISD2FB,ISD3FA, ISD2FA: Disabled Mode • All other fields: Anytime S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 857 Serial Clock Configuration. This field configuration is chip specific. For details, refer to chip-specific SCLKCFG QuadSPI information. It may be used for dividing clocks. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 858 This field is used to enable variable latency feature in the controller. This field is valid for HyperRAM where VAR_LAT_EN Data strobe acts as an output from the memory during the command and address (CA) cycles of a read or Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 859 It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 860 23–17 This field is reserved. Reserved This field is reserved. Reserved IDATSZ IP data transfer size. Defines the data transfer size in bytes of the IP command. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 861 • TCSS = 0.5 SCK clk if N= 0/1 else, N+0.5 SCK clk if N>1, where N is the setting of TCSS. 2. Any update to the TCSS register bits is visible on the flash interface only from the second transaction following the update. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 862 Master ID. The ID of the AHB master associated with BUFFER0. Any AHB access with this master port number is routed to this buffer. It must be ensured that the master IDs associated with all buffers must be different. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 863 MSTRID field of BUF2CR. Any buffer "miss" leads to the buffer being flushed and a serial flash transaction being triggered as per the sequence pointed to by the SEQID field. Write: • QSPI_SR[AHB_ACC] = 0 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 864 MSTRID fields) will be returned an ERROR response. Write: • QSPI_SR[AHB_ACC] = 0 Address: 0h base + 1Ch offset = 1Ch Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 865 "miss" leads to the buffer being flushed and a serial flash transaction being triggered as per the sequence pointed to by the SEQID field. Write: • QSPI_SR[AHB_ACC] = 0 Address: 0h base + 20h offset = 20h Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 866 Write: • QSPI_SR[AHB_ACC] = 0 Address: 0h base + 24h offset = 24h SOCCFG Reset QuadSPI_SOCCR field descriptions Field Description SOCCFG SOC Configuration For details, refer to chip-specific QuadSPI information. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 867 It is the responsibility of the software to ensure that BUF1IND value is not greater than the overall size of the buffer. The hardware does not provide any protection against illegal programming. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 868 • QSPI_SR[AHB_ACC] = 0 Address: 0h base + 38h offset = 38h TPINDX2 Reserved Reset QuadSPI_BUF2IND field descriptions Field Description 31–3 Top index of buffer 2. TPINDX2 Reserved This field is reserved. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 869 The software should ensure that the serial flash address provided in the QSPI_SFAR register or the incoming AHB address lies in the valid flash address range. Write: • QSPI_SR[IP_ACC] = 0 • QSPI_SR[AHB_ACC] = 0 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 870 The Sampling Register allows configuration of how the incoming data from the external serial flash devices are sampled in the QuadSPI module. Write: Disabled Mode Address: 0h base + 108h offset = 108h Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 871 Select sampling at non-inverted clock Select sampling at inverted clock. 4–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reserved This field is reserved. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 872 0x2 would indicate 8 bytes are available. Reserved This field is reserved. 34.4.2.17 RX Buffer Control Register (QuadSPI_RBCT) This register contains control data related to the receive data buffer. Write: • QSPI_SR[IP_ACC] = 0 S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 873 QSPI_SR[RXWE] flag is asserted.The value should be entered as the number of 4-byte entries minus 1. For example, a value of 0x0 would set the watermark to 4 bytes, 1 to 8 bytes, 2 to 12 bytes, and so on. For details, refer to Usage. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 874 TX buffer. The valid bits will be used and the rest of the bits will be discarded. Write: • QSPI_SR[TXFULL] = 0 32-bit write access required S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 875 4Bytes entries minus 1. For example, a value of 0x0 would set the watermark to 4 bytes, 1 to 8 bytes, 2 to 12 Bytes, and so on.For details, refer to Usage. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 876 The QSPI_SR register provides all available status information about SFM command execution and arbitration, the RX Buffer, TX Buffer, and the AHB Buffer. Address: 0h base + 15Ch offset = 15Ch Reserved Reserved Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 877 128 bit data available in TX FIFO for any pop operation; otherwise, QSPI_FR[TBUF] will be set. RX Buffer DMA. Asserted when RX Buffer read out via DMA is active i.e DMA is requested or running. RXDMA Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 878 IP Access. Asserted when transaction currently executed was initiated by IP bus. IP_ACC Module Busy. Asserted when module is currently busy handling a transaction to an external flash device. BUSY S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 879 QuadSPI module. Write: Enabled Mode Address: 0h base + 160h offset = 160h Reserved Reserved Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 880 The IP Command leading to this condition is continued until the number of bytes according to the QSPI_IPCR[IDATSZ] field has been read from the serial flash device. The content of the RX Buffer is not changed. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 881 • A write access occurs to the QSPI_IPCR[SEQID] field and the QSPI_SR[AHBGNT] bit is set. Any command leading to the assertion of the IPGEF flag is ignored. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 882 QuadSPI module from entering Stop Mode or Module Disable Mode when this flag is set. Write: Anytime Address: 0h base + 164h offset = 164h Reserved Reserved Reset AITIE Reserved Reserved TFIE Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 883 QuadSPI_SR[RBDF] flag is set. No RBDF interrupt will be generated RBDF Interrupt will be generated AHB Sequence Error Interrupt Enable: Triggered by ABSEF flags of QSPI_FR ABSEIE Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 884 No IPGEF interrupt will be generated IPGEF interrupt will be generated 3–1 This field is reserved. Reserved Reserved. Transaction Finished Interrupt Enable TFIE No TFF interrupt will be generated TFF interrupt will be generated S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 885 An AHB sequence may be suspended when a high priority AHB master makes an access before the AHB sequence completes the data transfer requested. Address: 0h base + 168h offset = 168h Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 886 Suspended Buffer: Provides the suspended buffer number. Valid only when SUSPND is set to 1'b1 SPDBUF 5–1 This field is reserved. Reserved When set, it signifies that a sequence is in suspended state SUSPND S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 887 This is a self-clearing field. 7–1 This field is reserved. Reserved Reserved. Buffer Pointer Clear: BFPTRC 1: Clears the sequence pointer for AHB accesses as defined in QuadSPI_BFGENCR. This is a self-clearing field. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 888 • QSPI_SR[AHB_ACC] = 0 Address: 0h base + 184h offset = 184h TPADA2 Reserved Reset * Notes: • TPADA2 field: See the module configuration for the device specific reset values. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 889 The QSPI_SFB2AD register provides the address mapping for the serial flash B2.The difference between QSPI_SFB2AD[TPADB2] and QSPI_SFB1AD[TPADB1] defines the size of the memory map for serial flash B2. Write: • QSPI_SR[IP_ACC] = 0 • QSPI_SR[AHB_ACC] = 0 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 890 RX Data. The RXDATA field contains the data associated with the related RX Buffer entry. Data format and byte ordering is given in Byte Ordering of Serial Flash Read Data S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 891 Setting both the LOCK and UNLOCK bits as "00" or "11" is not allowed. Write: Just after writing the LUT Key Register (QSPI_LUTKEY) Address: 0h base + 304h offset = 304h Reserved Reset Reserved Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 892 Address: 0h base + 310h offset + (4d × i), where i=0d to 63d INSTR1 PAD1 OPRND1 Reset INSTR0 PAD0 OPRND0 Reset * Notes: • The reset values for LUT0 and LUT1 are 0818_0403h and 2400_1C08h respectively. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 893 Any access to the address space between TOP_ADDR_MEMB1(T B1 (the first of the two independent TOP_ADDR_MEMB1 and TOP_ADDR_MEMA2 will be PADB1) routed to Serial Flash B1 flashes sharing the IOFB) Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 894 TOP_ADDR_MEMB2 should be initialized/programmed to TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively (in effect, setting the size of these devices to 0). This would ensure that the complete memory map is assigned to only one flash device. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 895 Serial Flash Byte Address Access Access Device QSPI_AMBA_BASE + 0x00 0x00_0000 to 0x00_0003 QSPI_AMBA_BASE + 0x00 QSPI_AMBA_BASE + 0x04 0x00_0004 to 0x00_0007 … … … Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 896 TOP_ADDR_MEMA2 + 0x04 0x00_0004 to 0x00_0007 … … … TOP_ADDR_MEMB1 - 0x08 (TOP_ADDR_MEMB1- TOP_ADDR_MEMA2 - 0x08) to TOP_ADDR_MEMB1 - 0x08 (TOP_ADDR_MEMB1 - TOP_ADDR_MEMA2 - 0x04 -0x01) Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 897 AHB RX Data Buffer register (ARDB4) 0000_0000h 34.5.4.1/897 AHB RX Data Buffer register (ARDB5) 0000_0000h 34.5.4.1/897 AHB RX Data Buffer register (ARDB6) 0000_0000h 34.5.4.1/897 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 898 RX Buffer, data read via register interface and AHB read, for the description of successive accesses to the RX Buffer content. Refer also to Byte Ordering of Serial Flash Read Data for the byte ordering scheme. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 899 Logical OR from: ipi_int_cerr IPAEF Peripheral access while AHB busy Error IPIEF Peripheral Command could not be triggered Error IPGEF Peripheral access while AHB Grant Error Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 900 This mode is used to allow communication with an external serial flash device. Compared to the standard SPI protocol, this communication method uses up to 4 bidirectional data lines operating at high data rates. The communication to the external S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 901 IP initiated transactions. pads application should ensure 2'd2 - Four that data size pads is a multiple of 2'd3- Eight 8 bytes) pads Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 902 The actual address to be provided to Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 903 The master port number of every incoming request is checked and the data is returned/ fetched into the corresponding associated buffer. Every "missed" access to the buffer causes the controller to clear the buffer and fetch QSPI_BUFxCR[ADATSZ] amount of S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 904 Once the high priority masters access completes, the suspended transaction is resumed (before any other AHB access is entertained). The status of the suspended buffer can be read from Sequence Suspend Status Register (QuadSPI_SPNDST). S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 905 QSPI_BUFxCR[ADATSZ] or data size mentioned in the sequence pointed to by the SEQID field when ADATSZ is programmed as zero. A few examples are shown in the figure below: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 906 Each sequence can have a maximum of 8 instruction-operand pairs. The LUT can hold a maximum of 16 sequences. The figure below shows the basic structure of the sequence in the LUT. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 907 (QuadSPI_LCKCR). Note that this IPS transaction should immediately follow the above IPS transaction (no other IPS transaction can be issued in between). A successful write into this register unlocks the LUT. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 908 • Write the serial flash address to be used by the instruction into QSPI_SFAR, refer to Serial Flash Address Register (QSPI_SFAR). For IP Commands not related to specific addresses, the base address of the related flash need to be S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 909 QSPI_SFACR[CAS] if required to desired value else to 0. Program the QSPI_SFACR[WA] to 1 if the serial flash is a word addressable flash else to 0 in case serial flash is byte addressable. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 910 ID points to a sequence in the LUT. It is the responsibility of the software to ensure that a correct read sequence is programmed in the LUT in accordance with the serial flash device connected on board. The user should S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 911 QSPI_BUFxCR[ADATSZ] field is then fetched from the external serial flash device into the internal AHB Buffer. Since the read access is triggered via the AHB bus, the QSPI_SR[AHB_ACC] status bit is set driving in turn the S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 912 • The RX Buffer is implemented as FIFO of depth 32 entries of 4 bytes. Its content is accessible in two different address areas both referring to the identical data and the same physical memory. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 913 AHB command read is triggered as described above. If the requested data is already available in the AHB Buffer they are provided directly to the host. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 914 • Flash A or Flash B in Individual Flash Mode • All AHB data read commands with access size of 32 bit Table 34-16. Byte Ordering in Individual Flash Mode S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 915 ABOF AHB Sequence Error ABSEF AHB Illegal Transaction Error AITEF AHB Illegal Burst Size Error AIBSEF IP Command Trigger during AHB IPAEF Access Error Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 916 • Buffer Overflow/Underrun Interrupt Request: The Buffer Overflow/Underrun IRQ is a combination of the following flags (all located in the QSPI_FR register with the related enable bits in the QSPI_RSER register): S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 917 TX Buffer fast enough as long as the command is executed without a TX Buffer overflow or underrun. The QuadSPI module sets the QSPI_FR[TBFF] flag so long as the TX Buffer is not full and can accept more data. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 918 Each of the memory vendors have a different way of enabling this mode (Refer to the memory specification from memory vendors). For example, the command B7h sent to Macronix flash will enable it for 32-bit address mode. • Extended Address register S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 919 0x1002. If not in this mode, the incoming address 0x2004 will be mapped to flash location 0x2004. 34.7.3 HyperRAM Support The QuadSPI supports HyperRAM memories and by virtue of this protocol, QuadSPI supports the following functionalities. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 920 This paragraph gives an overview of the different status and flag information available and their interdependencies for different use cases. Related registers are QSPI_SR and QSPI_FR. Refer to the related descriptions how to set up the QuadSPI module appropriately. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 921 • IP Commands - Error Situations Refer to Table 34-19 below. 34.8.2.3 Overview of Error Flags The following table gives an overview of the different error flags in the QSPI_FR register and additional error-related details. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 922 Buffer Related Error TBUF Note that only the buffer related errors are related to a transaction on the external serial flash. All the other errors do not trigger an actual transaction. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 923 IP Command has been finished and the RX Buffer readout has been finished as well. The QSPI ARDB Buffers access the Rx buffer i.e the S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 924 • During the execution of an AHB Command, the running AHB Command can't be terminated by issuing an IP Command. The command is ignored and the QSPI_FR[IPAEF] flag is asserted. Refer to Flag Register (QuadSPI_FR ) for the description of these flags. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 925 For the complete description of the DMA module refer to the related DMA Controller chapter. In this paragraph only the details specific to the DMA usage related to the QuadSPI module are given. 34.8.6.1 DMA Usage in Normal Mode S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 926 Minor Loop for 80Mhz Bus clock Frequency 6 + (4+3) /2 + (16/4)*2 + 2 = ~333ns 6 + (8+3) /2 + (32/4)*2 + 2 = ~500ns Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 927 DMA to read out the RX buffer entries should be smaller than the time taken by the controller to push in the remaining entries in the buffer. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 928 TX Buffer entry(setup of command and address not considered): 8 cycles for Octal DDR mode (Hyperflash/HyperRAM) instructions in Individual Flash Mode, 32 cycles for Quad SDR writes in individual flash mode. • Overhead due to clock domain crossing : 1 cycle. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 929 64 bit format on the AHB bus and 32 bit format on the IPS interface when read via the RX buffer and written in 32 bit format when written via the TX buffer. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 930 34.9.1 Programming Flash Data CPU write instructions to the QSPI_TBDR register like • Write QSPI_TBDR -> 0x01_02_03_04 • Write QSPI_TBDR -> 0x05_06_07_08 result in the following content of the TX Buffer: S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 931 • Read QSPI_RBDR1 <- 0x05_06_07_08 34.9.2.2 Readout of the RX Buffer via ARDBn The RX Buffer content appears at read access on the AMBA AHB interface at the QuadSPI module boundary: S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 932 IOFA[2], IOFB[3] and IOFB[2] in quad mode. For easy interfacing the outputs IOFA[3:2] for Flash A and the IOFB[3:2] for Flash B are driven to the logic state given by the configuration bits QSPI_MCR[ISD3FA], QSPI_MCR[ISD2FA], QSPI_MCR[ISD3FB] and QSPI_MCR[ISD2FB]. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 933 QuadSPI module. Table 34-32. Read Command (Spansion Hyperflash/HyperRAM) INSTR OPERAND COMMENT CMD_DDR 0xA0 Read command with continuous burst type ADDR_DDR 0x18 24 bit row address Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 934 0x10 16 bit column address with lower 3 bits valid rest 0 DUMMY 0x0F 15 dummy cycles READ_DDR 32 bit data read on 8 pads STOP 0x00 STOP, Instruction over S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 935 8 bit address 00h treated as command CMD_DDR 0x00 8 bit address 00h treated as command CMD_DDR 0xAA 8 bit address AAh treated as command Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 936 The following table shows the Fast Dual I/O DT read sequence for Macronix flashes. Table 34-36. Fast Dual I/O DT Read sequence Instruction Operand Comment 0xBD Fast Dual I/O DT read command = 0xBD Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 937 When in XIP mode the software should ensure that all the flashes connected to the controller are in XIP mode. As a part of initializing the controller, all the flashes may be enabled with XIP by carrying out dummy reads. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 938 The following table shows the Read status register sequence for Macronix/Spansion/ Numonyx/Winbond flashes. Table 34-41. Read Status Register Sequence Instruction Operand Comment 0x05 Read status register command = 0x05 READ 0x01 Read status register data STOP 0x00 STOP, Instruction over S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 939 3. Clock to data out delay of the external serial flash device, including input and output delays 4. Wire delay of application/PCB from the external serial flash device to the device containing the QuadSPI module 5. Device delay corresponding to the input data S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 940 This mode may not be available on this chip. See the chip- specific QuadSPI information for the read modes that this chip supports. QuadSPI uses different edges of the internal reference clock for sampling the input data in SDR mode. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 941 • Theoretically there should be two settings possible to capture the correct data, since the serial flash output is valid for 1 clock cycle, disregarding rise and fall times and timing uncertainties. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 942 QuadSPI information for the read modes that this chip supports. Data sampling in DDR mode can be supported using DQS method. Refer to Data Strobe (DQS) sampling method for more details. 34.12.3 Data Strobe (DQS) sampling method S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 943 Figure 34-10. Data Strobe functionality in SDR mode When using DQS for DDR reads, QuadSPI internally samples the incoming data on both the edges of the strobe signal. Refer to the figure below for more detail. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 944 QuadSPI module. This internally generated data strobe signal can be used by QuadSPI to capture the data in: • SDR mode • DDR mode Refer to QuadSPI chip-specific information for additional details about internally generated DQS. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 945 Data Strobe Signal* Data Data sampled on both the edges of Data Strobe Signal RWDS for Spansion's HyperFlash with latency in between Figure 34-12. Data Strobe functionality with latency included S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 946 QuadSPI, if it is 1, then, the data is aligned to 2x internal reference half clock. QSPI_FLSHCR[TDH] Internal Ref clock 2x Internal Ref clock Data aligned to internal Ref clock Data aligned to 2x half clock Figure 34-13. Data Hold S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 947 The two primary modes of operation are Run, Stop. The Wait For Interrupt (WFI) instruction invokes Stop modes for the chip. The available power modes allow an application to consume only the power that is necessary for execution. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 948 • All SRAM is operational (content is retained and I/O states are maintained). 1. HSRUN mode is not available in S32K11x series of devices. NOTE Before disabling a module, its interrupts and DMA requests should be disabled. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 949 Stop mode, but the bus slaves clocked by the bus clock remain in Run mode. The clock generators in the SCG and the PMC's on-chip regulator also remain in Run mode. The following can initiate an exit from STOP. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 950 Stop mode, then requesting bus slaves to enter Stop mode. In Stop and VLPS modes, the SCG and PMC would then also enter their appropriate modes. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 951 VLPS mode. CPO does not affect the SCG, PMC, SRAM, and flash memory read port, although the flash memory register interface is disabled. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 952 (or CPO), instead of waiting for the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it can be used to disable selected bus masters or slaves that should remain inactive during a DMA wake-up. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 953 VLPR modes offer a lower power operating mode than normal modes. VLPR is limited in frequency. Any RESET HSRUN VLPR VLPS STOP1/ STOP2 Figure 35-1. Power mode state transition diagram NOTE Figure 36-1 in the SMC chapter for more detailed mode transition conditions. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 954 No FTFC commands of any type, including CSE commands (for CSEc parts), are available when the chip is in these modes. 35.8 Module operation in available low power modes Table 35-4 illustrates module functionality in each of the available modes. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 955 STOP1, FF in STOP2 FF (Only SIRC and Static in LPO Clock as STOP1, FF in source) STOP2 Clocks 128 kHz LPO Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 956 FlexMemory (FlexRAM Low power (read Low power (no Low power (no read and as traditional SRAM) and write read and write) write) operation) Communication interfaces Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 957 STOP1, FF in STOP2 Analog 12-bit ADC OFF in STOP1, FF in STOP2 LS compare only HS or LS LS compare only compare FF in STOP2 Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 958 S32K148 is being used for an application not using QuadSPI, Ethernet, and SAI, then the on chip voltage monitor ensures the operation as per the specifications present in the S32K1xx Datasheet (See table LVR, LVD and POR operating requirements). S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 959 ARM CPU mode and the MCU power modes. RUN is mapped to RUN/VLPR and Deep Sleep is mapped to STOP/VLPS. ARM CPU mode MCU mode Deep Sleep Stop/VLPS S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 960 NOTE If the system clock is changed during the mode transition, the recommendation is to stall the communications for all the peripherals. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 961 Stop Control Register (SMC_STOPCTRL) 0000_0003h 36.3.5/967 Power Mode Status register (SMC_PMSTAT) 0000_0001h 36.3.6/968 36.3.1 SMC Version ID Register (SMC_VERID) Address: 0h base + 0h offset = 0h MAJOR MINOR FEATURE Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 962 Feature Specification Number This read only field returns the feature set number. 0x0000 Standard features implemented 36.3.2 SMC Parameter Register (SMC_PARAM) Address: 0h base + 4h offset = 4h Reset Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 963 For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is still in Normal Run mode. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 964 This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 965 Chip POR. It is unaffected by reset types that do not trigger Chip POR. See the Reset section details for more information. Address: 0h base + Ch offset = Ch Reset RUNM STOPM Reset S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 966 NOTE: When set to STOP, the STOPO bits in the STOPCTRL register must be used to select the variants of stop - STOP1/STOP2. Normal Stop (STOP) Reserved Very-Low-Power Stop (VLPS) Reserved Reserved Reseved Reserved S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 967 In STOP2, only system clocks are gated allowing peripherals running on bus clock to remain fully functional. In STOP1, both system and bus clocks are gated. Reserved Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 968 This read-only field is reserved and always has the value 0. PMSTAT Power Mode Status NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 969 The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. Any RESET HSRUN VLPR VLPS STOP1/ STOP2 Figure 36-1. Power mode state diagram S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 970 The SMC manages the system's entry into and exit from all power modes. This diagram illustrates the connections of the SMC with other system components in the chip that are necessary to sequence the system through all power modes. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 971 STOP2 mode bus clocks will not be gated. 5. Additionally, for VLPS mode, clock generators are disabled in the SCG unless configured to be enabled. See for the programming options. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 972 RUN and VLPR mode clocking configuration. 36.4.3 Run modes The run modes supported by this device can be found here. • Run (RUN) • Very Low-Power Run (VLPR) • High Speed Run (HSRUN) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 973 When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode. If a higher execution frequency is desired, poll PMSTAT until it is set to RUN when returning from VLPR mode. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 974 HSRUN mode. To reenter normal RUN mode, clear PMCTRL[RUNM]. Any reset also clears PMCTRL[RUNM] and causes the system to exit to normal RUN mode after the MCU exits its reset flow. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 975 In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. A module capable of providing an asynchronous interrupt to the device takes the device out of VLPS and returns the device to VLPR mode. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 976 • the SCG-generated clock source is enabled, • all system clocks, except the core clock, are disabled, • the debug module has access to core registers, and • access to the on-chip peripherals is blocked. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 977 • Low voltage reset (LVR) • Low voltage detect supporting two low voltage trip points and interrupt • Low power oscillator (LPO) with a typical frequency of 128 kHz 37.4 Modes of Operation S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 978 If supply level is higher than LVW threshold then this flag stay cleared, else this flag gets set. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 979 This sections provides the detailed information of all registers for the PMC module. 37.6.1 PMC register descriptions NOTE Different portions of PMC registers are reset only by particular reset types. Each register's description provides details. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 980 This register contains status and control bits to support the low voltage detect function. NOTE When the internal voltage regulator is in lowe power mode, the LVD system is disabled, regardless of the PMC_LVDSC1 settings. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 981 1b - If the supply voltage falls below V , a system reset will be generated. Reserved — 37.6.1.3 Low Voltage Detect Status and Control 2 Register (LVDSC2) 37.6.1.3.1 Offset Register Offset LVDSC2 S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 982 This bit enables hardware interrupt requests for LVWF. 0b - Hardware interrupt disabled (use polling) 1b - Request a hardware interrupt when LVWF=1 Reserved — 37.6.1.4 Regulator Status and Control Register (REGSC) S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 983 0b - Regulator is in low power mode or transition to/from 1b - Regulator is in full performance mode Clock Bias Disable Bit CLKBIASDIS Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 984 Table 37-1. Trimming effect of LPOTRIM[4:0] LPOTRIM[4:0] Decimal Period of LPO clock 10000 –16 lowest 10001 –15 increasing 11110 –2 11111 –1 00000 typical 128 kHz 00001 increasing 01110 01111 highest S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 985 37.6.1.5.4 Fields Field Function Reserved — LPO trimming bits LPOTRIM These bits are used for trimming the frequency of the low power oscillator. See the table above for trimming effect. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 986 Memory Map and Register Definition S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 987 For details regarding a specific ADC channel available on a particular package, see Introduction. Table 38-1. ADC external channels per package Chip Package ADC0 ADC1 S32K116 32 QFN 48 LQFP S32K118 48 LQFP 64 LQFP S32K142 64 LQFP...
Page 988 Table 38-2. ADCx_SC1n[ADCH] field configurations Chip ADCx_SC1n[ADCH] range ADCx_SC1n[ADCH] configuration for module disabled S32K116 00000 b - 11111 b 11111 b S32K118 00000 b - 11111 b 11111 b...
Page 989 The TRGMUX will provide user a more flexible DMA triggering scheme using software based on different application requirements, for example, the DMA can be triggered after multiple ADC conversion completion instead of every ADC conversion completion. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 990 • ADC1_SE8 and ADC0_SE8 channels are interleaved on PTB13 pin • ADC1_SE9 and ADC0_SE9 channels are interleaved on PTB14 pin PTB0 PTB1 ADC0 PTB13 PTB14 AD14 AD15 ADC1 Figure 38-1. ADC0 and ADC1 hardware interleaved channels integration S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 991 CPU involvement is not necessary. • Minimum one external pin per ADC (supported via the TRGMUX) • Software must determine relative priority • Starts conversion after a single ongoing conversion complete S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 992 SIM_ADCOPT[ADC1TRGSEL], each PDB supports upto four ADC channels, and each channel supports 8 pre-triggers. The triggers of ADC channels are OR’ed together to support up to 32 pre-triggers if necessary. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 993 * The block depicts simplified schematic and doesn’t show detailed latching. See section 'Trigger Latching and Arbitration' of ADC chapter for details Figure 38-2. ADC0_PDB0 ADC Triggering scheme example NOTE While using TRGMUX, only LPIT supports pretriggers. For other peripherals, software pretriggers need to be configured using SIM_ADCOPT[ADCxSWPRETRG]. S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 994 ADHWTS A:P ADC0 ADC_SC1A:P[COCO] Configured using TRGMUX_PDB0 and TRGMUX_PDB1 (Same configuration used for PDB0 and PDB1) ADHWT PDB1 ADHWTS A:P ADC1 trigger_in0 ADC_SC1A:P[COCO] Figure 38-4. ADC triggering with same source S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 995 4. Change the selections for desired source and then 5. Start the new trigger generation units If it is required to switch immediately 1. Stop the current trigger generation unit S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 996 TRGMUX). Case 2: Changing the trigger source/multiplexer control: a. Stop the trigger generation module (PDB or TRGMUX). b. Do one of the following options: Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 997 Wait for the latched triggers to be processed and the trigger handler to be idle (poll the status of ADC_SC2[TRGSTLAT] for all 0s). Table continues on the next page... S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 998 ADC conversion, an internal lock associated with the corresponding pre-trigger is activated. This lock becomes inactive when receiving the COCO signal from the ADC. S32K1xx Series Reference Manual, Rev. 4, 06/2017 Preliminary NXP Semiconductors...
Page 999 Figure 38-5. PWM Load Diagnosis – ADC Trigger Concept (block diagram) FTM_init_trig PDB_trigger_in0 PDB_ch0_pretrigger0/ADHWTS A PDB_ch0_pretrigger1/ADHWTS B ADC channel selection PDB_ch0_pretrigger2/ADHWTS C PDB_ch0_pretrigger3/ADHWTS D PDB_ch0_trigger/ADHWT ADHWT Figure 38-6. Example: PWM Load Diagnosis – ADC Trigger Concept 1 (Timing) S32K1xx Series Reference Manual, Rev. 4, 06/2017 NXP Semiconductors Preliminary...
Page 1000 After a POR, and after the flash memory has been made available, the ADC calibration must be executed by use of the CAL bit in the ADC_SC3 control register. S32K1xx Series Reference Manual, Rev. 4, 06/2017 1000 Preliminary NXP Semiconductors...

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