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Nuvoton NuMicro NUC029 Series Technical Reference Manual

Nuvoton NuMicro NUC029 Series Technical Reference Manual

32-bit arm cortex-m0 microcontroller

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NuMicro® NUC029LEE/NUC029SEE

®

®

32-bit Arm

Cortex

-M0 Microcontroller

NuMicro® NUC029 Series

NUC029LEE/NUC029SEE

Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

®

Nuvoton is providing this document only for reference purposes of NuMicro

microcontroller based system

design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Aug, 2018

Page 1 of 497

Rev 1.00

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Page 1 NUC029LEE/NUC029SEE Technical Reference Manual The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. ® Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design.
Page 2: Table Of Contents
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller TABLE OF CONTENTS LIST OF FIGURES ..................... 7 LIST OF TABLES ..................... 11 1 GENERAL DESCRIPTION ................... 12 2 FEATURES ......................13 3 ABBREVIATIONS ....................16 4 PARTS INFORMATION LIST AND PIN CONFIGURATION ........ 18 NUC029 Series Selection Code ...........
Page 3 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.3.5 Register Map ..................119 6.3.6 Register Description ................. 120 6.4 Flash Memory Controller (FMC) ............. 142 6.4.1 Overview ....................142 6.4.2 Features ....................142 6.4.3 Block Diagram ..................143 6.4.4 Functional Description ................144 6.4.5 Register Map ..................
Page 4 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.8.4 Basic Configuration .................. 236 6.8.5 Functional Description ................236 6.8.6 Register Map ..................239 6.8.7 Register Description ................. 241 6.9 PWM Generator and Capture Timer (PWM) ..........250 6.9.1 Overview ....................250 6.9.2 Features ....................
Page 5 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.12.7 Register Description ................. 320 6.13 UART Interface Controller (UART) ............336 6.13.1 Overview ....................336 6.13.2 Features ....................336 6.13.3 Block Diagram ..................337 6.13.4 Basic Configuration .................. 338 6.13.5 Functional Description ................339 6.13.6 Register Map ..................
Page 6 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.16.7 Register Description ................. 455 6.17 Analog-to-Digital Converter (ADC) ............472 6.17.1 Overview ....................472 6.17.2 Features ....................472 6.17.3 Block Diagram ..................473 6.17.4 Basic Configuration .................. 473 6.17.5 Functional Description ................474 6.17.6 Register Map ..................
Page 7 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller LIST OF FIGURES ® Figure 4.1-1 NuMicro NUC029 Series Selection Code ..............18 ® Figure 4.3-1 NuMicro NUC029SEE LQFP 64-pin Diagram ............20 ® Figure 4.3-2 NuMicro NUC029LEE LQFP 48-pin Diagram ............21 ®...
Page 8 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Figure 6.9-5 PWM Generator 4 Clock Source Control..............254 Figure 6.9-6 PWM Generator 4 Architecture Diagram ..............254 Figure 6.9-7 Legend of Internal Comparator Output of PWM-Timer ........... 255 Figure 6.9-8 PWM-Timer Operation Timing ................. 256 Figure 6.9-9 PWM Edge-aligned Interrupt Generate Timing Waveform ........
Page 9 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Figure 6.13-16 UA_BAUD Update Sequence in Automatic Resynchronization Mode when LINS_DUM_EN (UA_LIN_CTL[3])= 0 ................... 355 Figure 6.13-17 RS-485 RTS Driving Level in Auto Direction Mode ..........358 Figure 6.13-18 RS-485 RTS Driving Level with Software Control ..........358 Figure 6.13-19 Structure of RS-485 Frame .................
Page 10 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Figure 6.16-1 USB Device Block Diagram ................... 448 Figure 6.16-2 Wake-up Interrupt Operation Flow ............... 450 Figure 6.16-3 Endpoint SRAM Structure ..................451 Figure 6.16-4 Setup Transaction Followed by Data IN Transaction ..........452 Figure 6.16-5 Data Out Transfer ....................
Page 11: List Of Tables
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller LIST OF TABLES Table 4.1-1 List of Abbreviations....................17 Table 6.2-1 Address Space Assignments for On-Chip Controllers ..........33 Table 6.2-2 Exception Model ......................80 Table 6.2-3 System Interrupt Map ....................81 Table 6.2-4 Vector Table Format ....................
Page 12: General Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GENERAL DESCRIPTION ® ® ® The NuMicro NUC029LEE/NUC029SEE of NUC029 series is embedded with the ARM Cortex M0 core running up to 72 MHz and features 128 Kbytes flash, 16K bytes SRAM, and 8 Kbytes loader ROM for the ISP.
Page 13: Features
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller FEATURES ® ®  ARM Cortex -M0 core – Runs up to 72 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority –...
Page 14 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller – 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source) – Wake-up from Power-down or Idle mode – Interrupt or reset selectable on watchdog time-out – Supports 4 selectable Watchdog Timer reset delay period(1026, 130, 18 or 3 WDT_CLK) ...
Page 15 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller the bus – Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus – Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer –...
Page 16: Abbreviations
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ABBREVIATIONS Acronym Description ACMP Analog Comparator Controller Analog-to-Digital Converter Advanced Encryption Standard Advanced Peripheral Bus Advanced High-Performance Bus Brown-out Detection Controller Area Network Debug Access Port Data Encryption Standard External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO...
Page 17: Table 4.1-1 List Of Abbreviations
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Serial Peripheral Interface Samples per Second TDES Triple Data Encryption Standard Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID Universal Serial Bus Watchdog Timer WWDT Window Watchdog Timer Table 4.1-1 List of Abbreviations Aug, 2018 Page 17 of 497 Rev 1.00...
Page 18: Parts Information List And Pin Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PARTS INFORMATION LIST AND PIN CONFIGURATION ® 4.1 NuMicro NUC029 Series Selection Code NUC029 CPU core Temperature ARM Cortex M0 N: - 40 ℃ ~ +85℃ E: - 40 ℃ ~ +105℃ Package Type Flash Size A: Less than 68K...
Page 19: Nuc029 Series Selection Guide
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ® 4.2 NuMicro NUC029 Series Selection Guide Connectivity √ NUC029FAE Conf TSSOP20 -40 to +105 √ √ QFN33(4*4) NUC029TAN -40 to +85 √ √ QFN33(5*5) NUC029ZAN -40 to +85 √ √ √...
Page 20: Pin Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 4.3 Pin Configuration ® 4.3.1 NuMicro NUC029LEE/NUC029SEE Pin Diagram ® 4.3.1.1 NuMicro NUC029SEE LQFP 64 pin (7 mm * 7mm) AD8/ADC5/PA.5 PB.9/TM1/UART2_TXD AD7/ADC6/PA.6 PB.10/TM2/UART2_RXD PB.11/TM3/PWM4 PE.5/TM1_EXT/TM1/PWM5 AD5/ADC7/PC.7 PC.0/SPI0_SS0 AD4/ADC8/PC.6 PC.1/SPI0_CLK AD3/ADC9/PC.15 PC.2/SPI0_MISO0 NUC029SEE AD2/ADC10/PC.14...
Page 21: Figure 4.3-2 Numicro
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ® 4.3.1.2 NuMicro NUC029LEE LQFP 48 pin (7 mm * 7mm) ADC5/PA.5 PC.0/SPI0_SS0 ADC6/PA.6 PC.1/SPI0_CLK PC.2/SPI0_MISO0 PC.3/SPI0_MOSI0 ADC7/PC.7 PB.3/UART0_nCTS/TM3_EXT/TM3 NUC029LEE ADC8/PC.6 PB.2/UART0_nRTS/TM2_EXT/TM2 LQFP 48-pin ADC11/TM0/TM0_EXT/INT1/PB.15 PB.1/UART0_TXD XT1_OUT/PF.0 PB.0/UART0_RXD XT1_IN/PF.1 USB_D+ nRESET USB_D- USB_VDD33_CAP CLKO/TM0/STADC/PB.8...
Page 22: Pin Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 4.4 Pin Description ® 4.4.1 NuMicro NUC029LEE/NUC029SEE Pin Description Pin No. Pin Name Description Type LQFP LQFP 64-pin 48-pin PB.14 General purpose digital I/O pin. INT0 External interrupt0 input pin. EBI Address/Data bus bit0 PB.13 General purpose digital I/O pin.
Page 23 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Pin No. Pin Name Description Type LQFP LQFP 64-pin 48-pin EBI chip select enable output pin LDO_CAP LDO output pin. Power supply for I/O ports and LDO source for internal PLL and digital circuit. Ground pin for digital circuit.
Page 24 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Pin No. Pin Name Description Type LQFP LQFP 64-pin 48-pin PE.5 General purpose digital I/O pin. PWM5 PWM5 output/Capture input. TM1_EXT Timer1 external capture input pin. Timer1 toggle output pin. PB.11 General purpose digital I/O pin.
Page 25 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Pin No. Pin Name Description Type LQFP LQFP 64-pin 48-pin PWM0 PWM0 output/Capture input. AD13 EBI Address/Data bus bit13 ICE_DAT Serial wire debugger data pin. ICE_CLK Serial wire debugger clock pin. Ground pin for analog circuit.
Page 26 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Pin No. Pin Name Description Type LQFP LQFP 64-pin 48-pin ADC8 ADC8 analog input. EBI Address/Data bus bit4 PC.15 General purpose digital I/O pin. ADC9 ADC9 analog input. EBI Address/Data bus bit3 PC.14 General purpose digital I/O pin.
Page 27: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller BLOCK DIAGRAM ® 5.1 NuMicro NUC029LEE/NUC029SEE Block Diagram Memory Timer/PWM Analog Interface 32-bit Timer x 4 12-bit ADC x 12 APROM LDROM 128 KB 8 KB USB PHY PDMA Cortex-M0 72MHz Watchdog Timer DataFlash SRAM...
Page 28: Functional Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller FUNCTIONAL DESCRIPTION ® ® 6.1 ARM Cortex -M0 Core ® The Cortex -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug ®...
Page 29 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller (WFE) instructions, or the return from interrupt sleep-on-exit feature  NVIC: 32 external interrupt inputs, each with four levels of priority Dedicated Non-maskable Interrupt (NMI) input Supports for both level-sensitive and pulse-sensitive interrupt lines Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode ...
Page 30: System Manager
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2 System Manager 6.2.1 Overview System management includes the following sections:  System Resets  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset , multi-functional pin control ...
Page 31: System Power Distribution
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.3 System Power Distribution In this chip, the power distribution is divided into three segments.  Analog power from AV and AV provides the power for analog components operation.  Digital power from V and V supplies the power to the internal regulator which provides a fixed 1.8 V power for digital operation and I/O pins.
Page 32: System Memory Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.4 System Memory Map ® The NuMicro NUC029LEE/NUC029SEE provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the following table. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on-chip ®...
Page 33: Register Lock
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6.2-1 Address Space Assignments for On-Chip Controllers 6.2.5 Register Lock Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation.
Page 34: Auto Trim
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWRCON [4] PD_WU_DLY Wake-Up Delay Counter Enable Bit (Write Protect) PWRCON [3] OSC10K_EN 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Bit (Write Protect) PWRCON [2] OSC22M_EN 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Bit (Write Protect) PWRCON [1] XTL32K_EN...
Page 35 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller according to the accurate LXT (32.768 kHz crystal oscillator) or internal USB synchronous mode, automatically gets accurate HIRC output frequency, 0.25 % deviation within all temperature ranges. For instance, the system needs an accurate 22.1184 MHz clock. In such case, if users do not want to use PLL as the system clock source, they need to solder 32.768 kHz crystal in system, and set FREQSEL (SYS_IRCTCTL[1:0] trim frequency selection) to “01”, and the auto-trim function will be enabled.
Page 36: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value GCR Base Address: GCR_BA = 0x5000_0000 PDID GCR_BA+0x00 Part Device Identification Number Register 0x2014_0018 RSTSRC GCR_BA+0x04...
Page 37: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.8 Register Description Part Device ID Code Register (PDID) Register Offset Description Reset Value PDID GCR_BA+0x00 Part Device Identification Number Register 0x2014_0018 [1] Each part number has a unique default reset value. PDID PDID PDID...
Page 38 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller System Reset Source Register (RSTSRC) This register provides specific information for software to identify this chip’s reset source from last operation. Register Offset Description Reset Value RSTSRC GCR_BA+0x04 System Reset Source Register 0x0000_00XX Reserved Reserved...
Page 39 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller indicate the previous reset source. 0 = No reset from LVR. 1 = The LVR controller had issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0. Watchdog Timer Reset Flag The RSTS_WDT flag is set by the “Reset Signal”...
Page 40 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Peripheral Reset Control Register 1 (IPRSTC1) Register Offset Description Reset Value IPRSTC1 GCR_BA+0x08 Peripheral Reset Control Register 1 0x0000_0000 Reserved Reserved Reserved Reserved EBI_RST PDMA_RST CPU_RST CHIP_RST Bits Description [31:4] Reserved Reserved.
Page 41 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is the same as the POR reset, all the chip controllers are reset and the chip setting from flash are also reload. For the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2 0 = CHIP normal operation.
Page 42 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Peripheral Reset Control Register 2 (IPRSTC2) Setting these bits to 1 will generate asynchronous reset signals to the corresponding module. User needs to set these bits to 0 to release the corresponding module from reset state. Register Offset Description...
Page 43 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 0 = UART0 controller normal operation. 1 = UART0 controller reset. [15:14] Reserved Reserved. SPI1 Controller Reset [13] SPI1_ RST 0 = SPI1 controller normal operation. 1 = SPI1 controller reset. SPI0 Controller Reset SPI0_ RST 0 = SPI0 controller normal operation.
Page 44 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Brown-out Detector Control Register (BODCR) Partial of the BODCR control registers values are initiated by the flash configuration and partial bits are write-protected bit. Programming write-protected bits needs to write “59h”, “16h”, “88h” to address 0x5000_0100 to disable register protection.
Page 45 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller through the voltage of BOD_VL setting. 1 = When Brown-out Detector detects the V is dropped down through the voltage of BOD_VL setting or the V is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled.
Page 46 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Temperature Sensor Control Register (TEMPCR) Register Offset Description Reset Value TEMPCR GCR_BA+0x1C Temperature Sensor Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VTEMP_EN Bits Description [31:1] Reserved Reserved. Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function.
Page 47 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Power-on-Reset Control Register (PORCR) Register Offset Description Reset Value PORCR GCR_BA+0x24 Power-on-reset Controller Register 0x0000_XXXX Reserved Reserved POR_DIS_CODE POR_DIS_CODE Bits Description [31:16] Reserved Reserved. Power-On-Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
Page 48 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIOA Multiple Function Pin and Input Type Control Register (GPA_MFP) Register Offset Description Reset Value GPA_MFP GCR_BA+0x30 GPIOA Multiple Function and Input Type Control Register 0x0000_0000 GPA_TYPE GPA_TYPE GPA_MFP GPA_MFP Bits Description Trigger Function Selection [31:16]...
Page 49 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PA.11 Pin Function Selection Bits EBI_EN (ALT_MFP[11]) and GPA_MFP[11] determine the PA.11 function. (EBI_EN, GPA_MFP11) value and function mapping is as following list. [11] GPA_MFP11 (0, 0) = GPIO function is selected. (0, 1) = I2C1_SCL function is selected.
Page 50 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PA.3 Pin Function Selection Bits EBI_HB_EN[2] (ALT_MFP[18]), EBI_EN (ALT_MFP[11]) and GPA_MFP[3] determine the PA.3 function. (EBI_HB_EN, EBI_EN, GPA_MFP3) value and function mapping is as following list. GPA_MFP3 (0, 0, 0) = GPIO function is selected. (0, 0, 1) = ADC3 function is selected.
Page 51 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIOB Multiple Function Pin and Input Type Control Register (GPB_MFP) Register Offset Description Reset Value GPB_MFP GCR_BA+0x34 GPIOB Multiple Function and Input Type Control Register 0x0000_0000 GPB_TYPE GPB_TYPE GPB_MFP GPB_MFP Bits Description Trigger Function Selection [31:16]...
Page 52 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller (PB11_PWM4, GPB_MFP11) value and function mapping is as following list. (0, 0) = GPIO function is selected. (0, 1) = TM3 function is selected. (1, 1) = PWM4 function is selected. PB.10 Pin Function Selection Bits PB10_S01 (ALT_MFP[0]) and GPB_MFP[10] determine the PB.10 function.
Page 53 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PB3_T3EX (ALT_MFP[27]) and GPB_MFP[3] determine the PB.3 function. (EBI_nWRH_EN, EBI_EN, PB3_TM3, PB3_T3EX, GPB_MFP3) value and function mapping is as following list. (0, 0, 0, 0, 0) = GPIO function is selected. (0, 0, 0, 0, 1) = UART0_nCTS function is selected.
Page 54 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIOC Multiple Function Pin and input Type Control Register (GPC_MFP) Register Offset Description Reset Value GPC_MFP GCR_BA+0x38 GPIOC Multiple Function and Input Type Control Register 0x0000_0000 GPC_TYPE GPC_TYPE GPC_MFP GPC_MFP Bits Description Trigger Function Selection [31:16]...
Page 55 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PC.9 Pin Function Selection Bit GPC_MFP[9] determines the PC.9 function. GPC_MFP9 0 = GPIO function is selected to the pin PC.9. 1 = SPI1_CLK function is selected to the pin PC.9. PC.8 Pin Function Selection Bits EBI_MCLK_EN (ALT_MFP[12]), EBI_EN (ALT_MFP[11]), GPC_MFP[8] determine the PC.8 function.
Page 56 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIOE Multiple Function Pin and Input Type Control Register (GPE_MFP) Register Offset Description Reset Value GPE_MFP GCR_BA+0x40 GPIOE Multiple Function and Input Type Control Register 0x0000_0000 GPE_TYPE GPE_TYPE Reserved Reserved GPE_MFP5 Reserved Bits Description...
Page 57 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIOF Multiple Function Pin and Input Type Control Register (GPF_MFP) Register Offset Description Reset Value GPF_MFP GCR_BA+0x44 GPIOF Multiple Function and Input Type Control Register 0x0000_000X Note: The default value of GPF_MFP[3]/GPF_MFP[2] is 1. The default value of GPF_MFP[1]/GPF_MFP[0] is decided by user configuration CGPFMFP(CONFIG0[27]).
Page 58 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Alternative Multiple Function Pin Control Register (ALT_MFP) Register Offset Description Reset Value ALT_MFP GCR_BA+0x50 Alternative Multiple Function Pin Control Register 0x0000_0000 Reserved PB8_CLKO Reserved PB3_T3EX PB2_T2EX PE5_T1EX PB15_T0EX EBI_HB_EN EBI_nWRH_E EBI_nWRL_E EBI_MCLK_E Reserved EBI_EN...
Page 59 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PB.2 Pin Alternative Function Selection Bits EBI_nWRL_EN (ALT_MFP[13]), EBI_EN (ALT_MFP[11]), PB2_TM2 (ALT_MFP2[4]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function. (EBI_nWRL_EN, EBI_EN, PB2_TM2, PB2_T2EX, GPB_MFP2) value and function mapping is as following list. [26] PB2_T2EX (0, 0, 0 , 0, 0) = GPIO function is selected.
Page 60 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Bit EBI_HB_EN[4] (ALT_MFP[20]), EBI_EN (ALT_MFP[11]) and GPA_MFP[1] determine the PA.1 function. (EBI_HB_EN, EBI_EN, GPA_MFP1) value and function mapping is as following list. [20] EBI_HB_EN[4] (0, 0, 0) = GPIO function is selected. (0, 0, 1) = ADC1 function is selected.
Page 61 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Bits EBI_nWRL_EN (ALT_MFP[13]), EBI_EN (ALT_MFP[11]), PB2_TM2 (ALT_MFP2[4]), PB2_T2EX (ALT_MFP[26]) and GPB_MFP[2] determine the PB.2 function. (EBI_nWRL_EN, EBI_EN, PB2_TM2, PB2_T2EX, GPB_MFP2) value and function mapping is as following list. (0, 0, 0 , 0, 0) = GPIO function is selected. [13] EBI_nWRL_EN (0, 0, 0, 0, 1) = UART0_nRTS function is selected.
Page 62 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Alternative Multiple Function Pin Control Register 2 (ALT_MFP2) Register Offset Description Reset Value ALT_MFP2 GCR_BA+0x5C Alternative Multiple Function Pin Control Register 2 0x0000_0000 Reserved Reserved Reserved Reserved PB3_TM3 PB2_TM2 PE5_TM1 PB15_TM0 PB14_15_EBI Reserved Bits...
Page 63 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PE.5 Pin Alternative Function Selection Bits PE5_T1EX (ALT_MFP[25]), PE5_TM1 (ALT_MFP2[3]) and GPE_MFP5 determine the PE.5 function. (PE5_T1EX, PE5_TM1, GPE_MFP5) value and function mapping is as following list. PE5_TM1 (0, 0, 0) = GPIO function is selected. (0, 0, 1) = PWM5 function is selected.
Page 64 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRC Trim Control Register (SYS_IRCTCTL) Register Offset Description Reset Value IRCTCTL GCR_BA+0x80 IRC Trim Control Register 0x0000_0000 Reserved Reserved CLKERR_ Reserved STOP_EN TRIM_RETRY_CNT TRIM_LOOP Reserved TRIM_SEL Bits Description [31:9] Reserved Reserved. Clock Error Stop Enable Bit CLKERR_STOP_E 0 = The trim operation is kept going if clock is inaccuracy.
Page 65 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller If no any target frequency is selected (TRIM_SEL is 00), the HIRC auto trim function is disabled. During auto trim operation, if clock error detected because of CLKERR_STOP_EN is set to 1 or trim retry limitation counts reached, this field will be cleared to 00 automatically.
Page 66 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRC Trim Interrupt Enable Register (SYS_IRCTIEN) Register Offset Description Reset Value IRCTIEN GCR_BA+0x84 IRC Trim Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved TRIM_FAIL_ Reserved CLKERR_IEN Reserved Bits Description [31:3] Reserved Reserved. Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
Page 67 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRC Trim Interrupt Status Register (SYS_IRCTSTS) Register Offset Description Reset Value IRCTSTS GCR_BA+0x88 IRC Trim Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved TRIM_FAIL_ Reserved CLKERR_INT FREQ_LOCK Bits Description [31:3] Reserved Reserved. Clock Error Interrupt Status When the frequency of external 32.768 kHz low speed crystal or internal 22.1184 MHz high speed oscillator is shift larger to unreasonable value, this bit will be set and to be an...
Page 68 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller HIRC Trim Control Register (SYS_HIRCTCTL) Register Offset Description Reset Value HIRCTCTL GCR_BA+0x90 HIRC Trim Control Register 0x0008_0000 Reserved Reserved BOUNDARY Reserved BOUNDEN CESTOPEN RETRYCNT LOOPSEL Reserved FREQSEL Bits Description [31:21] Reserved Reserved.
Page 69 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 11 = Trim value calculation is based on average difference in 32 clocks of reference clock. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
Page 70 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller HIRC Trim Interrupt Enable Register (SYS_HIRCTIEN) Register Offset Description Reset Value HIRCTIEN GCR_BA+0x94 HIRC Trim Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKEIEN TFALIEN Reserved Bits Description [31:3] Reserved Reserved. Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
Page 71 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller HIRC Trim Interrupt Status Register (SYS_HIRCTSTS) Register Offset Description Reset Value HIRCTSTS GCR_BA+0x98 HIRC Trim Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved OVBDIF Reserved CLKERIF TFAILIF FREQLOCK Bits Description [31:4] Reserved Reserved.
Page 72 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller This bit indicates the HIRC frequency is locked. This is a status bit and doesn’t trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.
Page 73 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Register Write Protection Register (REGWRPROT) This register is write for disable/enable register protection and read for the REGPROTDIS status Register Offset Description Reset Value REGWRPROT GCR_BA+0x100 Register Write Protection Register 0x0000_0000 Reserved Reserved Reserved...
Page 74: System Timer (Systick)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller description. 6.2.9 System Timer (SysTick) ® The Cortex -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, then decrement on subsequent clocks.
Page 75 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.9.1 System Timer Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SYST Base Address: SCS_BA = 0xE000_E000 SYST_CSR SCS_BA+0x10 SysTick Control and Status Register 0x0000_0000 SYST_RVR SCS_BA+0x14...
Page 76 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.9.2 System Timer Control Register Description SysTick Control and Status (SYST_CSR) Register Offset Description Reset Value SYST_CSR SCS_BA+0x10 SysTick Control and Status Register 0x0000_0000 Reserved Reserved COUNTFLAG Reserved Reserved CLKSRC TICKINT ENABLE Bits Description...
Page 77 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SysTick Reload Value Register (SYST_RVR) Register Offset Description Reset Value SYST_RVR SCS_BA+0x14 SysTick Reload Value Register 0xXXXX_XXXX Reserved RELOAD RELOAD RELOAD Bits Description [31:24] Reserved Reserved. [23:0] RELOAD Value to load into the Current Value register when the counter reaches 0. Aug, 2018 Page 77 of 497 Rev 1.00...
Page 78 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SysTick Current Value Register (SYST_CVR) Register Offset Description Reset Value SYST_CVR SCS_BA+0x18 SysTick Current Value Register 0xXXXX_XXXX Reserved CURRENT CURRENT CURRENT Bits Description [31:24] Reserved Reserved. System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The [23:0] CURRENT counter does not provide read-modify-write protection.
Page 79: Nested Vectored Interrupt Controller (Nvic)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.10 Nested Vectored Interrupt Controller (NVIC) ® The Cortex -M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor kernel and provides following features: ...
Page 80: Table 6.2-2 Exception Model
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.10.1 Exception Model and System Interrupt Map ® The following table lists the exception model supported by NuMicro NUC029LEE/NUC029SEE. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest user-configurable priority is denoted as “0”...
Page 81: Table 6.2-3 System Interrupt Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART1_INT UART1 UART1 interrupt SPI0_INT SPI0 SPI0 interrupt SPI1_INT SPI1 SPI1 interrupt Reserved Reserved I2C0_INT C0 interrupt I2C1_INT C1 interrupt Reserved Reserved Reserved USB_INT USBD USB 2.0 FS Device interrupt Reserved Reserved PDMA_INT PDMA...
Page 82 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write- 1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not activate.
Page 83 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.10.4 NVIC Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value NVIC Base Address: SCS_BA = 0xE000_E000 NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ31 Set-enable Control Register 0x0000_0000 NVIC_ICER SCS_BA+0x180...
Page 84 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.10.5 NVIC Control Register Description IRQ0 ~ IRQ31 Set-Enable Control Register (NVIC_ISER) Register Offset Description Reset Value NVIC_ISER SCS_BA+0x100 IRQ0 ~ IRQ31 Set-enable Control Register 0x0000_0000 SETENA SETENA SETENA SETENA Bits Description Interrupt Enable Register Enable one or more interrupts.
Page 85 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER) Register Offset Description Reset Value NVIC_ICER SCS_BA+0x180 IRQ0 ~ IRQ31 Clear-enable Control Register 0x0000_0000 CLRENA CLRENA CLRENA CLRENA Bits Description Interrupt Disable Bits Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Page 86 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ0 ~ IRQ31 Set-Pending Control Register (NVIC_ISPR) Register Offset Description Reset Value NVIC_ISPR SCS_BA+0x200 IRQ0 ~ IRQ31 Set-pending Control Register 0x0000_0000 SETPEND SETPEND SETPEND SETPEND Bits Description Set Interrupt Pending Register Write Operation: 0 = No effect.
Page 87 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ0 ~ IRQ31 Clear-Pending Control Register (NVIC_ICPR) Register Offset Description Reset Value NVIC_ICPR SCS_BA+0x280 IRQ0 ~ IRQ31 Clear-Pending Control Register 0x0000_0000 CLRPEND CLRPEND CLRPEND CLRPEND Bits Description Clear Interrupt Pending Register Write Operation: 0 = No effect.
Page 88 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ0 ~ IRQ3 Priority Register (NVIC_IPR0) Register Offset Description Reset Value NVIC_IPR0 SCS_BA+0x400 IRQ0 ~ IRQ3 Priority Control Register 0x0000_0000 PRI_3 Reserved PRI_2 Reserved PRI_1 Reserved PRI_0 Reserved Bits Description Priority Of IRQ3 [31:30] PRI_3 “0”...
Page 89 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ4 ~ IRQ7 Priority Register (NVIC_IPR1) Register Offset Description Reset Value NVIC_IPR1 SCS_BA+0x404 IRQ4 ~ IRQ7 Priority Control Register 0x0000_0000 PRI_7 Reserved PRI_6 Reserved PRI_5 Reserved PRI_4 Reserved Bits Description Priority Of IRQ7 [31:30] PRI_7 “0”...
Page 90 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ8 ~ IRQ11 Priority Register (NVIC_IPR2) Register Offset Description Reset Value NVIC_IPR2 SCS_BA+0x408 IRQ8 ~ IRQ11 Priority Control Register 0x0000_0000 PRI_11 Reserved PRI_10 Reserved PRI_9 Reserved PRI_8 Reserved Bits Description Priority Of IRQ11 [31:30] PRI_11 “0”...
Page 91 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ12 ~ IRQ15 Priority Register (NVIC_IPR3) Register Offset Description Reset Value NVIC_IPR3 SCS_BA+0x40C IRQ12 ~ IRQ15 Priority Control Register 0x0000_0000 PRI_15 Reserved PRI_14 Reserved PRI_13 Reserved PRI_12 Reserved Bits Description Priority Of IRQ15 [31:30] PRI_15 “0”...
Page 92 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ16 ~ IRQ19 Priority Register (NVIC_IPR4) Register Offset Description Reset Value NVIC_IPR4 SCS_BA+0x410 IRQ16 ~ IRQ19 Priority Control Register 0x0000_0000 PRI_19 Reserved PRI_18 Reserved PRI_17 Reserved PRI_16 Reserved Bits Description Priority Of IRQ19 [31:30] PRI_19 “0”...
Page 93 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ20 ~ IRQ23 Priority Register (NVIC_IPR5) Register Offset Description Reset Value NVIC_IPR5 SCS_BA+0x414 IRQ20 ~ IRQ23 Priority Control Register 0x0000_0000 PRI_23 Reserved PRI_22 Reserved PRI_21 Reserved PRI_20 Reserved Bits Description Priority Of IRQ23 [31:30] PRI_23 “0”...
Page 94 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ24 ~ IRQ27 Priority Register (NVIC_IPR6) Register Offset Description Reset Value NVIC_IPR6 SCS_BA+0x418 IRQ24 ~ IRQ27 Priority Control Register 0x0000_0000 PRI_27 Reserved PRI_26 Reserved PRI_25 Reserved PRI_24 Reserved Bits Description Priority Of IRQ27 [31:30] PRI_27 “0”...
Page 95 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ28 ~ IRQ31 Priority Register (NVIC_IPR7) Register Offset Description Reset Value NVIC_IPR7 SCS_BA+0x41C IRQ28 ~ IRQ31 Priority Control Register 0x0000_0000 PRI_31 Reserved PRI_30 Reserved PRI_29 Reserved PRI_28 Reserved Bits Description Priority Of IRQ31 [31:30] PRI_31 “0”...
Page 96 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.10.6 Interrupt Source Register Map ® Besides the interrupt control registers associated with the NVIC, the NuMicro NUC029LEE/NUC029SEE also implement some specific control registers to facilitate the interrupt functions, including “interrupt source identification”, ”NMI source selection” and “interrupt test mode”, which are described below.
Page 97 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ23_SRC INT_BA+0x5C IRQ23 (USBD) Interrupt Source Identity 0xXXXX_XXXX IRQ24_SRC INT_BA+0x60 Reserved 0xXXXX_XXXX IRQ25_SRC INT_BA+0x64 Reserved 0xXXXX_XXXX IRQ26_SRC INT_BA+0x68 IRQ26 (PDMA) Interrupt Source Identity 0xXXXX_XXXX IRQ27_SRC INT_BA+0x6C Reserved 0xXXXX_XXXX IRQ28_SRC INT_BA+0x70 IRQ28 (PWRWU) Interrupt Source Identity 0xXXXX_XXXX IRQ29_SRC INT_BA+0x74...
Page 98 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.10.7 Interrupt Source Register Description Interrupt Source Identity Register (IRQn_SRC) Register Offset Description Reset Value IRQ0_SRC INT_BA+0x00 IRQ0 (BOD) Interrupt Source Identity 0xXXXX_XXXX IRQ1_SRC INT_BA+0x04 IRQ1 (WDT) Interrupt Source Identity 0xXXXX_XXXX IRQ2_SRC INT_BA+0x08 IRQ2 (EINT0) Interrupt Source Identity...
Page 99 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller IRQ28_SRC INT_BA+0x70 IRQ28 (PWRWU) Interrupt Source Identity 0xXXXX_XXXX IRQ29_SRC INT_BA+0x74 IRQ29 (ADC) Interrupt Source Identity 0xXXXX_XXXX IRQ30_SRC INT_BA+0x78 IRQ30 (IRC) Interrupt Source Identity 0xXXXX_XXXX IRQ31_SRC INT_BA+0x7C IRQ31 (RTC) Interrupt Source Identity 0xXXXX_XXXX Reserved Reserved...
Page 100 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Bit1: 0 Bit0: GPC_INT Bit3: PWM3_INT Bit2: PWM2_INT [3:0] INT_BA+0x18 Bit1: PWM1_INT Bit0: PWM0_INT Bit3: 0 Bit2: 0 [3:0] INT_BA+0x1C Bit1: PWM5_INT Bit0: PWM4_INT Bit2: 0 Bit1: 0 [2:0] INT_BA+0x20 Bit0: TMR0_INT Bit2: 0 [2:0] INT_BA+0x24...
Page 101 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Bit2: 0 [2:0] INT_BA+0x68 Bit1: 0 Bit0: PDMA_INT Bit2: 0 [2:0] INT_BA+0x70 Bit1: 0 Bit0: PWRWU_INT Bit2: 0 [2:0] INT_BA+0x74 Bit1: 0 Bit0: ADC_INT Bit2: 0 [2:0] INT_BA+0x78 Bit1: 0 Bit0: IRC_INT Bit2: 0 Bit1: 0 [2:0]...
Page 102 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller NMI Source Interrupt Select Control Register (NMI_SEL) Register Offset Description Reset Value NMI_SEL INT_BA+0x80 NMI Source Interrupt Select Control Register 0x0000_0000 Reserved Reserved Reserved NMI_EN Reserved NMI_SEL Bits Description [31:8] Reserved Reserved.
Page 103 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller MCU Interrupt Request Source Register (MCU_IRQ) Register Offset Description Reset Value MCU_IRQ INT_BA+0x84 MCU Interrupt Request Source Register 0x0000_0000 MCU_IRQ MCU_IRQ MCU_IRQ MCU_IRQ Bits Description MCU IRQ Source Register The MCU_IRQ collects all the interrupts from the peripherals and generates the ®...
Page 104 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller MCU Interrupt Request Control Register (MCU_IRQCR) Register Offset Description Reset Value MCU_IRQCR INT_BA+0x88 MCU Interrupt Request Control Register 0x0000_0000 Reserved Reserved Reserved Reserved FAST_IRQ Bits Description [31:1] Reserved Reserved. Fast IRQ Latency Enable Bit 0 = MCU IRQ latency is fixed at 13 clock cycles of HCLK, MCU will enter IRQ handler after FAST_IRQ this fixed latency when interrupt happened.
Page 105: System Control
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.11 System Control ® The Cortex -M0 status and operating mode control are managed by System Control Registers. ® ® Including CPUID, Cortex -M0 interrupt priority and Cortex -M0 power management can be controlled through these system control registers.
Page 106 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.2.11.2 System Control Register Description CPUID Register (CPUID) Register Offset Description Reset Value CPUID SCS_BA+0xD00 CPUID Register 0x410C_C200 IMPLEMENTER Reserved PART PARTNO PARTNO REVISION Bits Description Implementer Code Assigned By ARM [31:24] IMPLEMENTER Implementer code assigned by ARM.
Page 107 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Interrupt Control State Register (ICSR) Register Offset Description Reset Value ICSR SCS_BA+0xD04 Interrupt Control and State Register 0x0000_0000 NMIPENDSET Reserved PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR Reserved ISRPREEMPT ISRPENDING Reserved VECTPENDING VECTPENDING Reserved Reserved VECTACTIVE Bits...
Page 108 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Write Operation: 0 = No effect. 1 = Changes SysTick exception state to pending. Read Operation: 0 = SysTick exception is not pending. 1 = SysTick exception is pending. SysTick Exception Clear-Pending Bit Write Operation: 0 = No effect.
Page 109 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Application Interrupt and Reset Control Register (AIRCR) Register Offset Description Reset Value AIRCR SCS_BA+0xD0C Application Interrupt and Reset Control Register 0xFA05_0000 VECTORKEY VECTORKEY Reserved SYSRESETRE VECTCLKAC Reserved Reserved TIVE Bits Description Register Access Key Write Operation: When writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise...
Page 110 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller System Control Register (SCR) Register Offset Description Reset Value SCS_BA+0xD10 System Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SEVONPEND Reserved SLEEPDEEP SLEEPONEXIT Reserved Bits Description [31:5] Reserved Reserved. Send Event On Pending Bit 0 = Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded.
Page 111 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller System Handler Priority Register 2 (SHPR2) Register Offset Description Reset Value SHPR2 SCS_BA+0xD1C System Handler Priority Register 2 0x0000_0000 PRI_11 Reserved Reserved Reserved Reserved Bits Description Priority Of System Handler 11 – SVCall [31:30] PRI_11 “0”...
Page 112 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller System Handler Priority Register 3 (SHPR3) Register Offset Description Reset Value SHPR3 SCS_BA+0xD20 System Handler Priority Register 3 0x0000_0000 PRI_15 Reserved PRI_14 Reserved Reserved Reserved Bits Description Priority Of System Handler 15 – SysTick [31:30] PRI_15 “0”...
Page 113: Clock Controller
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.3 Clock Controller 6.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider.
Page 114: Figure 6.3-1 Clock Generator Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller XTL32K_EN (PWRCON[1]) X32_OUT 32.768 kHz X32_IN XTL12M_EN (PWRCON[0]) XT1_OUT 4~24 MHz PLL_SRC (PLLCON[19]) XT1_IN PLL FOUT OSC22M_EN (PWRCON[2]) 22.1184 MHz HIRC HIRC OSC10K_EN(PWRCON[3]) LIRC 10 kHz LIRC OSC48M_EN(PWRCON[12]) HIRC48 48 MHz HIRC48 Legend: = 32.768 kHz external low speed crystal oscillator...
Page 115: Figure 6.3-2 Clock Generator Global View Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 22.1184 22.1184 MHz CPUCLK 10 kHz 4~24 PLLFOUT 1/(HCLK_N+1) HCLK PDMA 32.768 kHz 32.768 4~24 MHz PCLK I2C 0~1 22.1184 MHz 10 kHz 10 kHz CLKSEL0[2:0] TMR 3 External trigger TMR 2 HCLK 22.1184 MHz TMR 1...
Page 116: System Clock And Systick Clock
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.3.2 System Clock and SysTick Clock The system clock has 5 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is shown in Figure 6.3-3.
Page 117: Power-Down Mode Clock
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.3.3 Power-down Mode Clock When chip enters Power-down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down mode.
Page 118: Figure 6.3-6 Frequency Divider Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller DIVIDER_EN (FRQDIV[4]) Enable divide-by-2 counter FSEL 16 chained (FRQDIV[3:0]) divide-by-2 counter FRQDIV_CLK DIVIDER1 …... CLKO_1HZ_EN (FRQDIV[5]) (FRQDIV[6]) 0000 0001 16 to 1 CLKO 1110 1111 RTC_SEL_10K (CLKSEL2[18]) 32.768 kHz 1Hz clock from RTC /32768 10 kHz Figure 6.3-6 Frequency Divider Block Diagram...
Page 119: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.3.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CLK Base Address: CLK_BA = 0x5000_0200 PWRCON CLK_BA+0x00 System Power-down Control Register 0x0000_001X AHBCLK CLK_BA+0x04...
Page 120: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.3.6 Register Description System Power-down Control Register (PWRCON) Except the BIT[6], all the other bits are protected, programming these bits need to write “59h”, “16h”, “88h” to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100 Register Offset...
Page 121 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller to set this bit again for next Power-down. In Power-down mode, 4~24 MHz external high speed crystal oscillator and the 22.1184 MHz internal high speed RC oscillator will be disabled in this mode, but the 32.768 kHz external low speed crystal oscillator and 10 kHz internal low speed oscillator are not controlled by Power-down mode.
Page 122 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 1 = 32.768 kHz external low speed crystal oscillator (LXT) Enabled (Normal operation). Note: This bit is the protected bit, and programming it needs to write “59h”, “16h”, and “88h” to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
Page 123: Table 6.3-1 Chip Idle/Power-Down Mode Control Table
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Register Or SLEEPDEEP PD_WAIT_CPU PWR_DOWN_EN CPU Run WFI Instruction Clock Disable Instruction (SCR[2]) (PWRCON[8]) (PWRCON[7]) Mode Normal operation All clocks disabled by control register Idle mode Only CPU clock disabled (CPU entering Sleep mode) Power-down mode Most clocks are disabled except...
Page 124 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller AHB Devices Clock Enable Control Register (AHBCLK) These bits for this register are used to enable/disable clock for system clock PDMA clock. Register Offset Description Reset Value AHBCLK CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x0000_0005 Reserved Reserved...
Page 125 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller APB Devices Clock Enable Register (APBCLK) These bits of this register are used to enable/disable clock for peripheral controller clocks. Register Offset Description Reset Value APBCLK CLK_BA+0x08 APB Devices Clock Enable Control Register 0x0000_000X Reserved ADC_EN...
Page 126 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 1 = UART1 clock Enabled. UART0 Clock Enable Bit [16] UART0_EN 0 = UART0 clock Disabled. 1 = UART0 clock Enabled. [15:14] Reserved Reserved. SPI1 Clock Enable Bit [13] SPI1_EN 0 = SPI1 clock Disabled. 1 = SPI1 clock Enabled.
Page 127 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Note: This bit is the protected bit, and programming it needs to write “59h”, “16h”, and “88h” to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. Aug, 2018 Page 127 of 497 Rev 1.00...
Page 128 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Clock status Register (CLKSTATUS) These bits of this register are used to monitor if the chip clock source stable or not, and whether clock switch failed. Register Offset Description Reset Value CLKSTATUS CLK_BA+0x0C Clock Status Monitor Register...
Page 129 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 32.768 KHz External Low Speed Crystallator Oscillator (LXT) Clock Source Stable Flag (Read Only) XTL32K_STB 0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. 1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stable and enabled.
Page 130 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Clock Source Select Control Register 0 (CLKSEL0) Register Offset Description Reset Value CLKSEL0 CLK_BA+0x10 Clock Source Select Control Register 0 0x0000_003X Reserved Reserved Reserved USB_S Reserved STCLK_S HCLK_S Bits Description [31:9] Reserved Reserved.
Page 131 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 001 = Clock source from 32.768 kHz external low speed crystal oscillator clock. 010 = Clock source from PLL clock. 011 = Clock source from 10 kHz internal low speed RC oscillator clock. 111 = Clock source from 22.1184 MHz internalhigh speed RC oscillator clock.
Page 132 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Clock Source Select Control Register 1(CLKSEL1) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLKSEL1 CLK_BA+0x14 Clock Source Select Control Register 1 0xFFFF_FFFF PWM23_S PWM01_S...
Page 133 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM01_S list below:. .00 = Reserved. .01 = Reserved. .10 = Reserved. .11 = Clock source from 10 kHz internal low speed RC oscillator clock. [27:26] Reserved Reserved. UART Clock Source Selection 00 = Clock source from 4~24 MHz external high speed crystal oscillator clock.
Page 134 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 111 = Clock source from 22.1184 MHz internal high speed RC oscillator clock. Others = reserved. [7:6] Reserved Reserved. SPI1 Clock Source Selection SPI1_S 0 = Clock source from PLL clock. 1 = Clock source from HCLK.
Page 135 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Clock Source Select Control Register 2 (CLKSEL2) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLKSEL2 CLK_BA+0x1C Clock Source Select Control Register 2 0x0002_00FF Reserved RTC_SEL_10...
Page 136 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM2 and PWM3 used the same peripheral clock source; both of them used the same prescaler. The perpherial clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]). If PWM23_S_E = 0, the peripheral clock source of PWM2 and PWM3 defined by PWM23_S list below:.
Page 137 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 01 = Clock source from 32.768 kHz external low speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from 22.1184 MHz internal high speed RC oscillator clock. [1:0] Reserved Reserved.
Page 138 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Clock Divider Register (CLKDIV) Register Offset Description Reset Value CLKDIV CLK_BA+0x18 Clock Divider Number Register 0x0000_0000 Reserved ADC_N Reserved UART_N USB_N HCLK_N Bits Description [15:12] Reserved Reserved. ADC Clock Divide Number From ADC Clock Source ADC_N [23:16] ADC clock frequency = (ADC clock source frequency) / (ADC_N + 1).
Page 139 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PLL Control Register (PLLCON) The PLL reference clock input is from the 4~24 MHz external high speed crystal oscillator clock input or from the 22.1184 MHz internal high speed RC oscillator. These registers are used to control the PLL output frequency and PLL operating mode.
Page 140 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Output Clock Frequency Setting    FOUT Constraint:         preferred Symbol Description FOUT Output Clock Frequency Input (Reference) Clock Frequency Input Divider (IN_DV + 2) Feedback Divider (FB_DV + 2) OUT_DV = “00”...
Page 141 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Frequency Divider Control Register (FRQDIV) Register Offset Description Reset Value FRQDIV CLK_BA+0x24 Frequency Divider Control Register 0x0000_0000 Reserved Reserved Reserved CLKO_1HZ_E Reserved DIVIDER1 DIVIDER_EN FSEL Bits Description [31:7] Reserved Reserved. Clock Output 1Hz Enable Bit 0 = 1 Hz clock output for 32.768 kHz external low speed crystal oscillator clock frequency CLKO_1HZ_EN compensation Disabled.
Page 142: Flash Memory Controller (Fmc)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.4 Flash Memory Controller (FMC) 6.4.1 Overview ® The NuMicro NUC029LEE/NUC029SEE has 128K bytes on-chip embedded Flash for application program memory (APROM) that can be updated through ISP procedure. The In-System- Programming (ISP) function enables user to update program memory when chip is soldered on ®...
Page 143: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.4.3 Block Diagram The flash memory controller consists of AHB slave interface, ISP control logic, writer interface and flash macro interface timing control logic. The block diagram of flash memory controller is shown as follows: Cortex-M0 0x0001_FFFF...
Page 144: Functional Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.4.4 Functional Description 6.4.4.1 Flash Memory Organization ® The NuMicro NUC029LEE/NUC029SEE flash memory consists of program memory (APROM), Data Flash, ISP loader program memory (LDROM), and user configuration. Program memory is main memory for user applications and called APROM. User can write their application to APROM and set system to boot from APROM.
Page 145: Figure 6.4-2 Flash Memory Organization
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller The Flash memory organization is shown as Figure 6.4-2: 0x0030_03FF User Configuration 0x0030_0000 0x0010_1FFF ISP Loader Program Memory 0x0010_0000 Reserved for Further Used 0x0001_FFFF Data Flash Application Program Memory 0x0030_0004 CONFIG1 0x0030_0000 CONFIG0 0x0000_0000...
Page 146 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.4.4.2 User Configuration User configuration is internal programmable configuration area for boot options. The user configuration is located at 0x300000 of Flash Memory Organization and they are two 32 bits words. Any change on user configuration will take effect after system reboot. CONFIG0 (Address = 0x0030_0000) CWDTEN CWDTPDEN...
Page 147 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Brown-out Voltage Selection 00 = 2.2 V [22:21] CBOV 01 = 2.7 V 10 = 3.7 V 11 = 4.4 V Brown-out Reset Enable Bit [20] CBORST 0 = Brown-out reset Enabled after powered on. 1 = Brown-out reset Disabled after powered on.
Page 148 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CONFIG1 (Address = 0x0030_0004) Reserved Reserved DFBADR.19 DFBADR.18 DFBADR.17 DFBADR.16 DFBADR.15 DFBADR.14 DFBADR.13 DFBADR.12 DFBADR.11 DFBADR.10 DFBADR.9 DFBADR.8 DFBADR.7 DFBADR.6 DFBADR.5 DFBADR.4 DFBADR.3 DFBADR.2 DFBADR.1 DFBADR.0 Config Address = 0x0030_0004 Bits Description [31:20] Reserved...
Page 149: Figure 6.4-3 Program Executing Range For Booting From Aprom And Ldrom
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.4.4.3 Boot Selection ® The NuMicro NUC029LEE/NUC029SEE provides In-System-Programming (ISP) feature to enable user to update program memory by a stand-alone ISP firmware. A dedicated 8 KB program memory (LDROM) is used to store ISP firmware. User can select to start program fetch from APROM or LDROM by CBS[1] in CONFIG0.
Page 150: Figure 6.4-4 Executable Range Of Code With Iap Function Enabled
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 0x0010_1FFF 0x0010_1FFF LDROM LDROM (8K) (8K) 0x0010_0000 0x0010_0000 LDROM first page Reserved Reserved Default remap structure APROM APROM 0x0000_0000 0x0000_0000 LDROM first page CBS = 10b CBS = 00b Figure 6.4-4 Executable Range of Code with IAP Function Enabled When chip boots with the IAP function enabled, any other page within the executable range of code can be mirrored to the first page of executable code (0x0000_0000~0x0000_01FF) any time.
Page 151: Figure 6.4-5 Example Flow Of Boot Selection By Bs Bit
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Power CBS = 11b ? CBS = 01b ? Set CPU_RST = 1 Set CPU_RST = 1 Fetch code from Fetch code from AP-ROM LD-ROM Set BS = 1 Set BS = 0 Unlock Switch to boot from Unlock...
Page 152: Figure 6.4-6 Isp Flow Example
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller hardware automatically. User can check whether ISP operation is finished or not by the ISPGO bit. User should add ISB instruction next to the instruction in which ISPGO bit is set 1 to ensure correct execution of the instructions following ISP operation.
Page 153: Table 6.4-2 Isp Command List
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ISP Command ISPCMD ISPADR ISPDAT Valid address of flash memory origination. FLASH Page Erase 0x22 It must be 512 bytes page alignment. FLASH Program 0x21 Valid address of flash memory origination Programming Data FLASH Read 0x00...
Page 154: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.4.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value FMC Base Address: FMC_BA = 0x5000_C000 ISPCON FMC_BA+0x00 ISP Control Register 0x0000_0000 ISPADR FMC_BA+0x04 ISP Address Register...
Page 155: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.4.6 Register Description ISP Control Register (ISPCON) Register Offset Description Reset Value ISPCON FMC_BA+0x00 ISP Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF LDUEN CFGUEN APUEN Reserved ISPEN Bits Description Reserved [31:7] Reserved.
Page 156 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Boot Select (Write Protect ) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened 0 = Boot from APROM.
Page 157 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ISP Address Register (ISPADR) Register Offset Description Reset Value ISPADR FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPADR ISPADR ISPADR ISPADR Bits Description ISP Address ® The NuMicro NUC029LEE/NUC029SEE has a maximum of 32Kx32 (128 KB) embedded ISPADR [31:0] Flash, which supports word program only.
Page 158 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ISP Data Register (ISPDAT) Register Offset Description Reset Value ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 ISPDAT ISPDAT ISPDAT ISPDAT Bits Description ISP Data [31:0] ISPDAT Write data to this register before ISP program operation Read data from this register after ISP read operation Aug, 2018 Page 158 of 497...
Page 159 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ISP Command Register (ISPCMD) Register Offset Description Reset Value ISPCMD FMC_BA+0x0C ISP Command Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPCMD Bits Description [31:6] Reserved Reserved. ISP Command ISP command table is shown below: 0x00 = Read.
Page 160 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ISP Trigger Control Register (ISPTRG) Register Offset Description Reset Value ISPTRG FMC_BA+0x10 ISP Trigger Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPGO Bits Description [31:1] Reserved Reserved. ISP Start Trigger (Write-Protection Bit) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
Page 161 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Data Flash Base Address Register (DFBADR) Register Offset Description Reset Value DFBADR FMC_BA+0x14 Data Flash Base Address 0x000X_XXXX DFBADR DFBADR DFBADR DFBADR Bits Description Data Flash Base Address This register indicates Data Flash start address. It is read only. DFBADR [31:0] Tthe Data Flash size is defined by user configuration, register content is loaded from...
Page 162 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Flash Access Time Control Register (FATCON) Register Offset Description Reset Value FATCON FMC_BA+0x18 Flash Access Time Control Register 0x0000_0000 Reserved Reserved Reserved Reserved FOMSEL1 Reserved FOMSEL0 Reserved Bits Description [31:7] Reserved Reserved.
Page 163 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ISP Status Register (ISPSTA) Register Offset Description Reset Value ISPSTA FMC_BA+0x40 ISP Status Register 0x0000_0000 Reserved Reserved VECMAP VECMAP Reserved Reserved ISPFF Reserved ISPGO Bits Description [31:21] Reserved Reserved. Vector Page Mapping Address (Read Only) VECMAP [20:9] The current flash address space 0x0000_0000~0x0000_01FF is mapping to address...
Page 164: External Bus Interface (Ebi)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller External Bus Interface (EBI) 6.5.1 Overview ® The NuMicro NUC029LEE/NUC029SEE LQFP-64 package equips an external bus interface (EBI) for access external device. To save the connections between external device and this chip, EBI supports address bus and data bus multiplex mode.
Page 165: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.5.3 Block Diagram H_CLK MCLK MCLK MCLKDIV Divider ExttIR2R Idle Cycle ExttIW2X Timing Controller ExttACC ExttAHD EBI State EBI Signal ExttALE AD[15:0] Machine Timing Controller Register Output Controller ExtBW16 Controller EBI request Address Hit ExtEN Request...
Page 166: Figure 6.5-2 Connection Of 16-Bit Ebi Data Width With 16-Bit Device
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller For 16-bit device, the AD [15:0] shared by address (Addr [15:0]) and 16-bit data (Data [15:0]). For 8-bit device, only AD [7:0] shared by address (Addr [7:0]) and 8-bit data (Data [7:0]), AD [15:8] is dedicated for address (Addr [15:8]) and could be connected to 8-bit device directly.
Page 167 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller from HCLK by setting MCLKDIV[2:0] (EBICON [10:8] External Output Clock Divider). Therefore, the EBI controller is suitable for a wide frequency range of EBI device. If MCLK frequency is setting as HCLK/1, EBI signals are synchronized by positive edge of MCLK, else by negative edge of MCLK.
Page 168: Figure 6.5-4 Timing Control Waveform For 16-Bit Data Width
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller tASU tALE tLHD tA2D tACC tAHD MCLK Address RData AD[15:0] output[15:0] input Address AD[15:0] WData output[15:0] output[15:0] Figure 6.5-4 Timing Control Waveform for 16-bit Data Width The figure above shows an example of setting 16-bit data width for EBI application. In this example, AD0~AD15 are used to be address[15:0] and data[15:0].
Page 169: Figure 6.5-5 Timing Control Waveform For 8-Bit Data Width
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller tASU tALE tLHD tA2D tACC tAHD MCLK Address RData AD[7:0] output[7:0] input AD[15:8] Address output[15:8] Address AD[7:0] WData output[7:0] output[7:0] AD[15:8] Address output[15:8] Figure 6.5-5 Timing Control Waveform for 8-bit Data Width The figure above shows an example of setting 8-bit data width for EBI application.
Page 170: Figure 6.5-6 Timing Control Waveform For Insert Idle Cycle
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Insert Idle Cycle When EBI is accessing continuously, bus conflict may occur if the device access time is much longer compared with system clock frequency. The EBI controller supplies additional idle cycle to solve this problem.
Page 171: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.5.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value EBI Base Address: EBI_BA = 0x5001_0000 EBICON EBI_BA+0x00 External Bus Interface General Control Register 0x0000_0000 EXTIME EBI_BA+0x04...
Page 172: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.5.6 Register Description External Bus Interface General Control Register (EBICON) Register Offset Description Reset Value EBICON EBI_BA+0x00 External Bus Interface General Control Register 0x0000_0000 Reserved Reserved ExttALE Reserved MCLKDIV Reserved ExtBW16 ExtEN Bits Description...
Page 173 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller This bit defines if the data bus is 8-bit or 16-bit. 1 = EBI data width is 16-bit 0 = EBI data width is 8-bit EBI Enable This bit is the functional enable bit for EBI. ExtEN 1 = EBI function Enabled 0 = EBI function Disabled...
Page 174 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller External Bus Interface Timing Control Register (EXTIME) Register Offset Description Reset Value EXTIME EBI_BA+0x04 External Bus Interface Timing Control Register 0x0000_0000 Reserved ExtIR2R Reserved ExtIW2X Reserved ExttAHD ExttACC Reserved Bits Description [31:28] Reserved Reserved...
Page 175 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller External Bus Interface Control Register 2 (EBICON2) Register Offset Description Reset Value EBICON2 EBI_BA+0x08 External Bus Interface General Control Register 2 0x0000_0000 Reserved Reserved Reserved Reserved WAHD_OFF RAHD_OFF WBUFF_EN Bits Description [31:3] Reserved Reserved...
Page 176: General Purpose I/O (Gpio)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.6 General Purpose I/O (GPIO) 6.6.1 Overview ® The NuMicro NUC029LEE/NUC029SEE has up to 45 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 45 pins are arranged in 5 ports named as GPIOA, GPIOB, GPIOC, GPIOE and GPIOF.
Page 177: Basic Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.6.3 Basic Configuration The GPIO pin functions are configured in GPA_MFP, GPB_MFP, GPC_MFP, GPE_MFP, ALT_MFP, ALT_MFP1 and ALT_MFP2 registers. 6.6.4 Functional Description 6.6.4.1 Input Mode Explanation Set GPIOx_PMD (PMDn[1:0]) to 00b as the GPIOx port [n] pin is in Input mode and the I/O pin is in tri-state (high impedance) without output drive capability.
Page 178: Figure 6.6-2 Open-Drain Output
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.6.4.3 Open-drain Output Mode Explanation Set GPIOx_PMD (PMDn[1:0]) to 10b as the GPIOx port [n] pin is in Open-drain mode and the digital output function of I/O pin supports only sink current capability, an additional pull-up resistor is needed for driving high state.
Page 179 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.6.4.5 GPIO Interrupt and Wake-up Function Each GPIO pin can be set as chip interrupt source by setting correlative GPIOx_IEN bit and GPIOx_IMD. There are four types of interrupt condition can be selected: low level trigger, high level trigger, falling edge trigger and rising edge trigger.
Page 180: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.6.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value GPIO Base Address: GPIO_BA = 0x5000_4000 GPIOA_PMD GPIO_BA+0x000 R/W GPIO Port A Pin I/O Mode Control Register 0xXXXX_XXXX GPIOA_OFFD GPIO_BA+0x004...
Page 181 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Register Offset R/W Description Reset Value GPIOC_IEN GPIO_BA+0x09C R/W GPIO Port C Interrupt Enable Register 0x0000_0000 GPIOC_ISRC GPIO_BA+0x0A0 R/W GPIO Port C Interrupt Source Flag Register 0x0000_0000 GPIOD_PMD GPIO_BA+0x0C0 R/W GPIO Port D Pin I/O Mode Control Register 0xXXXX_XXXX GPIOD_OFFD GPIO_BA+0x0C4...
Page 182 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Register Offset R/W Description Reset Value PEn_PDIO GPIO_BA+0x300 R/W GPIO PE.n Pin Data Input/Output Register 0x0000_000X n=0,1..15 + 0x04 * n PFn_PDIO GPIO_BA+0x340 R/W GPIO PF.n Pin Data Input/Output Register 0x0000_000X n=0,1..3 + 0x04 * n Aug, 2018...
Page 183: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.6.6 Register Description GPIO Port [A/B/C/E/F] Pin I/O Mode Control Register (GPIOx_PMD) Register Offset R/W Description Reset Value GPIOA_PMD GPIO_BA+0x000 R/W GPIO Port A Pin I/O Mode Control Register 0xXXXX_XXXX GPIOB_PMD GPIO_BA+0x040 R/W GPIO Port B Pin I/O Mode Control Register 0xXXXX_XXXX...
Page 184 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIO Port [A/B/C/E/F] Pin Digital Input Path Disable Register (GPIOx_OFFD) Register Offset R/W Description Reset Value GPIOA_OFFD GPIO_BA+0x004 R/W GPIO Port A Pin Digital Input Path Disable Register 0x0000_0000 GPIOB_OFFD GPIO_BA+0x044 R/W GPIO Port B Pin Digital Input Path Disable Register 0x0000_0000 GPIOC_OFFD...
Page 185 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIO Port [A/B/C/E/F] Data Output Value Register (GPIOx_DOUT) Register Offset R/W Description Reset Value GPIOA_DOUT GPIO_BA+0x008 R/W GPIO Port A Data Output Value Register 0x0000_FFFF GPIOB_DOUT GPIO_BA+0x048 R/W GPIO Port B Data Output Value Register 0x0000_FFFF GPIOC_DOUT GPIO_BA+0x088...
Page 186 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIO Port [A/B/C/E/F] Data Output Write Mask Register (GPIOx _DMASK) Register Offset R/W Description Reset Value GPIOA_DMASK GPIO_BA+0x00C R/W GPIO Port A Data Output Write Mask Register 0x0000_0000 GPIOB_DMASK GPIO_BA+0x04C R/W GPIO Port B Data Output Write Mask Register 0x0000_0000 GPIOC_DMASK GPIO_BA+0x08C R/W GPIO Port C Data Output Write Mask Register...
Page 187 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIO Port [A/B/C/E/F] Pin Value (GPIOx _PIN) Register Offset R/W Description Reset Value GPIOA_PIN GPIO_BA+0x010 GPIO Port A Pin Value 0x0000_XXXX GPIOB_PIN GPIO_BA+0x050 GPIO Port B Pin Value 0x0000_XXXX GPIOC_PIN GPIO_BA+0x090 GPIO Port C Pin Value 0x0000_XXXX GPIOE_PIN...
Page 188 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIO Port [A/B/C/E/F] De-bounce Enable Register (GPIOx _DBEN) Register Offset R/W Description Reset Value GPIOA_DBEN GPIO_BA+0x014 R/W GPIO Port A De-bounce Enable Register 0x0000_0000 GPIOB_DBEN GPIO_BA+0x054 R/W GPIO Port B De-bounce Enable Register 0x0000_0000 GPIOC_DBEN GPIO_BA+0x094...
Page 189 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIO Port [A/B/C/E/F] Interrupt Mode Control Registrt (GPIOx _IMD) Register Offset R/W Description Reset Value GPIOA_IMD GPIO_BA+0x018 R/W GPIO Port A Interrupt Mode Control Register 0x0000_0000 GPIOB_IMD GPIO_BA+0x058 R/W GPIO Port B Interrupt Mode Control Register 0x0000_0000 GPIOC_IMD GPIO_BA+0x098...
Page 190 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIO Port [A/B/C/E/F] Interrupt Enable Register (GPIOx _IEN) Register Offset R/W Description Reset Value GPIOA_IEN GPIO_BA+0x01C R/W GPIO Port A Interrupt Enable Register 0x0000_0000 GPIOB_IEN GPIO_BA+0x05C R/W GPIO Port B Interrupt Enable Register 0x0000_0000 GPIOC_IEN GPIO_BA+0x09C...
Page 191 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Note2: The PA.7, PB.12, PC.4, PC.5, PC.12, PC.13 pin is ignored. GPIO Port [A/B/C/E/F] Interrupt Source Flag Register (GPIOx _ISRC) Register Offset R/W Description Reset Value GPIOA_ISRC GPIO_BA+0x020 R/W GPIO Port A Interrupt Source Flag Register 0x0000_0000 GPIOB_ISRC GPIO_BA+0x060...
Page 192 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Interrupt De-bounce Cycle Control Register (DBNCECON) Register Offset R/W Description Reset Value DBNCECON GPIO_BA+0x180 R/W External Interrupt De-bounce Control Register 0x0000_0020 Reserved Reserved Reserved Reserved ICLK_ON DBCLKSRC DBCLKSEL Bits Description Interrupt Clock On Mode 0 = Edge detection circuit is active only if I/O pin corresponding GPIOx_IEN bit is set to ICLK_ON 1 = All I/O pins edge detection circuit is always active after reset.
Page 193 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Sample interrupt input once per 16*256 clocks Sample interrupt input once per 32*256 clocks Sample interrupt input once per 64*256 clocks Sample interrupt input once per 128*256 clocks Aug, 2018 Page 193 of 497 Rev 1.00...
Page 194 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller GPIO Px.n Pin Data Input/Output Register (Pxn_PDIO) Register Offset R/W Description Reset Value PAn_PDIO GPIO_BA+0x200 R/W GPIO PA.n Pin Data Input/Output Register 0x0000_000X n=0,1..6,8..15 + 0x04 * n PBn_PDIO GPIO_BA+0x240 R/W GPIO PB.n Pin Data Input/Output Register 0x0000_000X n=0,1..11,13..15 + 0x04 * n...
Page 195: Pdma Controller (Pdma)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.7 PDMA Controller (PDMA) 6.7.1 Overview ® The NuMicro NUC029LEE/NUC029SEE DMA contains nine-channel peripheral direct memory access (PDMA) controller and a cyclic redundancy check (CRC) generator. The PDMA that transfers data to and from memory or transfer data to and from APB devices. For PDMA channel (PDMA CH0~CH8), there is one-word buffer as transfer buffer between the Peripherals APB devices and Memory.
Page 196: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Supports the follows write data length in CPU PIO mode  8-bit write mode (byte): 1-AHB clock cycle operation.  16-bit write mode (half-word): 2-AHB clock cycle operation.  32-bit write mode (word): 4-AHB clock cycle operation. Supports byte alignment transfer data length and word alignment transfer source address in CRC DMA mode.
Page 197: Basic Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC Checksum Reg CRC CTL CRC Seed CCITT Checksum CRC-8 Reverse / In Data 1's COMP Reverse/ CRC-16 1's COMP CRC-32 CRC CTL CRC BM FSM Control Figure 6.7-2 CRC Generator Block Diagram 6.7.4 Basic Configuration The PDMA controller peripheral clock can be enabled in PDMA_EN (AHBCLK[1]).
Page 198 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller  Configure the channel service setting by setting PDMA_PDSSR0/ PDMA_PDSSR1 register.  Configure PDMA_CSRx register: Enable PDMA channel(PDMACEN (PDMA_CSRx[0])) Set source/destination address direction(SAD_SEL (PDMA_CSRx[5:4]) / DAD_SEL (PDMA_CSRx[7:6])) Configure PDMA mode selection(MODE_SEL (PDMA_CSRx[3:2])) Configure peripheral transfer width selection (APB_TWS (PDMA_CSRx[20:19])).
Page 199 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller  Write data to CRC write data register (CRC_WDATA (CRC_WDATA[31:0])) to perform CRC calculation.  Then, get the CRC checksum results by reading the CRC checksum register (CRC_CHECKSUM (CRC_CHECKSUM[31:0])). Procedure when operating in CRC DMA mode: ...
Page 200: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.7.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PDMA Base Address: PDMA_CHx_BA = 0x5000_8000 + 0x100 * x x=0,1 .. 8 CRC_BA = 0x5000_8E00 PDMA_GCR_BA = 0x5000_8F00 PDMA_CSRx...
Page 201 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC_DMAISR CRC_BA+0x24 R/W CRC DMA Interrupt Status Register 0x0000_0000 CRC_WDATA CRC_BA+0x80 R/W CRC Write Data Register 0x0000_0000 CRC_SEED CRC_BA+0x84 R/W CRC Seed Register 0xFFFF_FFFF CRC_CHECKSUM CRC_BA+0x88 CRC Checksum Register 0xFFFF_FFFF PDMA_GCRCSR PDMA_GCR_BA+0x00 R/W PDMA Global Control Register 0x0000_0000...
Page 202: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.7.7 Register Description PDMA Channel x Control Register (PDMA_CSRx) Register Offset Description Reset Value PDMA_CSRx PDMA_CHx_BA+0x00 PDMA Channel x Control Register 0x0000_0000 x=0,1 .. 8 Reserved TRIG_EN Reserved APB_TWS Reserved Reserved DAD_SEL SAD_SEL MODE_SEL...
Page 203 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Transfer Source Address Direction Selection 00 = Transfer source address is increasing successively. 01 = Reserved. [5:4] SAD_SEL 10 = Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations).
Page 204 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Channel x Source Address Register (PDMA_SARx) Register Offset Description Reset Value PDMA_SARx PDMA_CHx_BA+0x04 PDMA Channel x Source Address Register 0x0000_0000 x=0,1 .. 8 PDMA_SAR PDMA_SAR PDMA_SAR PDMA_SAR Bits Description PDMA Transfer Source Address Register [31:0] PDMA_SAR This field indicates a 32-bit source address of PDMA.
Page 205 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Channel x Destination Address Register (PDMA_DARx) Register Offset Description Reset Value PDMA_DARx PDMA_CHx_BA+0x08 PDMA Channel x Destination Address Register 0x0000_0000 x=0,1 .. 8 PDMA_DAR PDMA_DAR PDMA_DAR PDMA_DAR Bits Description PDMA Transfer Destination Address Register [31:0] PDMA_DAR This field indicates a 32-bit destination address of PDMA.
Page 206 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Channel x Transfer Byte Count Register (PDMA_BCRx) Register Offset Description Reset Value PDMA_BCRx PDMA_CHx_BA+0x0C R/W PDMA Channel x Transfer Byte Count Register 0x0000_0000 x=0,1 .. 8 Reserved Reserved PDMA_BCR PDMA_BCR Bits Description [31:16]...
Page 207 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Channel x Internal Buffer Pointer Register (PDMA_POINTx) Register Offset Description Reset Value PDMA_POINTx PDMA_CHx_BA+0x10 PDMA Channel x Internal Buffer Pointer Register 0xXXXX_0000 x=0,1 .. 8 Reserved Reserved Reserved Reserved PDMA_POINT Bits Description [31:4]...
Page 208 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Channel x Current Source Address Register (PDMA_CSARx) Register Offset Description Reset Value PDMA_CSARx PDMA_CHx_BA+0x14 PDMA Channel x Current Source Address Register 0x0000_0000 x=0,1 .. 8 PDMA_CSAR PDMA_CSAR PDMA_CSAR PDMA_CSAR Bits Description PDMA Current Source Address Register (Read Only) [31:0]...
Page 209 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Channel x Current Destination Address Register (PDMA_CDARx) Register Offset R/W Description Reset Value PDMA_CDARx PDMA_CHx_BA+0x18 PDMA Channel x Current Destination Address Register 0x0000_0000 x=0,1 .. 8 PDMA_CDAR PDMA_CDAR PDMA_CDAR PDMA_CDAR Bits Description PDMA Current Destination Address Register (Read Only)
Page 210 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Channel x Current Byte Count Register (PDMA_CBCRx) Register Offset R/W Description Reset Value PDMA_CBCRx PDMA_CHx_BA+0x1C R PDMA Channel x Current Transfer Byte Count Register 0x0000_0000 x=0,1 .. 8 Reserved Reserved PDMA_CBCR PDMA_CBCR Bits...
Page 211 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Channel x Interrupt Enable Register (PDMA_IERx) Register Offset Description Reset Value PDMA_IERx PDMA_CHx_BA+0x20 PDMA Channel x Interrupt Enable Register 0x0000_0001 x=0,1 .. 8 Reserved Reserved Reserved Reserved BLKD_IE TABORT_IE Bits Description [31:2] Reserved...
Page 212 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Channel x Interrupt Status Register (PDMA_ISRx) Register Offset Description Reset Value PDMA_ISRx PDMA_CHx_BA+0x24 PDMA Channel x Interrupt Status Register 0x0000_0000 x=0,1 .. 8 Reserved Reserved Reserved Reserved BLKD_IF TABORT_IF Bits Description [31:2] Reserved...
Page 213 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Shared Buffer FIFO 0 Register (PDMA_SBUF0_Cx) Register Offset Description Reset Value PDMA_SBUF0_Cx PDMA_CHx_BA+0x80 PDMA Channel x Shared Buffer FIFO 0 Register 0x0000_0000 x=0,1 .. 8 PDMA_SBUF0 PDMA_SBUF0 PDMA_SBUF0 PDMA_SBUF0 Bits Description PDMA Shared Buffer FIFO 0 (Read Only) [31:0]...
Page 214 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC Control Register (CRC_CTL) Register Offset Description Reset Value CRC_CTL CRC_BA+0x00 CRC Control Register 0x2000_0000 CHECKSUM_ CHECKSUM_ CRC_MODE CPU_WDLEN WDATA_COM WDATA_RVS TRIG_EN Reserved Reserved Reserved CRC_RST CRCCEN Bits Description CRC Polynomial Mode This field indicates the CRC operation polynomial mode.
Page 215 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Checksum Reverse This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register. [25] CHECKSUM_RVS 0 = Bit order reverse for CRC checksum Disabled. 1 = Bit order reverse for CRC checksum Enabled.
Page 216 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC DMA Source Address Register (CRC_DMASAR) Register Offset Description Reset Value CRC_DMASAR CRC_BA+0x04 CRC DMA Source Address Register 0x0000_0000 CRC_DMASAR CRC_DMASAR CRC_DMASAR CRC_DMASAR Bits Description CRC DMA Transfer Source Address Register This field indicates a 32-bit source address of CRC DMA.
Page 217 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC DMA Transfer Byte Count Register (CRC_DMABCR) Register Offset Description Reset Value CRC_DMABCR CRC_BA+0x0C CRC DMA Transfer Byte Count Register 0x0000_0000 Reserved Reserved CRC_DMABCR CRC_DMABCR Bits Description [31:16] Reserved Reserved. CRC DMA Transfer Byte Count Register [15:0] CRC_DMABCR This field indicates a 16-bit total transfer byte count number of CRC DMA...
Page 218 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC DMA Current Source Address Register (CRC_DMACSAR) Register Offset Description Reset Value CRC_DMACSAR CRC_BA+0x14 CRC DMA Current Source Address Register 0x0000_0000 CRC_DMACSAR CRC_DMACSAR CRC_DMACSAR CRC_DMACSAR Bits Description CRC DMA Current Source Address Register (Read Only) [31:0] CRC_DMACSAR This field indicates the current source address where the CRC DMA transfer just occurs.
Page 219 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC DMA Current Transfer Byte Count Register (CRC_DMACBCR) Register Offset Description Reset Value CRC_DMACBCR CRC_BA+0x1C CRC DMA Current Transfer Byte Count Register 0x0000_0000 Reserved Reserved CRC_DMACBCR CRC_DMACBCR Bits Description [31:16] Reserved Reserved.
Page 220 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC DMA Interrupt Enable Register (CRC_DMAIER) Register Offset Description Reset Value CRC_DMAIER CRC_BA+0x20 CRC DMA Interrupt Enable Register 0x0000_0001 Reserved Reserved Reserved CRC_BLKD_ CRC_TABOR Reserved T_IE Bits Description [31:2] Reserved Reserved. CRC DMA Block Transfer Done Interrupt Enable Bit Enable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF (CRC_DMAISR[1]) bit is set to 1.
Page 221 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC DMA Interrupt Status Register (CRC_DMAISR) Register Offset Description Reset Value CRC_DMAISR CRC_BA+0x24 CRC DMA Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved CRC_BLKD_I CRC_TABOR Reserved T_IF Bits Description [31:2] Reserved Reserved. CRC DMA Block Transfer Done Interrupt Flag This bit indicates that CRC DMA transfer has finished or not.
Page 222 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC Write Data Register (CRC_WDATA) Register Offset Description Reset Value CRC_WDATA CRC_BA+0x80 CRC Write Data Register 0x0000_0000 CRC_WDATA CRC_WDATA CRC_WDATA CRC_WDATA Bits Description CRC Write Data Register When operating in CPU PIO mode, software can write data to this field to perform CRC operation.
Page 223 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC Seed Register (CRC_SEED) Register Offset Description Reset Value CRC_SEED CRC_BA+0x84 CRC Seed Register 0xFFFF_FFFF CRC_SEED CRC_SEED CRC_SEED CRC_SEED Bits Description CRC Seed Register [31:0] CRC_SEED This field indicates the CRC seed value. Aug, 2018 Page 223 of 497 Rev 1.00...
Page 224 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CRC Checksum Register (CRC_CHECKSUM) Register Offset Description Reset Value CRC_CHECKSUM CRC_BA+0x88 CRC Checksum Register 0xFFFF_FFFF CRC_CHECKSUM CRC_CHECKSUM CRC_CHECKSUM CRC_CHECKSUM Bits Description CRC Checksum Register [31:0] CRC_CHECKSUM This fields indicates the CRC checksum result Aug, 2018 Page 224 of 497 Rev 1.00...
Page 225 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Global Control Register (PDMA_GCRCSR) Register Offset Description Reset Value PDMA_GCRCSR PDMA_GCR_BA+0x00 R/W PDMA Global Control Register 0x0000_0000 Reserved CRC_CLK_EN Reserved CLK8_EN CLK7_EN CLK6_EN CLK5_EN CLK4_EN CLK3_EN CLK2_EN CLK1_EN CLK0_EN Reserved Bits Description [31:25]...
Page 226 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Controller Channel 2 Clock Enable Bit CLK2_EN [10] 0 = Disabled. 1 = Enabled. PDMA Controller Channel 1 Clock Enable Bit CLK1_EN 0 = Disabled. 1 = Enabled. PDMA Controller Channel 0 Clock Enable Bit CLK0_EN 0 = Disabled.
Page 227 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Service Selection Control Register 0 (PDMA_PDSSR0) Register Offset Description Reset Value PDMA_PDSSR0 PDMA_GCR_BA+0x04 R/W PDMA Service Selection Control Register 0 0xFFFF_FFFF SPI3_TXSEL SPI3_RXSEL SPI2_TXSEL SPI2_RXSEL SPI1_TXSEL SPI1_RXSEL SPI0_TXSEL SPI0_RXSEL Bits Description PDMA SPI3 TX Selection This field defines which PDMA channel is connected to the on-chip peripheral SPI3 TX.
Page 228 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA SPI0 TX Selection This field defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. [7:4] SPI0_TXSEL Software can configure the TX channel setting by this field. The channel configuration is the same as SPI0_RXSEL (PDMA_PDSSR0[3:0]) field.
Page 229 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Service Selection Control Register 1 (PDMA_PDSSR1) Register Offset Description Reset Value PDMA_PDSSR1 PDMA_GCR_BA+0x08 R/W PDMA Service Selection Control Register 1 0xFFFF_FFFF Reserved ADC_RXSEL Reserved UART1_TXSEL UART1_RXSEL UART0_TXSEL UART0_RXSEL Bits Description [31:28] Reserved Reserved.
Page 230 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA UART0 RX Selection This field defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by this field. For example, UART0_RXSEL (PDMA_PDSSR1[3:0]) = 0110, which means UART0_RX is connected to PDMA_CH6.
Page 231 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PDMA Global Interrupt Status Register (PDMA_GCRISR) Register Offset Description Reset Value PDMA_GCRISR PDMA_GCR_BA+0x0C R PDMA Global Interrupt Status Register 0x0000_0000 INTR Reserved Reserved INTRCRC Reserved INTR8 INTR7 INTR6 INTR5 INTR4 INTR3 INTR2 INTR1 INTR0...
Page 232 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Interrupt Status Of Channel 3 INTR3 This bit is the interrupt status of PDMA channel3. Note: This bit is read only. Interrupt Status Of Channel 2 INTR2 This bit is the interrupt status of PDMA channel2. Note: This bit is read only.
Page 233: Timer Controller (Timer)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.8 Timer Controller (TIMER) 6.8.1 Overview The timer controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins.
Page 234: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.8.3 Block Diagram The Timer Controller block diagram and clock control are shown as follows. WAKE_EN (TCSR[23]) 24-bit TCMPR[23:0] CRST (TCSR[26]) Reset counter (TISR[1]) Timer wakeup CEN (TCSR[30]) (TISR[0]) TMRx_CLK 8-bit Internal 24-bit pre-scale up-counter...
Page 235: Figure 6.8-2 Clock Source Of Timer Controller
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller TMR0_S (CLKSEL1[10:8]) TMR1_S (CLKSEL1[14:12]) TMR2_S (CLKSEL1[18:16]) TMR3_S (CLKSEL1[22:20]) TMR0_EN (APBCLK[2]) TMR1_EN (APBCLK[3]) TMR2_EN (APBCLK[4]) TMR3_EN (APBCLK[5]) 22.1184 MHz HIRC 10 kHz LIRC TM0/TM1/TM2/TM3 TMRx_CLK HCLK 32.768 kHz LXT Legend: 4~24 MHz HXT HXT = High-Speed External clock signal = Low-Speed External clock signal HIRC = High-Speed Internal clock signal...
Page 236: Basic Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.8.4 Basic Configuration The peripheral clock source of Timer0 ~ Timer3 can be enabled in APBCLK[5:2] and selected as different frequency in CLKSEL1[10:8] for Timer0, CLKSEL1[14:12] for Timer1, CLKSEL1[18:16] for Timer2 and CLKSEL1[22:20] for Timer3. 6.8.5 Functional Description 6.8.5.1 Timer Interrupt Flag Timer controller supports two interrupt flags;...
Page 237: Figure 6.8-3 Continuous Counting Mode
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.8.5.5 Continuous Counting Mode If timer controller is configured at continuous counting mode (TCSR[28:27] is 11) and CEN bit is set, the timer counter starts up counting. Once the TDR value reaches TCMP value, the TIF flag will be set to 1 and TDR value keeps up counting.
Page 238 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.8.5.6 Event Counting Mode Timer controller also provides an application which can count the input event from TMx pin (x= 0~3) and the number of event will reflect to TDR value. It is also called as event counting function. In this function, CTB (TCSR[24]) bit should be set and the timer peripheral clock source should be set as HCLK.
Page 239: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.8.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value TIMER Base Address: TMR01_BA = 0x4001_0000 TMR23_BA = 0x4011_0000 TCSR0 TMR01_BA+0x00 Timer0 Control and Status Register 0x0000_0005 TCMPR0 TMR01_BA+0x04...
Page 240 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller TCAP3 TMR23_BA+0x30 Timer3 Capture Data Register 0x0000_0000 TEXCON3 TMR23_BA+0x34 Timer3 External Control Register 0x0000_0000 TEXISR3 TMR23_BA+0x38 Timer3 External Interrupt Status Register 0x0000_0000 Aug, 2018 Page 240 of 497 Rev 1.00...
Page 241: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.8.7 Register Description Timer Control Register (TCSR) Register Offset Description Reset Value TCSR0 TMR01_BA+0x00 Timer0 Control and Status Register 0x0000_0005 TCSR1 TMR01_BA+0x20 Timer1 Control and Status Register 0x0000_0005 TCSR2 TMR23_BA+0x00 Timer2 Control and Status Register 0x0000_0005 TCSR3 TMR23_BA+0x20...
Page 242 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Timer Operating Mode 00 = The Timer controller is operated in One-shot mode. 01 = The Timer controller is operated in Periodic mode. [28:27] MODE 10 = The Timer controller is operated in Toggle-output mode. 11 = The Timer controller is operated in Continuous Counting mode.
Page 243 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Timer Compare Register (TCMPR) Register Offset Description Reset Value TCMPR0 TMR01_BA+0x04 Timer0 Compare Register 0x0000_0000 TCMPR1 TMR01_BA+0x24 Timer1 Compare Register 0x0000_0000 TCMPR2 TMR23_BA+0x04 Timer2 Compare Register 0x0000_0000 TCMPR3 TMR23_BA+0x24 Timer3 Compare Register 0x0000_0000 Reserved TCMP...
Page 244 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Timer Interrupt Status Register (TISR) Register Offset Description Reset Value TISR0 TMR01_BA+0x08 Timer0 Interrupt Status Register 0x0000_0000 TISR1 TMR01_BA+0x28 Timer1 Interrupt Status Register 0x0000_0000 TISR2 TMR23_BA+0x08 Timer2 Interrupt Status Register 0x0000_0000 TISR3 TMR23_BA+0x28 Timer3 Interrupt Status Register...
Page 245 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Timer Data Register (TDR) Register Offset Description Reset Value TDR0 TMR01_BA+0x0C R Timer0 Data Register 0x0000_0000 TDR1 TMR01_BA+0x2C R Timer1 Data Register 0x0000_0000 TDR2 TMR23_BA+0x0C R Timer2 Data Register 0x0000_0000 TDR3 TMR23_BA+0x2C R Timer3 Data Register 0x0000_0000...
Page 246 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Timer Capture Data Register (TCAP) Register Offset Description Reset Value TCAP0 TMR01_BA+0x10 Timer0 Capture Data Register 0x0000_0000 TCAP1 TMR01_BA+0x30 Timer1 Capture Data Register 0x0000_0000 TCAP2 TMR23_BA+0x10 Timer2 Capture Data Register 0x0000_0000 TCAP3 TMR23_BA+0x30 Timer3 Capture Data Register...
Page 247 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Timer External Control Register (TEXCON) Register Offset Description Reset Value TEXCON0 TMR01_BA+0x14 Timer0 External Control Register 0x0000_0000 TEXCON1 TMR01_BA+0x34 Timer1 External Control Register 0x0000_0000 TEXCON2 TMR23_BA+0x14 Timer2 External Control Register 0x0000_0000 TEXCON3 TMR23_BA+0x34 Timer3 External Control Register...
Page 248 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 0 = RSTCAPSEL function of TMx_EXT pin will be ignored. 1 = RSTCAPSEL function of TMx_EXT pin is active. Timer External Capture Pin Edge Detect Selection 00 = A 1 to 0 transition on TMx_EXT pin will be detected. [2:1] TEX_EDGE 01 = A 0 to 1 transition on TMx_EXT pin will be detected.
Page 249 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Timer External Interrupt Status Register (TEXISR) Register Offset Description Reset Value TEXISR0 TMR01_BA+0x18 Timer0 External Interrupt Status Register 0x0000_0000 TEXISR1 TMR01_BA+0x38 Timer1 External Interrupt Status Register 0x0000_0000 TEXISR2 TMR23_BA+0x18 Timer2 External Interrupt Status Register 0x0000_0000 TEXISR3 TMR23_BA+0x38...
Page 250: Pwm Generator And Capture Timer (Pwm)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.9 PWM Generator and Capture Timer (PWM) 6.9.1 Overview ® The NuMicro NUC029LEE/NUC029SEE has 2 sets of PWM group supporting a total of 3 sets of PWM generators that can be configured as 6 independent PWM outputs, PWM0~PWM5, or as 3 complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3) and (PWM4, PWM5) with 3 programmable Dead-zone generators.
Page 251: Features
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For example: HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns So the maximum capture frequency will be 1/900ns ≈ 1000 kHz 6.9.2 Features 6.9.2.1 PWM Function: ...
Page 252: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.9.3 Block Diagram Figure 6.9-1 to Figure 6.9-6 illustrates the architecture of PWM in pair (e.g. PWM-Timer 0/1 are in one pair and PWM-Timer 2/3 are in another one). PWM01_S (CLKSEL2[8], CLKSEL1[29:28]) PWM01_EN(APBCLK[20]) 22.1184 MHz HCLK...
Page 253: Figure 6.9-3 Pwm Generator 2 Clock Source Control
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM23_S (CLKSEL2[9], CLKSEL1[31:30]) PWM23_EN(APBCLK[21]) 22.1184 MHz HCLK PWM23_CLK 32.768 kHz 4~24 MHz 10 kHz Figure 6.9-3 PWM Generator 2 Clock Source Control DZI23(PPR[31:24]) Dead Zone PWM Generator Generator 2 in PWMA group CNR2 CSR2(CSR[10:8]) CMR2...
Page 254: Figure 6.9-5 Pwm Generator 4 Clock Source Control
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM45_S (CLKSEL2[10], CLKSEL2[5:4]) PWM45_EN(APBCLK[22]) 22.1184 MHz HCLK PWM45_CLK 32.768 kHz 4~24 MHz 10 kHz Figure 6.9-5 PWM Generator 4 Clock Source Control DZI01(PPR[23:16]) Dead Zone PWM Generator Generator 0 in PWMB group CNR0 CSR0(CSR[2:0]) CMR0...
Page 255: Basic Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.9.4 Basic Configuration The PWM pin functions are configured in GPA_MFP, GPB_MFP and GPE_MFP registers. The PWM clock can be enabled in APBCLK[22:20]. The PWM clock source is selected by CLKSEL1[31:28], CLKSEL2[5:4] and CLKSEL2[10:8]. 6.9.5 Functional Description 6.9.5.1 PWM-Timer Operation The PWM controller supports 2 operation types: Edge-aligned and Center-aligned type.
Page 256: Figure 6.9-8 Pwm-Timer Operation Timing
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Comparator (CMR) down-counter PWM-Timer output CMR = 1 CNR = 3 CMR = 0 Auto reload = 1 CNR = 4 (CHnMOD=1) (S/W write new value) (Write initial setting) Auto-load Auto-load Set CHnEN=1 (H/W update value) (PWMIFn is set by H/W)
Page 257: Figure 6.9-10 Center-Aligned Type Output Waveform
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.9.5.3 Center-aligned PWM (up/down-counter) The Center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/Down Counting mode. The PWM counter will start counting-up from 0 to match the value of CMRn (old);...
Page 258: Figure 6.9-11 Pwm Center-Aligned Interrupt Generate Timing Waveform
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller CNRn (7FF) CMRn (3FF) PWMIFn (INTxxTYPE=0) clear clear clear PWMIFn (INTxxTYPE=1) clear clear PWMDIFn clear clear PWMn generator ouput PWM period PWM period Figure 6.9-11 PWM Center-aligned Interrupt Generate Timing Waveform 6.9.5.4 PWM Double Buffering, Auto-reload and One-shot Operation PWM Timers have double buffering function and the reload value is updated at the start of next period without affecting current timer operation.
Page 259: Figure 6.9-12 Pwm Double Buffering Illustration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Write Write Write Write CNR=150 CNR=199 CNR=99 CNR=0 CMR=50 CMR=49 CMR=0 CMR=XX Start Stop Waveform write a nonzero number to prescaler & setup clock dividor Figure 6.9-12 PWM Double Buffering Illustration 6.9.5.5 Modulate Duty Ratio The double buffering function allows CMRn written at any point in current cycle.
Page 260: Figure 6.9-14 Paired-Pwm Output With Dead-Zone Generation Operation
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM-Timer Output 0/2/4/6 PWM-Timer Inversed output 1/3/5/7 Dead-Zone Generator output 0/2/4/6 Dead-Zone Generator output 1/3/5/7 Dead zone interval Figure 6.9-14 Paired-PWM Output with Dead-zone Generation Operation 6.9.5.7 PWM Center-aligned Trigger ADC Function PWM can trigger ADC to start conversion when PWM counter up count to CNR in Center-aligned type by setting PWMnTEN (TCON[3:0]) to “1”.
Page 261: Figure 6.9-16 Capture Operation Timing
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller the corresponding GPIO pins must be configured as capture function (POE disabled and CAPENR enabled) for the corresponding capture channel. PWM Counter Reload Reload No reload due to (If CNRn = 8) no CAPIFn Capture Input n CAPCHnEN...
Page 262: Figure 6.9-17 Pwm Group A Pwm-Timer Interrupt Architecture Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWMIF0 PWM0_INT PWMDIF0 PWM Interrupt source in PWMA group CAPIF0 PWMIF1 PWM1_INT PWMDIF1 CAPIF1 PWMA_INT PWMIF2 PWM2_INT PWMDIF2 CAPIF2 PWMIF3 PWM3_INT PWMDIF3 CAPIF3 Figure 6.9-17 PWM Group A PWM-Timer Interrupt Architecture Diagram PWM Interrupt source in PWMB group PWMIF0...
Page 263 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.9.5.10 PWM-Timer Start Procedure The following procedure is recommended for starting a PWM drive. Setup clock source divider select register (CSR) Wait until SYNCBUSYn be set to 0 by hardware (if PWM clock source is not from HCLK) Setup prescaler (PPR) Wait until SYNCBUSYn be set to 0 by hardware (if PWM clock source is not from...
Page 264 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.9.5.13 PWM-Timer Stop Procedure Method 1: Set 16-bit counter (CNR) as 0, and monitor PDR (current value of 16-bit down-counter). When PDR reaches to 0, disable PWM-Timer (CHnEN in PCR). (Recommended) Method 2: Set 16-bit counter (CNR) as 0.
Page 265: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.9.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value PWM Base Address:  PWM group A PWMA_BA = 0x4004_0000  PWM group B PWMB_BA = 0x4014_0000 PWMA_BA+0x00 PWM Prescaler Register...
Page 266 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWMB_BA+0x44 PWMA_BA+0x50 CCR0 PWM Capture Control Register 0 0x0000_0000 PWMB_BA+0x50 CCR2 PWMA_BA+0x54 PWM Capture Control Register 2 0x0000_0000 PWMA_BA+0x58 CRLR0 PWM Capture Rising Latch Register (Channel 0) 0x0000_0000 PWMB_BA+0x58 PWMA_BA+0x5C CFLR0 PWM Capture Falling Latch Register (Channel 0) 0x0000_0000 PWMB_BA+0x5C...
Page 267: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.9.7 Register Description PWM Prescale Register (PPR) Register Offset Description Reset Value PWMA_BA+0x00 PWM Prescaler Register 0x0000_0000 PWMB_BA+0x00 DZI23 DZI01 CP23 CP01 Bits Description Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A) [31:24] DZI23...
Page 268 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Clock Source Divider Select Register (CSR) Register Offset Description Reset Value PWMA_BA+0x04 PWM Clock Source Divider Select Register 0x0000_0000 PWMB_BA+0x04 Reserved Reserved Reserved CSR3 Reserved CSR2 Reserved CSR1 Reserved CSR0 Bits Description [31:15]...
Page 269 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Control Register (PCR) Register Offset Description Reset Value PWMA_BA+0x08 PWM Control Register 0x0000_0000 PWMB_BA+0x08 PWM23TYPE PWM01TYPE Reserved CH3MOD CH3INV CH3PINV CH3EN Reserved CH2MOD CH2INV CH2PINV CH2EN Reserved CH1MOD CH1INV CH1PINV CH1EN Reserved DZEN23...
Page 270 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 1 = Auto-reload mode. Note: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared. PWM-Timer 2 Output Inverter Enable (PWM Timer 2 For Group A) [18] CH2INV 0 = Inverter Disabled.
Page 271 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM-Timer 0 Output Inverter Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B) CH0INV 0 = Inverter Disabled. 1 = Inverter Enabled. PWM-Timer 0 Output Polar Inverse Enable (PWM Timer 0 For Group A And PWM Timer 4 For Group B) CH0PINV 0 = PWM0 output polar inverse Disabled.
Page 272 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Counter Register 3-0 (CNR3-0) Register Offset Description Reset Value PWMA_BA+0x0C CNR0 PWM Counter Register 0 0x0000_0000 PWMB_BA+0x0C PWMA_BA+0x18 CNR1 PWM Counter Register 1 0x0000_0000 PWMB_BA+0x18 CNR2 PWMA_BA+0x24 PWM Counter Register 2 0x0000_0000 CNR3 PWMA_BA+0x30...
Page 273 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Comparator Register 3-0 (CMR3-0) Register Offset Description Reset Value PWMA_BA+0x10 CMR0 PWM Comparator Register 0 0x0000_0000 PWMB_BA+0x10 PWMA_BA+0x1C CMR1 PWM Comparator Register 1 0x0000_0000 PWMB_BA+0x1C CMR2 PWMA_BA+0x28 PWM Comparator Register 2 0x0000_0000 CMR3 PWMA_BA+0x34...
Page 274 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Data Register 3-0 (PDR 3-0) Register Offset Description Reset Value PWMA_BA+0x14 PDR0 PWM Data Register 0 0x0000_0000 PWMB_BA+0x14 PWMA_BA+0x20 PDR1 PWM Data Register 1 0x0000_0000 PWMB_BA+0x20 PDR2 PWMA_BA+0x2C PWM Data Register 2 0x0000_0000 PDR3 PWMA_BA+0x38...
Page 275 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Backward Compatible Register (PBCR) Register Offset Description Reset Value PWMA_BA+0x3C PBCR PWM Backward Compatible Register 0x0000_0000 PWMB_BA+0x3C Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. PWM Backward Compatible Register 0 = Configure write 0 to clear CFLRI0~3 and CRLRI0~3.
Page 276 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Interrupt Enable Register (PIER) Register Offset Description Reset Value PWMA_BA+0x40 PIER PWM Interrupt Enable Register 0x0000_0000 PWMB_BA+0x40 Reserved Reserved INT23TYPE INT01TYPE Reserved PWMDIE3 PWMDIE2 PWMDIE1 PWMDIE0 Reserved PWMIE3 PWMIE2 PWMIE1 PWMIE0 Bits Description...
Page 277 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Channel 3 Period Interrupt Enable Bit PWMIE3 0 = Disabled. 1 = Enabled. PWM Channel 2 Period Interrupt Enable Bit PWMIE2 0 = Disabled. 1 = Enabled. PWM Channel 1 Period Interrupt Enable Bit PWMIE1 0 = Disabled.
Page 278 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Interrupt Indication Register (PIIR) Register Offset Description Reset Value PWMA_BA+0x44 PIIR PWM Interrupt Indication Register 0x0000_0000 PWMB_BA+0x44 Reserved Reserved Reserved PWMDIF3 PWMDIF2 PWMDIF1 PWMDIF0 Reserved PWMIF3 PWMIF2 PWMIF1 PWMIF0 Bits Description [31:12] Reserved...
Page 279 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0. PWM Channel 0 Period Interrupt Status PWMIF0 This bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register), software can write 1 to clear this bit to 0.
Page 280 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Capture Control Register (CCR0) Register Offset Description Reset Value PWMA_BA+0x50 CCR0 PWM Capture Control Register 0 0x0000_0000 PWMB_BA+0x50 Reserved CFLRI1 CRLRI1 Reserved CAPIF1 CAPCH1EN CFL_IE1 CRL_IE1 INV1 Reserved CFLRI0 CRLRI0 Reserved CAPIF0 CAPCH0EN CFL_IE0...
Page 281 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 1 = Falling latch interrupt Enabled. When Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt. Channel 1 Rising Latch Interrupt Enable Bit 0 = Rising latch interrupt Disabled. [17] CRL_IE1 1 = Rising latch interrupt Enabled.
Page 282 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 1 = Inverter Enabled. Reverse the input signal from GPIO before fed to Capture timer Aug, 2018 Page 282 of 497 Rev 1.00...
Page 283 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Capture Control Register (CCR2) Register Offset Description Reset Value CCR2 PWMA_BA+0x54 PWM Capture Control Register 2 0x0000_0000 Reserved CFLRI3 CRLRI3 Reserved CAPIF3 CAPCH3EN CFL_IE3 CRL_IE3 INV3 Reserved CFLRI2 CRLRI2 Reserved CAPIF2 CAPCH2EN CFL_IE2 CRL_IE2...
Page 284 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller When Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt. Channel 3 Rising Latch Interrupt Enable Bit 0 = Rising latch interrupt Disabled. [17] CRL_IE3 1 = Rising latch interrupt Enabled.
Page 285 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Capture Rising Latch Register3-0 (CRLR3-0) Register Offset Description Reset Value PWMA_BA+0x58 CRLR0 PWM Capture Rising Latch Register (Channel 0) 0x0000_0000 PWMB_BA+0x58 PWMA_BA+0x60 CRLR1 PWM Capture Rising Latch Register (Channel 1) 0x0000_0000 PWMB_BA+0x60 CRLR2 PWMA_BA+0x68...
Page 286 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Capture Falling Latch Register3-0 (CFLR3-0) Register Offset Description Reset Value PWMA_BA+0x5C CFLR0 PWM Capture Falling Latch Register (Channel 0) 0x0000_0000 PWMB_BA+0x5C PWMA_BA+0x64 CFLR1 PWM Capture Falling Latch Register (Channel 1) 0x0000_0000 PWMB_BA+0x64 CFLR2 PWMA_BA+0x6C...
Page 287 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Capture Input Enable Register (CAPENR) Register Offset Description Reset Value PWMA_BA+0x78 CAPENR PWM Capture Input 0~3 Enable Register 0x0000_0000 PWMB_BA+0x78 Reserved Reserved Reserved Reserved CINEN3 CINEN2 CINEN1 CINEN0 Bits Description [31:4] Reserved Reserved.
Page 288 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Output Enable Register (POE) Register Offset Description Reset Value PWMA_BA+0x7C PWM Output Enable for Channel 0~3 0x0000_0000 PWMB_BA+0x7C Reserved Reserved Reserved Reserved POE3 POE2 POE1 POE0 Bits Description [31:4] Reserved Reserved.
Page 289 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Trigger Control Register (TCON) Register Offset Description Reset Value PWMA_BA+0x80 TCON PWM Trigger Control for Channel 0~3 0x0000_0000 PWMB_BA+0x80 Reserved Reserved Reserved Reserved PWM3TEN PWM2TEN PWM1TEN PWM0TEN Bits Description [31:4] Reserved Reserved.
Page 290 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM Trigger Status Register (TSTATUS) Register Offset Description Reset Value PWMA_BA+0x84 TSTATUS PWM Trigger Status Register 0x0000_0000 PWMB_BA+0x84 Reserved Reserved Reserved Reserved PWM3TF PWM2TF PWM1TF PWM0TF Bits Description Channel 3 Center-Aligned Trigger Flag For Center-aligned Operating mode, this bit is set to 1 by hardware when PWM PWM3TF counter up count to CNR if PWM3TEN bit is set to 1.
Page 291 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM0 Synchronous Busy Status Register (SYNCBUSY0) Register Offset Description Reset Value PWMA_BA+0x88 SYNCBUSY0 PWM0 Synchronous Busy Status Register 0x0000_0000 PWMB_BA+0x88 Reserved Reserved Reserved Reserved S_BUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When software writes CNR0/CMR0/PPR or switches PWM0 operation mode (PCR[3]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
Page 292 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM1 Synchronous Busy Status Register (SYNCBUSY1) Register Offset Description Reset Value PWMA_BA+0x8C SYNCBUSY1 PWM1 Synchronous Busy Status Register 0x0000_0000 PWMB_BA+0x8C Reserved Reserved Reserved Reserved S_BUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When Software writes CNR1/CMR1/PPR or switches PWM1 operation mode (PCR[11]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
Page 293 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM2 Synchronous Busy Status Register (SYNCBUSY2) Register Offset Description Reset Value SYNCBUSY2 PWMA_BA+0x90 PWM2 Synchronous Busy Status Register 0x0000_0000 Reserved Reserved Reserved Reserved S_BUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When Software writes CNR2/CMR2/PPR or switch PWM2 operation mode (PCR[19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
Page 294 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PWM3 Synchronous Busy Status Register (SYNCBUSY3) Register Offset Description Reset Value SYNCBUSY3 PWMA_BA+0x94 PWM3 Synchronous Busy Status Register 0x0000_0000 Reserved Reserved Reserved Reserved S_BUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When Software writes CNR3/CMR3/PPR or switch PWM3 operation mode (PCR[27]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
Page 295: Watchdog Timer (Wdt)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.10 Watchdog Timer (WDT) 6.10.1 Overview The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
Page 296: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.10.3 Block Diagram The Watchdog Timer clock control and block diagram are shown as follows. WDT_S (CLKSEL1[1:0]) WDT_EN (APBCLK[0]) 10 kHz LIRC WDT_CLK HCLK/2048 32.768 kHz LXT Legend: = Low-Speed External clock signal LIRC = Low-Speed Internal clock signal Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Page 297: Basic Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.10.4 Basic Configuration The WDT peripheral clock is enabled in APBCLK[0] and clock source can be selected in CLKSEL1[1:0]. Or user can setting CONFIG0[31] is 0 to force Watchdog Timer enabled and active in 10 kHz after chip powered on or reset.
Page 298: Figure 6.10-3 Watchdog Timer Time-Out Interval And Reset Period Timing
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller (3/18/130/1026) * T Table 6.10-1 Watchdog Timer Time-out Interval Period Selection WTRF = 1 WTIF = 1 (if WTRE = 1) WDT_CLK RSTD WDT reset (low reset) · : Watchdog Clock Time Period ·...
Page 299: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.10.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WDT Base Address: WDT_BA = 0x4000_4000 WTCR WDT_BA+0x00 Watchdog Timer Control Register 0x0000_0700 WTCRALT WDT_BA+0x04...
Page 300: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.10.7 Register Description Watchdog Timer Control Register (WTCR) Register Offset Description Reset Value WTCR WDT_BA+0x00 Watchdog Timer Control Register 0x0000_0700 DBGACK_WD Reserved Reserved Reserved WTIS WTIE WTWKF WTWKE WTIF WTRF WTRE Bits Description ICE Debug Mode Acknowledge Disable Bit (Write Protect)
Page 301 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Watchdog Timer Time-Out Interrupt Enable Bit (Write Protect) If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. WTIE 0 = WDT time-out interrupt Disabled. 1 = WDT time-out interrupt Enabled.
Page 302 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Watchdog Timer Alternative Control Register (WTCRALT) Register Offset Description Reset Value WTCRALT WDT_BA+0x04 Watchdog Timer Alternative Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WTRDSEL Bits Description [31:2] Reserved Reserved. Watchdog Timer Reset Delay Selection (Write Protect) When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened.
Page 303: Window Watchdog Timer (Wwdt)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.11 Window Watchdog Timer (WWDT) 6.11.1 Overview The Window Watchdog Timer is used is to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.11.2 Features ...
Page 304: Basic Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Figure 6.11-2 Window Watchdog Timer Block Diagram 6.11.4 Basic Configuration The WWDT peripheral clock is enabled in APBCLK[0] and clock source can be selected in CLKSEL2[17:16]. 6.11.5 Functional Description The Window Watchdog Timer (WWDT) includes a 6-bit down counter with programmable prescale value to define different WWDT time-out intervals.
Page 305: Figure 6.11-3 Window Watchdog Timer Reset And Reload Behavior
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller unless chip is reset.  WWDT Compare Match Interrupt During down counting by the WWDT counter, the WWDTIF is set to 1 while the WWDT counter value (WWDTCVAL) is equal to WINCMP value and WWDTIF can be cleared by software; if WWDTIE is also set to 1 by software, the WWDT compare match interrupt signal is generated also while WWDTIF is set to 1 by hardware.
Page 306: Table 6.11-2 Wincmp Setting Limitation
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller  WWDT Window Setting Limitation When user writes 0x00005AA5 to WWDTRLD register to reload WWDT counter value to 0x3F, it needs 3 WWDT clocks to sync the reload command to actually perform reload action. This means if user set PERIODSEL to 0000, the counter prescale value should be as 1, and the WINCMP value must be larger than 2;...
Page 307: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.11.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value WWDT Base Address: WWDT_BA = 0x4000_4100 WWDTRLD WWDT_BA+0x00 Window Watchdog Timer Reload Counter Register 0x0000_0000 WWDTCR WWDT_BA+0x04...
Page 308: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.11.7 Register Description Window Watchdog Timer Reload Counter Register (WWDTRLD) Register Offset Description Reset Value WWDTRLD WWDT_BA+0x00 Window Watchdog Timer Reload Counter Register 0x0000_0000 WWDTRLD WWDTRLD WWDTRLD WWDTRLD Bits Description WWDT Reload Counter Register Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
Page 309 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Window Watchdog Timer Control Register (WWDTCR) Register Offset Description Reset Value WWDTCR WWDT_BA+0x04 Window Watchdog Timer Control Register 0x003F_0800 Note: This register can be written only one time after chip is powered on or reset. DBGACK_ Reserved WWDT...
Page 310 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT. 1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT. 1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT. 1111 = Pre-scale is 2048;...
Page 311 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Window Watchdog Timer Status Register (WWDTSR) Register Offset Description Reset Value WWDTSR WWDT_BA+0x08 Window Watchdog Timer Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WWDTRF WWDTIF Bits Description [31:2] Reserved Reserved. WWDT Time-Out Reset Flag This bit indicates the system has been reset by WWDT time-out reset or not.
Page 312 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Window Watchdog Timer Counter Value Register (WWDTCVR) Register Offset Description Reset Value WWDTCVR WWDT_BA+0x0C R Window Watchdog Timer Counter Value Register 0x0000_003F Reserved Reserved Reserved Reserved WWDTCVAL Bits Description [31:6] Reserved Reserved.
Page 313: Real Time Clock (Rtc)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.12 Real Time Clock (RTC) 6.12.1 Overview The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick and alarm match interrupts. The data format of time and calendar messages are expressed in BCD format.
Page 314: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.12.3 Block Diagram The block diagram of Real Time Clock is depicted as follows: Time Alarm Calendar Register Alarm Register (TAR) (CAR) AIER (RIER[0]) Calendar Time Loading Loading Alarm Interrupt Compare Register Register Operation...
Page 315 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.12.5.3 RTC Read/Write Enable AER (AER[15:0] RTC Register Access Enable Password) is served as read/write access of RTC registers to unlock register read/write protection function. If AER[15:0] is written to 0xA965, user can read ENF (AER[16] RTC Register Access Enable Flag) bit status to check the RTC registers are read/write accessible or locked.
Page 316 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 32770 1001 32762 0001 32769 1000 32761 0000 Following are the compensation examples for the real RTC source clock is higher or lower than 32768 Hz. Example 1: (RTC Source Clock > 32768 Hz) RTC Source Clock Measured: 32773.65 Hz ( >...
Page 317 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 09 (AM09) 29 (PM09) 10 (AM10) 30 (PM10) 11 (AM11) 31 (PM11) 6.12.5.7 Day of the Week counter The RTC controller provides day of week in DWR (DWR[2:0] Day of the Week Register). The value is defined from 0 to 6 to represent Sunday to Saturday respectively.
Page 318: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller (SPRCTL[2] SPR Register Enable) before writing one of 20 spare registers (SPR0 ~ SPR19). User could read SPRRDY (SPRCTL[7] SPR Register Ready) to check if data has been written into registers or not. User could only access the spare registers again once SPRRDY is 1. Any access to spare registers is available if SPRRDY is 0.
Page 319 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPR7 RTC_BA+0x5C RTC Spare Register 7 0x0000_0000 SPR8 RTC_BA+0x60 RTC Spare Register 8 0x0000_0000 SPR9 RTC_BA+0x64 RTC Spare Register 9 0x0000_0000 SPR10 RTC_BA+0x68 RTC Spare Register 10 0x0000_0000 SPR11 RTC_BA+0x6C RTC Spare Register 11 0x0000_0000 SPR12 RTC_BA+0x70...
Page 320: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.12.7 Register Description RTC Initiation Register (INIR) Register Offset Description Reset Value INIR RTC_BA+0x00 RTC Initiation Register 0x0000_0000 INIR INIR INIR INIR Bits Description RTC Initiation When RTC block is powered on, RTC is at reset state. User has to write a number [31:1] INIR[31:1] (0xa5eb1357) to INIR to make RTC leaving reset state.
Page 321 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Access Enable Register (AER) Register Offset Description Reset Value RTC_BA+0x04 RTC Access Enable Register 0x0000_0000 Reserved Reserved Bits Description [31:17] Reserved Reserved. RTC Register Access Enable Flag (Read Only) 0 = RTC register read/write access Disabled. [16] 1 = RTC register read/write access Enabled.
Page 322 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Frequency Compensation Register (FCR) Register Offset Description Reset Value RTC_BA+0x08 RTC Frequency Compensation Register 0x0000_0700 Reserved Reserved Reserved INTEGER Reserved FRACTION Bits Description [31:12] Reserved Reserved. Integer Part INTEGER [11:8] Please refer to 6.12.5.4.
Page 323 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Time Loading Register (TLR) Register Offset Description Reset Value RTC_BA+0x0C Time Loading Register 0x0000_0000 Reserved Reserved 10HR Reserved 10MIN 1MIN Reserved 10SEC 1SEC Bits Description [31:22] Reserved Reserved. [21:20] 10HR 10-Hour Time Digit (0~2) [19:16] 1-Hour Time Digit (0~9)
Page 324 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Calendar Loading Register (CLR) Register Offset Description Reset Value RTC_BA+0x10 Calendar Loading Register 0x0005_0101 Reserved 10YEAR 1YEAR Reserved 10MON 1MON Reserved 10DAY 1DAY Bits Description [31:24] Reserved Reserved. [23:20] 10YEAR 10-Year Calendar Digit (0~9) [19:16] 1YEAR...
Page 325 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Time Scale Selection Register (TSSR) Register Offset Description Reset Value TSSR RTC_BA+0x14 Time Scale Selection Register 0x0000_0001 Reserved Reserved Reserved Reserved 24H_12H Bits Description [31:1] Reserved Reserved. 24-Hour / 12-Hour Time Scale Selection It indicates that RTC TLR and TAR counter are in 24-hour time scale or 12-hour time scale.
Page 326 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Day of the Week Register (DWR) Register Offset Description Reset Value RTC_BA+0x18 Day of the Week Register 0x0000_0006 Reserved Reserved Reserved Reserved Bits Description [31:3] Reserved Reserved. Day Of The Week Register 000 = Sunday.
Page 327 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Time Alarm Register (TAR) Register Offset Description Reset Value RTC_BA+0x1C Time Alarm Register 0x0000_0000 Reserved Reserved 10HR Reserved 10MIN 1MIN Reserved 10SEC 1SEC Bits Description [31:22] Reserved Reserved. [21:20] 10HR 10-Hour Time Digit of Alarm Setting (0~2) [19:16] 1-Hour Time Digit of Alarm Setting (0~9)
Page 328 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Calendar Alarm Register (CAR) Register Offset Description Reset Value RTC_BA+0x20 Calendar Alarm Register 0x0000_0000 Reserved 10YEAR 1YEAR Reserved 10MON 1MON Reserved 10DAY 1DAY Bits Description [31:24] Reserved Reserved. [23:20] 10YEAR 10-Year Calendar Digit of Alarm Setting (0~9) [19:16] 1YEAR...
Page 329 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Leap Year Indication Register (LIR) Register Offset Description Reset Value RTC_BA+0x24 Leap Year Indicator Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:1] Reserved Reserved. Leap Year Indication Register (Read Only) 0 = This year is not a leap year.
Page 330 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Interrupt Enable Register (RIER) Register Offset Description Reset Value RIER RTC_BA+0x28 RTC Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved Reserved TIER AIER Bits Description [31:2] Reserved Reserved. Time Tick Interrupt Enable Bit This bit is used to enable/disable RTC Time Tick Interrupt, and generate an interrupt signal if TIF (RIIR[1] RTC Time Tick Interrupt Flag) is set to 1.
Page 331 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Interrupt Indication Register (RIIR) Register Offset Description Reset Value RIIR RTC_BA+0x2C RTC Interrupt Indicator Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:2] Reserved Reserved. RTC Time Tick Interrupt Flag When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TIER (RIER[1]) is set to 1.
Page 332 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Time Tick Register (TTR) Register Offset Description Reset Value RTC_BA+0x30 RTC Time Tick Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:3] Reserved Reserved. Time Tick Register These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 000 = Time tick is 1 second.
Page 333 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Spare Functional Control Register (SPRCTL) Register Offset Description Reset Value SPRCTL RTC_BA+0x3C RTC Spare Functional Control Register 0x0000_0080 Reserved Reserved Reserved SPRRDY Reserved SPREN Reserved Bits Description [31:8] Reserved Reserved. SPR Register Ready This bit indicates if the registers SPRCTL, SPR0 ~ SPR19 are ready to be accessed.
Page 334 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RTC Spare Register (SPRx) Register Offset Description Reset Value SPR0 RTC_BA+0x40 RTC Spare Register 0 0x0000_0000 SPR1 RTC_BA+0x44 RTC Spare Register 1 0x0000_0000 SPR2 RTC_BA+0x48 RTC Spare Register 2 0x0000_0000 SPR3 RTC_BA+0x4C RTC Spare Register 3 0x0000_0000...
Page 335 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Bits Descriptions Spare Register This field is used to store back-up information defined by user.. [31:0] SPARE Before storing back-up information in to SPARE register, user should write 0xA965 to AER[15:0] to make sure register read/write enable bit ENF (AER[16]) is active. Aug, 2018 Page 335 of 497 Rev 1.00...
Page 336: Uart Interface Controller (Uart)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.13 UART Interface Controller (UART) 6.13.1 Overview ® The NuMicro NUC029LEE/NUC029SEE provides up to three channels of Universal Asynchronous Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform Normal Speed UART. Besides, only UART0 and UART1 support the flow control function.
Page 337: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Supports hardware or software direct enable control provided by RTS pin (UART0 and UART1 support) 6.13.3 Block Diagram The UART clock control and block diagram are shown in Figure 5-67 and Figure 5-68 respectively.
Page 338: Basic Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Note: UART0 is equipped with 64 bytes FIFO. UART1/UART2 is equipped with 16 bytes FIFO. Figure 6.13-2 UART Block Diagram Each block is described in detail as follows: TX_FIFO The transmitter is buffered with a 64/16 byte FIFO to reduce the number of interrupts presented to the CPU.
Page 339: Functional Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Type Description UART_TXD Output UART transmit UART_RXD Input UART receive UART_nCTS Input UART modem clear to send UART_nRTS Output UART modem request to send Table 6.13-1 UART Interface Controller Pin 6.13.5 Functional Description The UART Controller supports four function modes including UART, IrDA, LIN and RS-485 mode.
Page 340: Table 6.13-3 Uart Controller Baud Rate Parameter Setting Table
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller A=2, B=11 A=4, B=15 230400 A=94 A=6, B=11 A=10, B=15 115200 A=10 A=190 A=14, B=11 A=22, B=15 57600 A=22 A=382 A=30, B=11 A=62, B=8 38400 A=34 A=46, B=11 A=574 A=34, B=15 A=126, B=8 19200 A=70...
Page 341: Figure 6.13-3 Transmit Delay Time Operation
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Peripheral Clock = 22.1184 MHz Baud Rate Mode 0 Mode 1 Mode 2 921600 Not support 0x2B00_0000 0x3000_0016 0x2F00_0001 460800 0x0000_0001 0x3000_002E 0x2B00_0002 0x2F00_0004 230400 0x0000_0004 0x3000_005E 0x2B00_0006 0x2F00_000A 115200 0x0000_000A 0x3000_00BE 0x2B00_000E...
Page 342 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller information includes the type and condition of the transfer operations being performed by the UART, as well as 3 error conditions (parity error, framing error, break interrupt) probably occur while receiving data. This FIFO control and status also support all of UART, IrDA, LIN and RS- 485 function mode.
Page 343: Table 6.13-5 Uart Controller Interrupt Source And Flag List
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Write “1” to LIN_IF and LIN_IF = LIN_BKDET_F Write “1” to LIN_BKDET_F Write “1” to BIT_ERR_F LIN_IF = BIT_ERR_F LIN Bus Interrupt LIN_ _INT LIN _IEN Write “1” to o LIN_IDPERR_F LIN_IF = LIN_IDPERR_F Write “1”...
Page 344: Table 6.13-7 Uart Line Control Of Word And Stop Length Setting
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UA_LCR register. Software can use the UA_LCR register to program the word length, stop bit and parity bit. The following tables list the UART word and stop bit length settings and the UART parity bit settings.
Page 345: Figure 6.13-4 Auto Flow Control Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Parallel to Serial Tx FIFO /CTS Flow Control Serial to Parallel Rx FIFO /RTS Flow Control Note: It is only supported in UART0 and UART1 Figure 6.13-4 Auto Flow Control Block Diagram The Figure 6.13-5 demonstrates the CTS auto flow control of UART function mode.
Page 346: Figure 6.13-6 Uart Rts Auto Flow Control Enabled
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Setting LEV_RTS(UA_MCR[9]) can control the RTS pin output is inverse or non-inverse from RTS signal. User can read the RTS_ST(UA_MCR[13]) bit to get real RTS pin output voltage logic status. RTS pin output status of UART function mode (RTS auto-flow control enabled) RX_POINTER RTS_TRI_LEV RX_POINTER...
Page 347: Figure 6.13-8 Irda Control Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller between transmission and reception, and this delay feature must be implemented by software. In IrDA mode, the DIV_X_EN (UA_BAUD [29]) register must be disabled. Baud Rate = Clock / (16 * BRD), where BRD is Baud Rate Divider in UA_BAUD register. The Figure 6.13-8 demonstrates the IrDA control block diagram.
Page 348: Figure 6.13-9 Irda Tx/Rx Timing Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller START BIT STOP BIT SOUT (from UART TX) IrDA TX Timing IR_SOUT (encoder output) 3/16 bit width 3/16 bit width IR_SIN (decorder input) IrDA RX Timing (to UART RX) Bit cycle width START BIT STOP BIT Figure 6.13-9 IrDA TX/RX Timing Diagram...
Page 349: Figure 6.13-11 Structure Of Lin Byte
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.13.5.8.2 Structure of LIN Byte In LIN mode, each byte field is initiated by a START bit with value 0 (dominant), followed by 8 data bits and no parity bit, LSB is first and ended by 1 stop bit with value 1 (recessive) in accordance with the LIN standard.
Page 350 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller (UA_LIN_CTL [12]) to “1”, if the input pin (UART_RX) state is not equal to the output pin (UART_TX) state in LIN transmitter state that hardware will generate an interrupt to CPU. Software can also monitor the LIN bus transfer state by checking the read back data in UA_RBR register.
Page 351: Figure 6.13-12 Break Detection In Lin Mode
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller When software enables the break detection function by setting LIN_BKDET_EN (UA_LIN_CTL[10]), the break detection circuit is activated. The break detection circuit is totally independent from the UART0/UART1 receiver. When the break detection function is enabled, the circuit looks at the input UART_RX pin for a start signal.
Page 352: Figure 6.13-13 Lin Frame Id And Parity Format
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Figure 6.13-13 LIN Frame ID and Parity Format 6.13.5.8.4 LIN Slave Mode The UART0/UART1 controller supports LIN Slave mode. To enable and initialize the LIN Slave mode, the following steps are necessary: 1.
Page 353 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller LIN header time-out error The LIN slave controller contains a header time-out counter. If the entire header is not received within the maximum time limit of 57 bit times, the header error flag LINS_HERR_F (UA_LIN_SR [1]) will be set.
Page 354: Figure 6.13-14 Lin Sync Field Measurement
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Slave mode with automatic resynchronization In Automatic Resynchronization mode, the controller will adjust the baud rate generator after each sync field reception. The initialization process flow of Automatic Resynchronization mode is shown as follows: 1.
Page 355: Figure 6.13-15 Ua_Baud Update Sequence In Automatic Resynchronization Mode When
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Frame slot Inter- frame Protected space Response Synch Break Identifier Field field field Check Data 1 Data 2 Data N H/W auto-reload initial baud Measurement S/W set LINS_DUM_EN to 1 rate which backup in time TEMP_REG and cleared LINS_DUM_EN to 0 by H/W...
Page 356 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Deviation error on the sync field When operating in Automatic Resynchronization mode, the controller will check the deviation error on the sync field. The deviation error is checked by comparing the current baud rate with the received sync field.
Page 357 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.13.5.9 RS-485 Function Mode Another alternate function of UART Controller is RS-485 function (user must set UA_FUN_SEL [1:0] to “11” to enable RS-485 function), and direction control provided by RTS pin from an asynchronous serial port.
Page 358: Figure 6.13-17 Rs-485 Rts Driving Level In Auto Direction Mode
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Setting LEV_RTS(UA_MCR[9]) can control RTS pin output driving level. User can read the RTS_ST(UA_MCR[13]) bit to get real RTS pin output voltage logic status. RTS pin output status of RS-485 function mode (RS-485 AUD mode enabled) Start Stop TX pin output*...
Page 359: Figure 6.13-19 Structure Of Rs-485 Frame
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Determine auto direction control by programming RS485_AUD (UA_ALT_CSR[10]). Differential Bus Driver Enable UART / RS-485 Controller RS-485 Transceiver Start Stop TX pin output RTS_ST Driver Enable* (UA_MCR[13]) Note: RS485_AUD(UA_ALT_CSR[10]) must be set to 1, and LEV_RTS(UA_MCR[9]) must be set to 0. Figure 6.13-19 Structure of RS-485 Frame Aug, 2018 Page 359 of 497...
Page 360: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.13.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value UART Base Address: UART0_BA = 0x4005_0000 UART1_BA = 0x4015_0000 UART2_BA = 0x4015_4000 UA_RBR UARTx_BA+0x00 UART Receive Buffer Register...
Page 361 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UA_LIN_CTL UARTx_BA+0x34 UART LIN Control Register 0x000C_0000 x=0,1,2 UA_LIN_SR UARTx_BA+0x38 UART LIN Status Register 0x0000_0000 x=0,1,2 Aug, 2018 Page 361 of 497 Rev 1.00...
Page 362: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.13.7 Register Description UART Receive Buffer Register (UA_RBR) Register Offset Description Reset Value UA_RBR UARTx_BA+0x00 UART Receive Buffer Register Undefined x=0,1,2 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Receive Buffer Register (Read Only) [7:0] By reading this register, the UART will return the 8-bit data received from RX pin (LSB first).
Page 363 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Transmit Holding Register (UA_THR) Register Offset Description Reset Value UA_THR UARTx_BA+0x00 UART Transmit Holding Register Undefined x=0,1,2 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Transmit Holding Register By writing one byte to this register, the data byte will be stored in transmitter FIFO. The [7:0] UART Controller will send out the data stored in transmitter FIFO top location through the TX pin.
Page 364 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Interrupt Enable Register (UA_IER) Register Offset Description Reset Value UA_IER UARTx_BA+0x04 UART Interrupt Enable Register 0x0000_0000 x=0,1,2 Reserved Reserved AUTO_CTS_E AUTO_RTS_E TIME_OUT_E DMA_RX_EN DMA_TX_EN Reserved LIN_IEN BUF_ERR_IE Reserved WAKE_EN TOUT_IEN MODEM_IEN RLS_IEN THRE_IEN...
Page 365 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller LIN Bus Interrupt Enable Bit 0 = Lin bus interrupt Disabled. LIN_IEN 1 = Lin bus interrupt Enabled. Note: This field is used for LIN function mode. Reserved Reserved. UART Wake-Up Function Enable Bit (Not Available In UART2 Channel) 0 = UART wake-up function Disabled.
Page 366 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART FIFO Control Register (UA_FCR) Register Offset Description Reset Value UA_FCR UARTx_BA+0x08 UART FIFO Control Register 0x0000_0101 x=0,1,2 Reserved Reserved RTS_TRI_LEV Reserved RX_DIS RFITL Reserved Reserved Bits Description [31:20] Reserved Reserved. RTS Trigger Level For Auto-Flow Control Use (Not Available In UART2 Channel) 0000 = RTS Trigger Level is 1 byte.
Page 367 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 0101 = RX FIFO Interrupt Trigger Level is 46/14 bytes (High Speed/Normal Speed). 0110 = RX FIFO Interrupt Trigger Level is 62/14 bytes (High Speed/Normal Speed). Other = Reserved. Reserved Reserved. TX Field Software Reset When TFR is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
Page 368 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Line Control Register (UA_LCR) Register Offset Description Reset Value UA_LCR UARTx_BA+0x0C UART Line Control Register 0x0000_0000 x=0,1,2 Reserved Reserved Reserved Reserved Bits Description [31:7] Reserved Reserved. Break Control Bit When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
Page 369 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART MODEM Control Register (UA_MCR) (Not Available in UART2 Channel) Register Offset Description Reset Value UA_MCR UARTx_BA+0x10 UART Modem Control Register 0x0000_0200 x=0,1 Reserved Reserved Reserved RTS_ST Reserved LEV_RTS Reserved Reserved Reserved Bits Description...
Page 370 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Modem Status Register (UA_MSR) (Not Available in UART2 Channel) Register Offset Description Reset Value UA_MSR UARTx_BA+0x14 UART Modem Status Register 0x0000_0110 x=0,1 Reserved Reserved Reserved LEV_CTS Reserved CTS_ST Reserved DCTSF Bits Description [31:9]...
Page 371 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART FIFO Status Register (UA_FSR) Register Offset Description Reset Value UA_FSR UARTx_BA+0x18 UART FIFO Status Register 0x1040_4000 x=0,1,2 Reserved TE_FLAG Reserved TX_OVER_IF TX_FULL TX_EMPTY TX_POINTER RX_FULL RX_EMPTY RX_POINTER RS485_ADD_ Reserved Reserved RX_OVER_IF DETF Bits...
Page 372 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty). TX FIFO Pointer (Read Only) This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one.
Page 373 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Note: This bit is read only, but can be cleared by writing “1” to it. RS-485 Address Byte Detection Flag (Read Only) 0 = Receiver detects a data that is not an address bit (bit 9 =’1’). 1 = Receiver detects a data that is an address bit (bit 9 =’1’).
Page 374 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Interrupt Status Control Register (UA_ISR) Register Offset Description Reset Value UA_ISR UARTx_BA+0x1C UART Interrupt Status Register 0x0000_0002 x=0,1,2 HW_BUF_ER HW_TOUT_IN HW_MODEM_ HW_RLS_INT Reserved Reserved R_INT HW_BUF_ER HW_MODEM_ HW_TOUT_IF HW_RLS_IF Reserved Reserved R_IF BUF_ERR_IN...
Page 375 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer maybe is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated. 0 = No buffer error interrupt flag is generated. 1 = Buffer error interrupt flag is generated.
Page 376 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 1 = Tout interrupt is generated. MODEM Status Interrupt Indicator (Read Only) (Not Available In UART2 Channel) This bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1 [11] MODEM_INT 0 = No Modem interrupt is generated.
Page 377 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller This bit is set when the CTS pin has state change (DCTSF (UA_MSR[0]) = 1). If MODEM_IEN (UA_IER [3]) is enabled, the Modem interrupt will be generated. 0 = No Modem interrupt flag is generated. 1 = Modem interrupt flag is generated.
Page 378 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Time-out Register (UA_TOR) Register Offset Description Reset Value UA_TOR UARTx_BA+0x20 UART Time-out Register 0x0000_0000 x=0,1,2 Reserved Reserved TOIC Bits Description [31:16] Reserved Reserved. TX Delay Time Value [15:8] This field is used to programming the transfer delay time between the last stop bit and next start bit.
Page 379 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Baud Rate Divider Register (UA_BAUD) Register Offset Description Reset Value UA_BAUD UARTx_BA+0x24 UART Baud Rate Divisor Register 0x0F00_0000 x=0,1,2 Reserved DIV_X_EN DIV_X_ONE DIVIDER_X Reserved Bits Description [31:30] Reserved Reserved. Divider X Enable Bit The BRD = Baud Rate Divider, and the baud rate equation is Baud Rate = Clock / [M * (BRD + 2)];...
Page 380 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART IrDA Control Register (IRCR) Register Offset Description Reset Value UA_IRCR UARTx_BA+0x28 UART IrDA Control Register 0x0000_0040 x=0,1,2 Reserved Reserved Reserved Reserved INV_RX INV_TX Reserved TX_SELECT Reserved Bits Description [31:7] Reserved Reserved.
Page 381 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Alternate Control/Status Register (UA_ALT_CSR) Register Offset Description Reset Value UA_ALT_CSR UARTx_BA+0x2C UART Alternate Control/Status Register 0x0000_000C x=0,1,2 ADDR_MATCH Reserved RS485_ADD_ Reserved RS485_AUD RS485_AAD RS485_NMM LIN_TX_EN LIN_RX_EN Reserved LIN_BKFL Bits Description Address Match Value Register [31:24] ADDR_MATCH...
Page 382 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 0 = LIN TX Break mode Disabled. 1 = LIN TX Break mode Enabled. Note: When TX break field transfer operation finished, this bit will be cleared automatically. LIN RX Enable Bit LIN_RX_EN 0 = LIN RX mode Disabled.
Page 383 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART Function Select Register (UA_FUN_SEL) Register Offset Description Reset Value UA_FUN_SEL UARTx_BA+0x30 UART Function Select Register 0x0000_0000 x=0,1,2 Reserved Reserved Reserved Reserved FUN_SEL Bits Description [31:2] Reserved Reserved. Function Select Enable Bit 00 = UART function Enabled.
Page 384 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART LIN Control Register (UA_LIN_CTL) Register Offset Description Reset Value UA_LIN_CTL UARTx_BA+0x34 UART LIN Control Register 0x000C_0000 x=0,1,2 LIN_PID LIN_HEAD_SEL LIN_BS_LEN LIN_BKFL LIN_BKDET_ Reserved BIT_ERR_EN LIN_RX_DIS LIN_IDPEN LIN_SHD LIN_MUTE_E LINS_DUM_E LINS_ARS_E LINS_HDET_ Reserved LINS_EN...
Page 385 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Header Break Field Synch field Protected Identifier field Break/Sync Inter-byte spaces Delimiter Length Note: This bit used for LIN master to sending header field. LIN Break Field Length This field indicates a 4-bit LIN TX break field count. Note1: These registers are shadow registers of LIN_BKFL, User can read/write it by [19:16] LIN_BKFL...
Page 386 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Note2: When transmitter header field (it may be “break” or “break + sync” or “break + sync + frame ID” selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. [7:5] Reserved Reserved.
Page 387 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller UART LIN Status Register (UA_LIN_SR) Register Offset Description Reset Value UA_LIN_SR UARTx_BA+0x38 UART LIN Status Register 0x0000_0000 x=0,1,2 Reserved Reserved LIN_BKDET_ Reserved BIT_ERR_F LINS_SYNC_ LINS_IDPERR LINS_HERR_ Reserved LINS_HDET_F Bits Description [31:10] Reserved Reserved.
Page 388 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller frame header. LIN Slave ID Parity Error Flag (Read Only) This bit is set by hardware when receipted frame ID parity is not correct. 0 = No active. LINS_IDPERR_F 1 = Receipted frame ID parity is not correct. Note1: This bit is read only, but it can be cleared by writing “1”...
Page 389: I 2 C Serial Interface Controller
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.14 I C Serial Interface Controller (I 6.14.1 Overview C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.
Page 390: Basic Configuration
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.14.3 Basic Configuration The basic configurations of I C0 are as follows:  C0 pins are configured on GPA_MFP [9:8] register  Enable I C0 clock by setting I2C0_EN (APBCLK [8]) ...
Page 391: Figure 6.14-2 I 2 C Bus Timing
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller of I2Cn_SCL; therefore, the I2Cn_SDA line may be changed only during the low period of I2Cn_SCL and must be held stable during the high period of I2Cn_SCL. A transition on the I2Cn_SDA line while I2Cn_SCL is high is interpreted as a command (START or STOP).
Page 392: Figure 6.14-4 Start And Stop Conditions
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller line while I2Cn_SCL is HIGH. The START signal denotes the beginning of a new data transmission. After having sent the address byte (address and read/write bit) the master may send any number of bytes followed by a stop condition.
Page 393: Figure 6.14-5 Bit Transfer On The I 2 C Bus
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller I2Cn_SCL I2Cn_SDA Data line stable; Change of data data valid allowed Figure 6.14-5 Bit Transfer on the I C Bus Clock pulse for acknowledgement I2Cn_SCL (from master) I2Cn_SDA (data output by transmitter) not acknowlegde I2Cn_SDA (data output...
Page 394: Figure 6.14-8 Master Reads Data From Slave
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller slave will start transmitting data after the slave returns acknowledge to the master. SLAVE ADDRESS DATA DATA data transfer ‘1’ : read (n bytes + acknowlegde) Figure 6.14-8 Master Reads Data from Slave 6.14.5.2 Operation Modes The on-chip I C ports support three operation modes, Master, Slave, and General Call Mode.
Page 395: Figure 6.14-10 Master Transmitter Mode Control Flow
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.14.5.2.1 Master Mode In below figures, all possible protocols for I C master are shown. User needs to follow proper path of the flow to implement required I C protocol. In other words, user can send a START signal to bus and I C will be in Master Transmitter mode (Figure 6.14-10) or Master receiver mode (Figure 6.14-12) after START signal has been sent successfully and new status code would be 0x08.
Page 396: Figure 6.14-11 Master Receiver Mode Control Flow
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller STATUS=0x08 STATUS=0xF8 STATUS=0x40 STATUS=0x50 I2CDAT I2CDAT (SLA+R) (Data) I2CDAT=SLA+R (STA,STO,SI,AA)=(1,0,1,X) (STA,STO,SI,AA)=(0,0,1,1) (STA,STO,SI,AA)=(0,0,1,x) (Arbitration Lost) ACK STATUS=0x38 I2CDAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x58 I2CDAT (Data) (STA,STO,SI,AA)=(0,0,1,0) STATUS=0x48 STATUS=0x08 (STA,STO,SI,AA)=(1,1,1,X) (Arbitration Lost) STATUS=0x38 STATUS=0xF8 I2CDAT ACK/ (SLA+R) I2CDAT=SLA+R...
Page 397: Figure 6.14-12 Save Mode Control Flow
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller If bus arbitration is lost in Master mode, I C port switches to Slave mode immediately and can detect its own slave address in the same serial transfer. If the detected address is SLA+W (Master want to write data to Slave) after arbitration lost, the status code is 0x68.
Page 398: Figure 6.14-13 Gc Mode
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Note: After slave gets status of 0x88, 0xC8, 0xC0 and 0xA0, slave can switch to not address mode and own SLA will not be recognized. If entering this status, slave will not receive any I signal or address from master.
Page 399: Figure 6.14-14 Arbitration Lost
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller If I C is still receiving data in GC mode but got a STOP or Repeat START, the status code will be 0xA0. User could follow the action for status code 0x98 in above figure when getting 0xA0 status. Note: After slave gets status of 0x98 and 0xA0, slave can switch to not address mode and own SLA will not be recognized.
Page 400: Figure 6.14-15 I 2 C Data Shifting Direction
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.14.5.3 I C Protocol Registers To control I C port through the following fifteen special function registers: I2CON (Control register), I2CSTATUS (Status register), I2CDAT (Data register), I2CADDRn (Address registers, n=0~3), I2CADMn (Address mask registers, n=0~3), I2CLK (Clock rate register), I2CTOC (Time- out counter register), I2CWKCON(Wake up control register), I2CWKSTS(Wake up status register).
Page 401 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.14.5.3.4 Control Register (I2CON) The CPU can be read from and written to I2CON register directly. When the I C port is enabled by setting ENS1 (I2CON [6]) to high, the internal states will be controlled by I2CON and I C logic hardware.
Page 402: Figure 6.14-16 I 2 C Time-Out Count Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 0x98 GC mode Data NACK 0xF8 Bus Released Note: Status “0xF8” exists in both master/slave modes, and it won’t raise interrupt. Table 6.14-1 I C Status Code Description 6.14.5.3.6 Clock Baud Rate Bits (I2CLK) The data baud rate of I C is determines by I2CLK (I2CLK[7:0]) when I C is in Master Mode, and it...
Page 403: Example For Random Read On Eeprom
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.14.6 Example for Random Read on EEPROM The following steps are used to configure the I C0 related registers when using I C to read data from EEPROM. Set the multi-function pin in the “GPA_MFP” registers as I2C0_SCL and I2C0_SDA pins. Enable I C APB clock by setting I2C0_EN(APBCLK[8]).
Page 404: Figure 6.14-18 Protocol Of Eeprom Random Read
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller STATUS=0x08 STATUS=0x18 STATUS=0xF8 I2CDAT I2CDAT (SLA+W) ROM Address High Byte I2CDAT=ROM Address High Byte I2CDAT=SLA+W STATUS=0xF8 (STA,STO,SI,AA)=(0,0,1,X) STATUS=0x20 (STA,STO,SI,AA)=(0,0,1,X) (STA,STO,SI,AA)=(1,0,1,X) (STA,STO,SI,AA)=(0,1,1,X) STATUS=0x28 STATUS=0x28 I2CDAT ROM Address Low Byte I2CDAT=ROM Address Low Byte (STA,STO,SI,AA)=(0,0,1,X) STATUS=0x30 STATUS=0xF8...
Page 405: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.14.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value C Base Address: I2C0_BA = 0x4002_0000 I2C1_BA = 0x4001_2000 I2CON I2Cn_BA+0x00 R/W I C Control Register 0x0000_0000...
Page 406: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.14.8 Register Description C Control Register (I2CON) Register Offset Description Reset Value I2CON I2Cn_BA+0x00 C Control Register 0x0000_0000 n=0,1 Reserved Reserved Reserved ENS1 Reserved Bits Description Reserved [31:8] Reserved. Interrupt Enable Bit 0 = I C interrupt Disabled.
Page 407 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller acknowledging the data sent by transmitter. When AA=0 prior to address or data received, a Not acknowledged (high level to I2Cn_SDA) will be returned during the acknowledge clock pulse on the I2Cn_SCL line. [1:0] Reserved Reserved.
Page 408 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller C Data Register (I2CDAT) Register Offset Description Reset Value I2CDAT I2Cn_BA+0x08 C Data Register 0x0000_0000 n=0,1 Reserved Reserved Reserved I2CDAT Bits Description [31:8] Reserved Reserved. C Data Register [7:0] I2CDAT This field is located with the 8-bit transferred data of I C serial port.
Page 409 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller C Status Register (I2CSTATUS ) Register Offset Description Reset Value I2CSTATUS I2Cn_BA+0x0C C Status Register 0x0000_00F8 n=0,1 Reserved Reserved Reserved I2CSTATUS Bits Description [31:8] Reserved Reserved. C Status Register There are 26 possible status codes. When I2CSTATUS contains 0xF8, no serial interrupt is requested.
Page 410 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller C Clock Divided Register (I2CLK) Register Offset Description Reset Value I2CLK I2Cn_BA+0x10 C Clock Divided Register 0x0000_0000 n=0,1 Reserved Reserved Reserved I2CLK Bits Description [31:8] Reserved Reserved. C Clock Divided Register [7:0] I2CLK The I...
Page 411 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller C Time-out Counter Register (I2CTOC) Register Offset Description Reset Value I2CTOC I2Cn_BA+0x14 C Time-out Counter Register 0x0000_0000 n=0,1 Reserved Reserved Reserved Reserved ENTI DIV4 Bits Description [31:3] Reserved Reserved. Time-Out Counter Enable Bit 0 = Disabled.
Page 412 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller C Slave Address Register (I2CADDRx) Register Offset Description Reset Value I2CADDR0 I2Cn_BA+0x04 C Slave Address Register0 0x0000_0000 n=0,1 I2CADDR1 I2Cn_BA+0x18 C Slave Address Register1 0x0000_0000 n=0,1 I2CADDR2 I2Cn_BA+0x1C C Slave Address Register2 0x0000_0000 n=0,1 I2CADDR3...
Page 413 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller C Slave Address Mask Register (I2CADMx) Register Offset Description Reset Value I2CADM0 I2Cn_BA+0x24 C Slave Address Mask Register0 0x0000_0000 n=0,1 I2CADM1 I2Cn_BA+0x28 C Slave Address Mask Register1 0x0000_0000 n=0,1 I2CADM2 I2Cn_BA+0x2C C Slave Address Mask Register2 0x0000_0000 n=0,1...
Page 414 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller C Wake-up Control Register (I2CWKUPCON) Register Offset Description Reset Value I2CWKUPCON I2Cn_BA+0x3C C Wake-up Control Register 0x0000_0000 n=0,1 Reserved Reserved Reserved Reserved WKUPEN Bits Description [31:1] Reserved Reserved. C Wake-Up Enable Bit WKUPEN 0 = I C wake-up function Disabled.
Page 415 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller C Wake-up Status Register (I2CWKUPSTS) Register Offset Description Reset Value I2CWKUPSTS I2Cn_BA+0x40 C Wake-up Status Register 0x0000_0000 n=0,1 Reserved Reserved Reserved Reserved WKUPIF Bits Description [31:1] Reserved Reserved. C Wake-Up Flag 0 = Chip is not woken-up from Power-down mode by I WKUPIF 1 = Chip is woken-up from Power-down mode by I...
Page 416: Serial Peripheral Interface (Spi)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.15 Serial Peripheral Interface (SPI) 6.15.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi- ®...
Page 417: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.15.3 Block Diagram Status/Control SPIn_CLK Register Interface SPIn_SS0 Control SYNC Gray Control Codec Pad MUX SPIn_MOSI0 Peripheral Clock Core Logic 8 Level TX Buffer PDMA SPIn_MISO0 Control 8 Level RX Buffer Figure 6.15-1 SPI Block Diagram 6.15.4 Basic Configuration The basic configurations of SPI0 are as follows:...
Page 418: Figure 6.15-2 Spi Master Mode Application Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller The SPI controller needs the SPI peripheral clock to drive the SPI logic unit to perform the data transfer. The SPI bus clock is the clock presented on SPIn_CLK pin. The SPI peripheral clock rate is determined by the settings of clock source, BCn option and clock divisor.
Page 419: Figure 6.15-4 32-Bit In One Transaction
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Transmit/Receive Bit Length The bit length of a transaction word is defined in TX_BIT_LEN bit field (SPI_CNTRL[7:3]). It can be configured up to 32-bit length in a transaction word for transmitting and receiving. SPIn_SS0 SPIn_CLK SPIn_MISO0...
Page 420 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller output pins SPIn_SS0. In Slave mode, the off-chip master device drives the slave select signal from the SPIn_SS0 input pin to this SPI controller. In Master and Slave mode, the active state of slave select signal can be programmed to low or high active in SS_LVL (SPI_SSR[2]), and SS_LTRIG (SPI_SSR[4]) defines the slave select signal SPIn_SS0 is level-triggered or edge- triggered.
Page 421: Figure 6.15-5 Variable Bus Clock Frequency
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller cycle of SPI clock of a transaction, and the bit field VARCLK[28:27] defines the third clock cycle, and so on. The VARCLK[0] has no meaning. The following figure shows the timing relationship among the SPI bus clock, the VARCLK setting, the DIVIDER setting and the DIVIDER2 setting.
Page 422: Figure 6.15-7 Timing Waveform For Byte Suspend
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.15.5.5 Byte Suspend Function In Master mode, if REORDER (SPI_CNTRL[19]) is set to 1, a suspend interval of 0.5 ~ 15.5 SPI clock periods will be inserted by hardware between two successive bytes in a transaction word. Both settings of byte suspend interval and word suspend interval are configured in SP_CYCLE (SPI_CNTRL[15:12]).
Page 423: Figure 6.15-8 Bit Sequence Of Dual Output Mode
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPIn_SS0 SPIn_CLK SPIn_MOSI0 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 Master output Output Slave input SPIn_MISO0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1...
Page 424: Figure 6.15-10 Fifo Mode Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller The received FIFO buffer is also an 8-layer depth, 32-bit wide, first-in, first-out register buffer. The receive control logic will store the received data to this buffer. The FIFO buffer data can be read from SPI_RX0 register by software.
Page 425: Timing Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller RX_FULL flag will be set to 1. The SPI controller will stop receiving data until the SPI_RX0 register is read by software. In Slave mode, when the FIFO bit is set as 1, the GO_BUSY bit will be set as 1 by hardware automatically.
Page 426: Figure 6.15-11 Spi Timing In Master Mode
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller TX_BIT_LEN (SPI_CNTRL[7:3]), and transmitting/receiving data from MSB or LSB first in LSB (SPI_CNTRL[10]). User can also select which edge of SPI clock to transmit/receive data in TX_NEG/RX_NEG (SPI_CNTRL[2:1]). Four SPI timing diagrams for master/slave operations and the related settings are shown below.
Page 427: Figure 6.15-13 Spi Timing In Slave Mode
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SS_LVL=1 SPIn_SS0 SS_LVL=0 CLKP=0 SPIn_CLK CLKP=1 SPIn_MISO0 TX0[6] TX0[0] TX0[7] TX0[6] TX0[7] TX0[0] SPIn_MOSI0 RX0[6] RX0[0] RX0[7] RX0[6] RX0[7] RX0[0] Slave Mode: CNTRL[SLVAE]=1, CNTRL[LSB]=0, CNTRL[TX_BIT_LEN]=0x08 1. CNTRL[CLKP]=0, CNTRL[TX_NEG]=1, CNTRL[RX_NEG]=0 or 2. CNTRL[CLKP]=1, CNTRL[TX_NEG]=0, CNTRL[RX_NEG]=1 Figure 6.15-13 SPI Timing in Slave Mode SS_LVL=1 SPIn_SS0...
Page 428: Programming Examples
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.15.7 Programming Examples Example 1: The SPI controller is set as a master to access an off-chip slave device with the following specifications:  Data bit is latched on positive edge of SPI clock. ...
Page 429 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 9) Go to 4) to continue another data transfer or set SSR [0] to 0 to inactivate the off-chip slave device. Example 2: The SPI controller is set as a slave device and connects with an off-chip master device.
Page 430: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.15.8 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SPI Base Address: SPI0_BA = 0x4003_0000 SPI1_BA = 0x4003_4000 SPI_CNTRL SPIn_BA+0x00 Control and Status Register 0x0500_3004 n=0,1 SPI_DIVIDER...
Page 431: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.15.9 Register Description SPI Control and Status Register (SPI_CNTRL) Register Offset Description Reset Value SPI_CNTRL SPIn_BA+0x00 Control and Status Register 0x0500_3004 Reserved TX_FULL TX_EMPTY RX_FULL RX_EMPTY VARCLK_EN Reserved FIFO Reserved REORDER SLAVE SP_CYCLE CLKP...
Page 432 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller FIFO Mode EnableBit 0 = FIFO mode Disabled. 1 = FIFO mode Enabled. Note1: Before enabling FIFO mode, the other related settings should be set in advance. Note2: In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 [21] FIFO automatically after writing data to the transmit FIFO buffer;...
Page 433 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 0 = SPI bus clock is idle low. 1 = SPI bus clock is idle high. Send LSB First 0 = The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first.
Page 434 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPI Divider Register (SPI_DIVIDER) Register Offset Description Reset Value SPI_DIVIDER SPIn_BA+0x04 Clock Divider Register 0x0000_0000 Reserved DIVIDER2 Reserved DIVIDER Bits Description [31:24] Reserved Reserved. Clock Divider 2 Register (Master Only) The value in this field is the 2 frequency divider for generating the second clock of the variable clock function.
Page 435 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPI Slave Select Register (SPI_SSR) Register Offset Description Reset Value SPI_SSR SPIn_BA+0x08 Slave Select Register 0x0000_0000 Reserved Reserved Reserved Reserved LTRIG_FLAG SS_LTRIG AUTOSS SS_LVL Reserved Bits Description [31:6] Reserved Reserved. Level Trigger Accomplish Flag In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.
Page 436 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller active state and writing 0 sets the line back to inactive state. If the AUTOSS bit is set, writing 0 to this field will keep the SPIn_SPISS0 line at inactive state; writing 1 to this field will select SPIn_SPISS0 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time.
Page 437 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPI Data Receive Register (SPI_RX) Register Offset Description Reset Value SPI_RX0 SPIn_BA+0x10 Data Receive Register 0 0x0000_0000 Bits Description Data Receive Register The data receive register holds the datum received from SPI data input pin. If FIFO mode is disabled, the last received data can be accessed through software by reading this [31:0] register.
Page 438 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPI Data Transmit Register (SPI_TX) Register Offset Description Reset Value SPI_TX0 SPIn_BA+0x20 Data Transmit Register 0 0x0000_0000 Bits Description Data Transmit Register The data transmit registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CNTRL register.
Page 439 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPI Variable Clock Pattern Register (SPI_VARCLK) Register Offset Description Reset Value SPI_VARCLK SPIn_BA+0x34 Variable Clock Pattern Register 0x007F_FF87 VARCLK VARCLK VARCLK VARCLK Bits Description Variable Clock Pattern This register defines the clock pattern of the SPI transfer. If the variable clock function is VARCLK [31:0] disabled, this setting is unmeaning.
Page 440 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPI DMA Control Register (SPI_DMA) Register Offset Description Reset Value SPI_DMA SPIn_BA+0x38 SPI DMA Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PDMA _RST RX_DMA_GO TX_DMA_GO Bits Description [31:2] Reserved Reserved. PDMA Reset 0 = No effect.
Page 441 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPI Control and Status Register 2 (SPI_CNTRL2) Register Offset Description Reset Value SPI_CNTRL2 SPIn_BA+0x3C Control and Status Register 2 0x0000_1000 Reserved Reserved SS_INT_OPT DUAL_ DUAL_ SLV_START SSTA_ Reserved SLV_ABORT NOSLVSEL IO_EN IO_DIR _INTSTS INTEN...
Page 442 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Slave 3-Wire Mode Start Interrupt EnableBit Used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer SSTA_INTEN [10]...
Page 443 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPI FIFO Control Register (SPI_FIFO_CTL) Register Offset Description Reset Value SPI_FIFO_CTL SPIn_BA+0x40 SPI FIFO Control Register 0x4400_0000 Reserved TX_THRESHOLD Reserved RX_THRESHOLD TIMEOUT_ Reserved Reserved INTEN Reserved RXOV_ Reserved Reserved TX_INTEN RX_INTEN TX_CLR RX_CLR INTEN...
Page 444 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 1 = RX threshold interrupt Enabled. Clear Transmit FIFO Buffer 0 = No effect. TX_CLR 1 = Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1.
Page 445 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller SPI Status Register (SPI_STATUS) Register Offset Description Reset Value SPI_STATUS SPIn_BA+0x44 SPI Status Register 0x0500_0000 TX_FIFO_COUNT TX_FULL TX_EMPTY RX_FULL RX_EMPTY Reserved TIMEOUT Reserved SLV_START RX_FIFO_COUNT Reserved _INTSTS Reserved TX_INTSTS Reserved Reserved RX_INTSTS OVERRUN Bits...
Page 446 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Note: This bit will be cleared by writing 1 to itself. [19:17] Reserved Reserved. SPI Unit Transfer Interrupt Flag It is a mutual mirror bit of SPI_CNTRL[16]. [16] 0 = No transaction has been finished since this bit was cleared to 0. 1 = SPI controller has finished one unit transfer.
Page 447: Usb Device Controller (Usbd)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.16 USB Device Controller (USBD) 6.16.1 Overview There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/ isochronous transfer types, and use High Internal RC Oscillator (HIRC48M) obtain to crystal-less option.
Page 448: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.16.3 Block Diagram Clock NVIC Generator VBUS Floating Floating Detection Interrupt Detection DPLL Control Control De-bouncing Status Registers USB_D+ APB Bus RXDP Endpoint USB_D- RXDM Control SRAM USB_VBUS Buffer (512 Control Bytes) Transceiver Figure 6.16-1 USB Device Block Diagram...
Page 449 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller and data buffer status in each endpoint. 6.16.5.3 Digital Phase Lock Loop (DPLL) The bit rate of USB data is 12 MHz. The DPLL uses the 48 MHz which comes from the clock controller to lock the input data RXDP and RXDM.
Page 450: Figure 6.16-2 Wake-Up Interrupt Operation Flow
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Wake Up Enable System Power Down System Wake-up Wait 20ms Wake-up Interrupt Figure 6.16-2 Wake-up Interrupt Operation Flow USB interrupt is used to notify users of any USB event on the bus, and user can read EPSTS (USB_EPSTS[31:8]) and EPEVT7~0 (USB_INTSTS[23:16]) to take necessary responses.
Page 451: Figure 6.16-3 Endpoint Sram Structure
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller USB SRAM = USBD_BA + 0x0100h USB SRAM Start Address Setup Token Buffer: 8 bytes BUFSEG0 = 0x008 EP0 SA = USBD_BA + 0x0108h EP0 SRAM Buffer: 64 bytes MXPLD0 = 0x40 BUFSEG1 = 0x048 EP1 SA = USBD_BA + 0x0148h EP1 SRAM Buffer: 64 bytes...
Page 452: Figure 6.16-4 Setup Transaction Followed By Data In Transaction
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.16.5.8 Handling Transactions with USB Device Peripheral User can use interrupt or poll USB_INTSTS to monitor the USB transactions. When transactions occur, USB_INTSTS will be set by hardware and send an interrupt request to CPU (if related interrupt enabled), or user can poll USB_INTSTS to get these events without interrupt.
Page 453: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.16.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value USB Base Address: USBD_BA = 0x4006_0000 USB_INTEN USBD_BA+0x000 R/W USB Interrupt Enable Register 0x0000_0000 USB_INTSTS USBD_BA+0x004 R/W USB Interrupt Event Status Register...
Page 454 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller USB_BUFSEG4 USBD_BA+0x540 R/W Endpoint 4 Buffer Segmentation Register 0x0000_0000 USB_MXPLD4 USBD_BA+0x544 R/W Endpoint 4 Maximal Payload Register 0x0000_0000 USB_CFG4 USBD_BA+0x548 R/W Endpoint 4 Configuration Register 0x0000_0000 USB_CFGP4 USBD_BA+0x54C R/W Endpoint 4 Set Stall and Clear In/Out Ready Control Register 0x0000_0000 USB_BUFSEG5 USBD_BA+0x550 R/W Endpoint 5 Buffer Segmentation Register...
Page 455: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.16.7 Register Description USB Interrupt Enable Register (USB_INTEN) Register Offset Description Reset Value USB_INTEN USBD_BA+0x000 R/W USB Interrupt Enable Register 0x0000_0000 Reserved Reserved INNAK_EN Reserved WAKEUP_EN Reserved WAKEUP_IE FLDET_IE USB_IE BUS_IE Bits Description Reserved...
Page 456 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller USB Interrupt Event Status Register (USB_INTSTS) Register Offset Description Reset Value USB_INTSTS USBD_BA+0x004 R/W USB Interrupt Event Status Register 0x0000_0000 SETUP Reserved EPEVT7 EPEVT6 EPEVT5 EPEVT4 EPEVT3 EPEVT2 EPEVT1 EPEVT0 Reserved WAKEUP_ Reserved SOF_STS...
Page 457 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 0 = No event occurred on endpoint 2. 1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1]. Endpoint 1’s USB Event Status 0 = No event occurred on endpoint 1.
Page 458 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller USB Device Function Address Register (USB_FADDR) A 7-bit value is used as the address of a device on the USB BUS. Register Offset Description Reset Value USB_FADDR USBD_BA+0x008 R/W USB Device Function Address Register 0x0000_0000 Reserved Reserved...
Page 459 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller USB Endpoint Status Register (USB_EPSTS) Register Offset Description Reset Value USBD_BA+0x00 USB_EPSTS USB Endpoint Status Register 0x0000_0000 EPSTS7 EPSTS6 EPSTS5 EPSTS5 EPSTS4 EPSTS3 EPSTS2 EPSTS2 EPSTS1 EPSTS0 OVERRUN Reserved Bits Description Endpoint 7 Bus Status These bits are used to indicate the current status of this endpoint 000 = In ACK.
Page 460 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 000 = In ACK. 001 = In NAK. 010 = Out Packet Data0 ACK. 110 = Out Packet Data1 ACK. 011 = Setup ACK. 111 = Isochronous transfer end. Endpoint 3 Bus Status These bits are used to indicate the current status of this endpoint 000 = In ACK.
Page 461 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller USB Bus Status and Attribution Register (USB_ATTR) Register Offset Description Reset Value USB_ATTR USBD_BA+0x010 R/W USB Bus Status and Attribution Register 0x0000_0040 Reserved Reserved Reserved BYTEM PWRDN DPPU_EN USB_EN Reserved RWAKEUP PHY_EN TIMEOUT RESUME...
Page 462 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Resume Status 0 = No bus resume. RESUME 1 = Resume from suspend. Note: This bit is read only. Suspend Status 0 = Bus no suspend. SUSPEND 1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. Note: This bit is read only.
Page 463 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Floating detection Register (USB_FLDET) Register Offset Description Reset Value USB_FLDET USBD_BA+0x014 R USB Floating Detection Register 0x0000_0000 Reserved Reserved Reserved Reserved FLDET Bits Description [31:1] Reserved Reserved. Device Floating Detected FLDET 0 = Controller is not attached into the USB host.
Page 464 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Buffer Segmentation Register (USB_STBUFSEG) For Setup token only. Register Offset Description Reset Value USBD_BA+0x01 USB_STBUFSEG Setup Token Buffer Segmentation Register 0x0000_0000 Reserved Reserved Reserved STBUFSEG[8] STBUFSEG[7:3] Reserved Bits Description [31:9] Reserved Reserved.
Page 465 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller USB Frame Number Register (USBD_FN) Register Offset R/W Description Reset Value USBD_FN USBD_BA+0x08C R USB Frame Number Register 0x0000_0XXX Reserved Reserved Reserved Bits Description [31:11] Reserved Reserved. Frame Number [10:0] These bits contain the 11-bits frame number in the last received SOF packet. Aug, 2018 Page 465 of 497 Rev 1.00...
Page 466 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Buffer Segmentation Register (USB_BUFSEGx) Register Offset Description Reset Value USBD_BA+0x50 USB_BUFSEG0 Endpoint 0 Buffer Segmentation Register 0x0000_0000 USBD_BA+0x51 USB_BUFSEG1 Endpoint 1 Buffer Segmentation Register 0x0000_0000 USBD_BA+0x52 USB_BUFSEG2 Endpoint 2 Buffer Segmentation Register 0x0000_0000 USBD_BA+0x53 USB_BUFSEG3...
Page 467 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Maximal Payload Register (USB_MXPLDx) Register Offset Description Reset Value USB_MXPLD0 USBD_BA+0x504 R/W Endpoint 0 Maximal Payload Register 0x0000_0000 USB_MXPLD1 USBD_BA+0x514 R/W Endpoint 1 Maximal Payload Register 0x0000_0000 USB_MXPLD2 USBD_BA+0x524 R/W Endpoint 2 Maximal Payload Register 0x0000_0000 USB_MXPLD3 USBD_BA+0x534 R/W...
Page 468 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Configuration Register (USB_CFGx) Register Offset Description Reset Value USB_CFG0 USBD_BA+0x508 R/W Endpoint 0 Configuration Register 0x0000_0000 USB_CFG1 USBD_BA+0x518 R/W Endpoint 1 Configuration Register 0x0000_0000 USB_CFG2 USBD_BA+0x528 R/W Endpoint 2 Configuration Register 0x0000_0000 USB_CFG3 USBD_BA+0x538 R/W...
Page 469 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Isochronous Endpoint This bit is used to set the endpoint as Isochronous endpoint, no handshake. ISOCH 0 = No Isochronous endpoint. 1 = Isochronous endpoint. Endpoint Number [3:0] EP_NUM These bits are used to define the endpoint number of the current endpoint. Aug, 2018 Page 469 of 497 Rev 1.00...
Page 470 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Extra Configuration Register (USB_CFGPx) Register Offset Description Reset Value USBD_BA+0x50 USB_CFGP0 Endpoint 0 Set Stall and Clear In/Out Ready Control Register 0x0000_0000 USBD_BA+0x51 USB_CFGP1 Endpoint 1 Set Stall and Clear In/Out Ready Control Register 0x0000_0000 USBD_BA+0x52 USB_CFGP2...
Page 471 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller USB Drive SE0 Register (USB_DRVSE0) Register Offset Description Reset Value USB_DRVSE0 USBD_BA+0x090 R/W USB Drive SE0 Control Register 0x0000_0001 Reserved Reserved Reserved Reserved DRVSE0 Bits Description Reserved [31:1] Reserved. Drive Single Ended Zero In USB Bus The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
Page 472: Analog-To-Digital Converter (Adc)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.17 Analog-to-Digital Converter (ADC) 6.17.1 Overview ® The NuMicro NUC029LEE/NUC029SEE contains one 12-bit successive approximation analog- to-digital converters (SAR A/D converter) with 12 input channels. The A/D converter supports three operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be started by software, PWM Center-aligned trigger and external STADC pin.
Page 473: Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.17.3 Block Diagram VALID & OVERRUN PDMA request Digital Control Logics ADC_INT STADC & ADC Clock Generator RSLT[11:0] Successive Approximations Register 12-bit DAC ADC0 ADC1 Analog Control ADC7 Logics AIN[7]* TEMP Comparator Reserved ADC11...
Page 474: Functional Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.17.5 Functional Description The A/D converter operates by successive approximation with 12-bit resolution. The ADC has three operation modes: Single mode, Single-cycle Scan mode and Continuous Scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, software must clear ADST bit (ADCR[11]) to 0.
Page 475: Figure 6.17-3 Single Mode Conversion Timing Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADC_CLK ADST (ADCR[11]) sample ADDRx[11:0] ADDRx[11:0] (ADCR[0]) Figure 6.17-3 Single Mode Conversion Timing Diagram 6.17.5.3 Single-Cycle Scan Mode In single-cycle scan mode, A/D conversion will sample and convert the specified channels once in the sequence from the smallest number enabled channel to the largest number enabled channel.
Page 476: Figure 6.17-4 Single-Cycle Scan On Enabled Channels Timing Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADST (ADCR[11]) CHANNEL[3:0] 0000b 0010b 0011b 1000b sample SAR[12:0] ADDR0 ADDR2 ADDR3 ADDR8 Single-cycle scan on channel 0, 2, 3 and 8 (ADCHER[12:0] = 0000100001101b) Figure 6.17-4 Single-Cycle Scan on Enabled Channels Timing Diagram 6.17.5.4 Continuous Scan Mode In continuous scan mode, A/D conversion is performed sequentially on the specified channels that enabled by CHEN bits (ADCHER[12:0] ).
Page 477: Figure 6.17-5 Continuous Scan On Enabled Channels Timing Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADST (ADCR[11]) Software clear ADST CHANNEL[3:0] 0000b 0010b 0011b 1000b 0000b 0010b 0011b 1000b 0000b sample ADDR0 ADDR2 ADDR3 ADDR8 Continuous scan on channel 0, 2, 3 and 8 (ADCHER[12:0] = 0000100001101b) Figure 6.17-5 Continuous Scan on Enabled Channels Timing Diagram 6.17.5.5 Internal Reference Voltage The band-gap voltage reference (V...
Page 478: Figure 6.17-6 Vbg For Measuring Av Dd Application Block Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller (2.5~5.5V) Internal Band-gap Channel 7 12-bit SAR ADC RSLT(ADDR7[15:0]) PRESEL(ADCHER[9:8]) = 2'b01 Channel Setting: Select ADC Channel 7 Source as Internal Band-gap and enable ADC Channe 7. ADC->ADCHER = 0x00000180; Figure 6.17-6 V for Measuring AV Application Block Diagram For example, the V...
Page 479: Figure 6.17-7 A/D Conversion Result Monitor Logics Diagram
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller (ADCR[8]) to 1 and the TRGS (ADCR[5:4]) to 11b. When PWM enables trigger ADC function, the PWM will generate a trigger signal to ADC when PWM counter is running to PWM center point. 6.17.5.8 Conversion Result Monitor by Compare Function The ADC controller provide two sets of compare register ADCMPR0 and ADCMPR1, to monitor maximum two specified channels conversion result from A/D conversion controller, refer to Figure...
Page 480: Figure 6.17-8 A/D Controller Interrupt
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADF(ADSR[0]) ADIE(ADCR[1]) CMPF0(ADSR[1]) ADC_INT CMPIE(ADCMPR0[1]) CMPF1(ADSR[2]) CMPIE(ADCMPR1[1]) Figure 6.17-8 A/D Controller Interrupt 6.17.5.10 Peripheral DMA Request When A/D conversion is finished, the conversion result will be loaded into ADDR register and VALID bit will be set to 1.
Page 481: Register Map
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.17.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value ADC Base Address: ADC_BA = 0x400E_0000 ADDR0 ADC_BA+0x00 ADC Data Register 0 0x0000_0000 ADDR1 ADC_BA+0x04...
Page 482: Register Description
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 6.17.7 Register Description ADC Data Registers (ADDR0 ~ ADDR11) Register Offset Description Reset Value ADDR0 ADC_BA+0x00 ADC Data Register 0 0x0000_0000 ADDR1 ADC_BA+0x04 ADC Data Register 1 0x0000_0000 ADDR2 ADC_BA+0x08 ADC Data Register 2 0x0000_0000 ADDR3 ADC_BA+0x0C...
Page 483: Figure 6.17-9 Adc Single-End Input Conversion Voltage And Conversion Result Mapping
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Overrun Flag 0 = Data in RSLT (ADDRx[15:0], x=0~11) is recent conversion result. 1 = Data in RSLT (ADDRx[15:0], x=0~11) is overwritten. [16] OVERRUN If converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone.
Page 484: Figure 6.17-10 Adc Differential Input Conversion Voltage And Conversion Result Mapping
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADC result in RSLT ADC result in RSLT (ADDRx[11:0], x=0~11) (ADDRx[15:0], x=0~11) Note: Vref voltage comes from Note: Vref voltage comes from (DMOF (ADCR[31]) = 0) (DMOF (ADCR[31]) = 1) AVDD for 64/48-pin package AVDD for 64/48-pin package 1111_1111_1111 0000_0111_1111_1111...
Page 485 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADC Control Register (ADCR) Register Offset Description Reset Value ADCR ADC_BA+0x20 ADC Control Register 0x0000_0000 DMOF Reserved Reserved Reserved ADST DIFFEN PTEN TRGEN TRGCOND TRGS ADMD ADIE ADEN Bits Description A/D Differential Input Mode Output Format 0 = A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format.
Page 486 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Differential Input Mode Control 0 = Single-end analog input mode. 1 = Differential analog input mode. ADC Analog Input Differential input Paired Channel plus minus ADC1 ADC2 ADC3 ADC4 [10] DIFFEN ADC5 ADC6 ADC7...
Page 487 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller A/D Converter Operation Mode 00 = Single conversion. 01 = Reserved. [3:2] ADMD 10 = Single-cycle scan. 11 = Continuous scan. When changing the operation mode, software should disable ADST bit (ADCR[11]) firstly. A/D Interrupt Enable Bit 0 = A/D interrupt function Disabled.
Page 488 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADC Channel Enable Register (ADCHER) Register Offset Description Reset Value ADCHER ADC_BA+0x24 ADC Channel Enable Register 0x0000_0000 Reserved Reserved Reserved CHEN1 PRESEL CHEN Bits Description [31:14] Reserved Reserved. Analog Input Channel Enable Bit 1 Set CHEN[14:10] to enable the corresponding analog input channel 11 ~ 8.
Page 489 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADC Compare Register 0/1 (ADCMPR0/1) Register Offset Description Reset Value ADCMPR0 ADC_BA+0x28 ADC Compare Register 0 0x0000_0000 ADCMPR1 ADC_BA+0x2C ADC Compare Register 1 0x0000_0000 Reserved CMPD[11:8] CMPD[7:0] Reserved CMPMATCNT Reserved CMPCH CMPCOND CMPIE CMPEN...
Page 490 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Compare Channel Selection 0000 = Channel 0 conversion result is selected to be compared. 0001 = Channel 1 conversion result is selected to be compared. 0010 = Channel 2 conversion result is selected to be compared. 0011 = Channel 3 conversion result is selected to be compared.
Page 491 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADC Status Register (ADSR) Register Offset Description Reset Value ADSR ADC_BA+0x30 ADC Status Register 0x0000_0000 OVERRUN1 VALID1 OVERRUN0 VALID0 CHANNEL BUSY CMPF1 CMPF0 Bits Description Overrun Flag [31:28] OVERRUN1 It is a mirror to OVERRUN bit (ADDR8~11[16]). It is read only.
Page 492 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller Compare Flag When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self. CMPF0 0 = Conversion result in ADDR does not meet ADCMPR0 setting.
Page 493 NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ADC PDMA Current Transfer Data Register (ADPDMA) Register Offset Description Reset Value ADPDMA ADC_BA+0x40 ADC PDMA Current Transfer Data Register 0x0000_0000 Reserved Reserved AD_PDMA AD_PDMA AD_PDMA Bits Description [31:18] Reserved Reserved. ADC PDMA Current Transfer Data Register When PDMA transferring, read this register can monitor current PDMA transfer data.
Page 494: Electrical Characteristics
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller ELECTRICAL CHARACTERISTICS ® For information on NuMicro NUC029LEE/NUC029SEE electrical characteristics, please refer to ® NuMicro NUC029LEE/NUC029SEE Datasheet. Aug, 2018 Page 494 of 497 Rev 1.00...
Page 495: Package Dimensions
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller PACKAGE DIMENSIONS 8.1 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm) Aug, 2018 Page 495 of 497 Rev 1.00...
Page 496: 48-Pin Lqfp (7X7X1.4 Mm Footprint 2.0 Mm)
NuMicro® NUC029LEE/NUC029SEE ® ® 32-bit Arm Cortex -M0 Microcontroller 8.2 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) Aug, 2018 Page 496 of 497 Rev 1.00...
Page 497: Revision History
Initial version. Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

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