Nuvoton NuMicro NUC442 Series Technical Reference Manual
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Nuvoton NuMicro NUC442 Series Technical Reference Manual

32-bit microcontroller
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NuMicro NUC442/NUC472 Series Technical Reference Manual
NuMicro™ NUC442/NUC472 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
May 23, 2014
32-bit Microcontroller
www.nuvoton.com
Page 1 of 1386
®
ARM Cortex
-M4
Rev.1.05

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Summary of Contents for Nuvoton NuMicro NUC442 Series

  • Page 1 The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.

  • Page 2: Table Of Contents

    NuMicro NUC442/NUC472 Series Technical Reference Manual TABLE OF CONTENTS GENERAL DESCRIPTION ............19 NuMicro NUC442/NUC472 General Description ........19 FEATURES ................20 NuMicro NUC442 Features – Connectivity Series ........20 NuMicro NUC472 Features - Advanced Series ........28 ABBREVIATIONS ............... 36 PARTS INFORMATION LIST AND PIN CONFIGURATION .....
  • Page 3 NuMicro NUC442/NUC472 Series Technical Reference Manual System Power Distribution ..............270 6.2.3 System Memory Map ................271 6.2.4 System Control Registers ............... 274 6.2.5 System Timer (SysTick) ................. 322 6.2.6 Nested Vectored Interrupt Controller (NVIC) ..........326 6.2.7 System Control Register Map and Description ..........345 6.2.8 Clock Controller ................
  • Page 4 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Map ..................441 6.6.5 Register Description ................444 6.6.6 Controller Area Network (CAN) ............475 Overview ................... 475 6.7.1 Features .................... 475 6.7.2 Block Diagram ..................476 6.7.3 Functional Description ................477 6.7.4 Test Mode ..................
  • Page 5 NuMicro NUC442/NUC472 Series Technical Reference Manual Overview ..................657 6.11.1 Features ..................657 6.11.2 Block Diagram .................. 658 6.11.3 Functional Description ................. 658 6.11.4 Register Map..................666 6.11.5 Register Description ................667 6.11.6 Ethernet MAC Controller (EMAC) (NUC472 Only) ........680 6.12 Overview ..................
  • Page 6 NuMicro NUC442/NUC472 Series Technical Reference Manual Overview ..................821 6.15.1 Features ..................822 6.15.2 Functional Description ................. 823 6.15.3 Operation Modes ................825 6.15.4 Protocol Registers ................833 6.15.5 Register Map..................838 6.15.6 Register Description ................839 6.15.7 S) ................. 849 6.16 S Controller (I Overview ..................
  • Page 7 NuMicro NUC442/NUC472 Series Technical Reference Manual Interrupt Sources ................920 6.19.4 Register Map..................921 6.19.5 Register Description ................922 6.19.6 PS/2 Device Controller (PS2D) ............925 6.20 Overview ..................925 6.20.1 Features ..................925 6.20.2 Block Diagram .................. 926 6.20.3 Functional Description .................
  • Page 8 NuMicro NUC442/NUC472 Series Technical Reference Manual Operation of Quadrature Encoder Interface ..........1041 6.23.5 Compare Function ................1045 6.23.6 Reload Counter by Pin IDX ..............1045 6.23.7 Capture QEI Counter ................ 1046 6.23.8 QEI Interrupt Architecture ..............1047 6.23.9 Register Map ................1049 6.23.10 Register Description ..............
  • Page 9 NuMicro NUC442/NUC472 Series Technical Reference Manual Programming Flows ................. 1166 6.27.6 Register Map.................. 1169 6.27.7 Register Description ................. 1170 6.27.8 Timer Controller (TIMER) ............... 1184 6.28 Overview ..................1184 6.28.1 Features ..................1184 6.28.2 Block Diagram ................1185 6.28.3 Basic Configuration ................1186 6.28.4 Functional Description ...............
  • Page 10 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Description ................. 1237 6.31.8 USB 2.0 Device Controller ............. 1266 6.32 Overview ..................1266 6.32.1 Features ..................1266 6.32.2 Block Diagram ................1267 6.32.3 Functional Description ............... 1267 6.32.4 Registers Map ................1270 6.32.5 Register Description .................
  • Page 11 NuMicro NUC442/NUC472 Series Technical Reference Manual List of Figure Figure 4.1-1 NuMicro NUC442/NUC472 Series Selection Code ..........40 Figure 4.2-1 NuMicro NUC442Rxxxx LQFP 64-pin Diagram ............41 Figure 4.2-2 NuMicro NUC442Vxxxx LQFP 100-pin Diagram ............ 42 Figure 4.2-3 NuMicro NUC442Kxxxx LQFP 128-pin Diagram ............ 43 Figure 4.2-4 NuMicro...
  • Page 12 NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.6-3 ADC Clock Control ....................429 Figure 6.6-4 Single Sampling Mode Conversion Timing Diagram ..........431 Figure 6.6-5 SAMPLE00~SAMPLE03 and SAMPLE10~SAMPLE13 Control Block Diagram..431 Figure 6.6-6 SAMPLE04~SAMPLE07 and SAMPLE14~SAMPLE17 Control Block Diagram..432 Figure 6.6-7 SAMPLE Module Conversion Priority Arbitrator Diagram ........
  • Page 13 NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.10-2 Embedded Description Table Data Structure ............611 Figure 6.10-3 Embedded Description Table Data Structure ............612 Figure 6.10-4 Embedded Description Table Data Structure ............613 Figure 6.11-1 EBI Block Diagram ....................658 Figure 6.11-2 Connection of 16-bit EBI Data Width with 16-bit Device ........
  • Page 14 NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.15-12 GC Mode ......................831 Figure 6.15-13 EEPROM Random Read ..................832 Figure 6.15-14 Protocol of EEPROM Random Read..............833 Figure 6.15-15 I C Data Shifting Direction ................... 834 Figure 6.15-16 I C Time-out Count Block Diagram ..............836 Figure 6.16-1 I S Clock Control Diagram ..................
  • Page 15 NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.21-6 PWM Generator 4 Architecture Diagram ............... 945 Figure 6.21-7 PWM waveform of Edge-aligned type ..............946 Figure 6.21-8 Center-Aligned Mode Output Waveform ............... 947 Figure 6.21-9 PWM Center Aligned Interrupt Generate Timing Waveform ......... 948 Figure 6.21-10 PWM Double Buffering Timing Waveform ............
  • Page 16 NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.23-3 Noise Filter ......................1041 Figure 6.23-4 Noise Filter Sampling Clock Selection ..............1041 Figure 6.23-5 QEA/QEB/IDX Timing Requirement through Noise Filter ........1041 Figure 6.23-6 X4 Counting Mode ....................1042 Figure 6.23-7 X2 Counting Mode ....................1043 Figure 6.23-8 Compare Operation .....................
  • Page 17 NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.27-16 SPI Timing in Slave Mode ................. 1165 Figure 6.27-17 SPI Timing in Slave Mode (Alternate Phase of SPICLK) ........1166 Figure 6.28-1 Timer Controller Block Diagram ................1185 Figure 6.28-2 Clock Source of Timer Controller ................ 1185 Figure 6.28-3 Continuous Counting Mode .................
  • Page 18 NuMicro NUC442/NUC472 Series Technical Reference Manual List of Tables Table 1.1-1 Key Features Support Table ..................19 Table 3.1-1 List of Abbreviations ....................37 Table 6.2-1 Address Space Assignments for On-Chip Controllers ..........273 Table 6.2-2 Exception Model ....................... 327 Table 6.2-3 Interrupt Number Table .....................

  • Page 19: General Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual GENERAL DESCRIPTION NuMicro NUC442/NUC472 General Description ® The NuMicro NUC442 Connectivity series with embedded Cortex -M4F core with DSP extensions and a Floating Point Unit runs up to 84 MHz with 256/512 Kbytes embedded flash memories and 64K-byte embedded SRAM.

  • Page 20: Features

    NuMicro NUC442/NUC472 Series Technical Reference Manual FEATURES NuMicro NUC442 Features – Connectivity Series  Core ® ® – Cortex -M4 core running up to 84 MHz – Supports DSP extension  Supports hardware divider – Supports IEEE 754 compliant Floating-point Unit (FPU) –...
  • Page 21 NuMicro NUC442/NUC472 Series Technical Reference Manual – Supports one PLL, up to 84 MHz for high performance system operation, sourced from  Built-in 22.1184 MHz high speed RC oscillator  4~24 MHz external high speed crystal oscillator – Supports clock failure detection for system clock –...
  • Page 22 NuMicro NUC442/NUC472 Series Technical Reference Manual – Supports One-shot or Auto-reload PWM counter operation mode – Supports Edge-aligned or Center-aligned PWM counter type – Supports 8-bit dead zone with maximum divided 8 pre-scale – Supports brake function source from pin or comparator output –...
  • Page 23 NuMicro NUC442/NUC472 Series Technical Reference Manual – Supports RS-485 9-bit mode and direction control – Programmable baud-rate generator up to 1/16 system clock – Supports PDMA mode  Smart Card Interface – Supports up to six ISO-7816-3 ports – Compliant to ISO-7816-3 T=0, T=1 –...
  • Page 24 NuMicro NUC442/NUC472 Series Technical Reference Manual – Supports mono and stereo audio data – Supports I S and MSB justified data format – Each provides two 8-word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary –...
  • Page 25 NuMicro NUC442/NUC472 Series Technical Reference Manual – Resolution up to 3M pixel – YUV422 and RGB565 color format supported for data-in from CMOS sensor – YUV422, RGB565, RGB555 and Y-only color format supported for data storing to system memory – Planar and packet data format supported for data storing to system memory –...
  • Page 26 NuMicro NUC442/NUC472 Series Technical Reference Manual – AES accelerator  Supports hardware AES (Advanced Encryption Standard) accelerator  Supports 128-, 192- and 256-bit keys  Supports ECB, CBC, CFB, OFB and CTR modes  Compliant with NIST 800 38A – Secure Hash Function accelerator ...
  • Page 27 NuMicro NUC442/NUC472 Series Technical Reference Manual – LQFP 144-pin/ 128-pin/ 100-pin/ 64-pin May 23, 2014 Page 27 of 1386 Rev.1.05...

  • Page 28: Numicro Nuc472 Features - Advanced Series

    NuMicro NUC442/NUC472 Series Technical Reference Manual NuMicro NUC472 Features - Advanced Series  Core ® ® – Cortex -M4 core running up to 84 MHz – Supports DSP extension  Supports hardware divider – Supports IEEE 754 compliant Floating-point Unit (FPU) –...
  • Page 29 NuMicro NUC442/NUC472 Series Technical Reference Manual  4~24 MHz external high speed crystal oscillator – Supports clock failure detection for system clock – Supports exception (NMI) generated once a clock failure detected – Flexible selection for different applications – Supports clock out –...
  • Page 30 NuMicro NUC442/NUC472 Series Technical Reference Manual – Supports 8-bit dead zone with maximum divided 8 pre-scale – Supports brake function source from pin or comparator output – Supports mask function for each PWM pin – Supports independent, complementary, synchronized and group PWM output mode –...
  • Page 31 NuMicro NUC442/NUC472 Series Technical Reference Manual – Supports PDMA mode  Smart Card Interface – Supports up to six ISO-7816-3 ports – Compliant to ISO-7816-3 T=0, T=1 – Separate receive / transmit 4 bytes entry FIFO for data payloads – Programmable transmission clock frequency –...
  • Page 32 NuMicro NUC442/NUC472 Series Technical Reference Manual – Each provides two 8-word FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Each supports two PDMA requests, one for transmitting and the other for receiving ...
  • Page 33 NuMicro NUC442/NUC472 Series Technical Reference Manual – YUV422, RGB565, RGB555 and Y-only color format supported for data storing to system memory – Planar and packet data format supported for data storing to system memory – Image cropping supported with the cropping window up to 4096x2048 –...
  • Page 34 NuMicro NUC442/NUC472 Series Technical Reference Manual  Supports 128-, 192- and 256-bit keys  Supports ECB, CBC, CFB, OFB and CTR modes  Compliant with NIST 800 38A – Secure Hash Function accelerator  Supports hardware SHA (Secure Hash) accelerator ...
  • Page 35 NuMicro NUC442/NUC472 Series Technical Reference Manual  Operating Temperature: -40℃~105℃  Packages – All Green package (RoHS) – LQFP 176-pin/ 144-pin/ 128-pin/ 100-pin May 23, 2014 Page 35 of 1386 Rev.1.05...

  • Page 36: Abbreviations

    NuMicro NUC442/NUC472 Series Technical Reference Manual ABBREVIATIONS Acronym Description ACMP Analog Comparator Controller Analog-to-Digital Converter Advanced Encryption Standard Advanced Peripheral Bus Advanced High-Performance Bus Brown-out Detection Controller Area Network Debug Access Port Data Encryption Standard External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out Flash Memory Controller...

  • Page 37: Table 3.1-1 List Of Abbreviations

    NuMicro NUC442/NUC472 Series Technical Reference Manual Serial Peripheral Interface Samples per Second TDES Triple Data Encryption Standard Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID Universal Serial Bus Watchdog Timer WWDT Window Watchdog Timer Table 3.1-1 List of Abbreviations May 23, 2014 Page 37 of 1386 Rev.1.05...

  • Page 38: Parts Information List And Pin Configuration

    NuMicro NUC442/NUC472 Series Technical Reference Manual PARTS INFORMATION LIST AND PIN CONFIGURATION Selection Guide 4.1.1 NuMicro NUC442 Connectivity Series Selection Guide Connectivity NUC442JI8AE 16 114 6+6 4 LQFP144 16-ch NUC442JG8AE 256 16 114 6+6 4 LQFP144 16-ch NUC442KI8AE 16 100 6+6 4 LQFP128 16-ch...
  • Page 39 NuMicro NUC442/NUC472 Series Technical Reference Manual NUC472JG8AE 256 16 114 6+6 4 v LQFP144 16-ch NUC472KI8AE 16 101 6+6 4 v LQFP128 16-ch NUC472KG8AE 256 16 101 6+6 4 v LQFP128 16-ch NUC472VI8AE 6+5 4 v LQFP100 16-ch NUC472VG8AE 256 6+5 4 v LQFP100 16-ch...

  • Page 40: Figure 4.1-1 Numicro Nuc442/Nuc472 Series Selection Code

    NuMicro NUC442/NUC472 Series Technical Reference Manual Reserved or Memory size 4: Cortex-M4 N: - 40 C~ +85 E: - 40 C~+105 4: Connectivity Series 7: Advanced Series 8: 64 KB R: LQFP 64 10x10mm G: 256 KB V: LQFP 100 14x14mm I : 512 KB K: LQFP 128 14x14mm J: LQFP 144 20x20mm...

  • Page 41: Pin Configuration

    NuMicro NUC442/NUC472 Series Technical Reference Manual Pin Configuration 4.2.1 NuMicro NUC442 Pin Diagrams  4.2.1.1 NuMicro NUC442Rxxxx LQFP 64-pin INT2/EBI_MCLK/UART4_RXD/SC1_DAT/I2S1_DI/PC.0 EBI_AD13/TM3_CNT_OUT/UART4_TXD/SC1_CLK/I2S1_BCLK/PC.1 EBI_AD12/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2 LDO_CAP ECAP0_IC2/EBI_AD11/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3 PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3 ECAP0_IC1/EBI_AD10/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4 PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2 EBI_AD9/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6 PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1 EBI_AD8/SPI0_MOSI0/TM1_EXT/PC.7 NUC442 LQFP 64 PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0 SPI0_CLK/TM0_EXT/PC.8 PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20 LDO_CAP PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19 SPI0_SS0/ACMP0_P2/ADC0_4/PE.4 PA.8/SC0_RST/SPI3_CLK/PWM1_2/EPWM0_4/EBI_A18 SD0_CDn/SPI0_CLK/ACMP0_P1/ADC0_5/PE.5 PA.7/SC0_CLK/SPI3_SS0/PWM1_3/EPWM0_5/EBI_A17 EBI_nWR/SD0_CMD/SPI0_MISO0/ACMP0_P0/ADC0_6/PE.6...

  • Page 42: Figure 4.2-2 Numicro Nuc442Vxxxx Lqfp 100-Pin Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual  4.2.1.2 NuMicro NUC442Vxxxx LQFP 100-pin EBI_AD13/TM3_CNT_OUT/UART4_TXD/SC1_CLK/I2S1_BCLK/PC.1 EBI_AD12/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2 ECAP0_IC2/EBI_AD11/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3 LDO_CAP ECAP0_IC1/EBI_AD10/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4 PC.11/UART2_TXD/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3 ECAP0_IC0/EBI_MCLK/QEI0_A/CLKO/PC.5 PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2 EBI_AD9/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6 PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6 EBI_AD8/SPI0_MOSI0/TM1_EXT/PC.7 PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21 SPI0_CLK/TM0_EXT/PC.8 PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3 LDO_CAP PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2 PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1 INT4/ADC0_0/PE.0 PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0 NUC442 LQFP 100 TM2_CNT_OUT/ADC0_1/PE.1 PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20 SPI0_MISO0/ACMP0_O/ADC0_2/PE.2 PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19 SPI0_MOSI0/ACMP0_P3/ADC0_3/PE.3 PA.8/SC0_RST/SPI3_CLK/PWM1_2/EPWM0_4/EBI_A18 SPI0_SS0/ACMP0_P2/ADC0_4/PE.4 PA.7/SC0_CLK/SPI3_SS0/PWM1_3/EPWM0_5/EBI_A17 SD0_CDn/SPI0_CLK/ACMP0_P1/ADC0_5/PE.5...

  • Page 43: Figure 4.2-3 Numicro Nuc442Kxxxx Lqfp 128-Pin Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual  4.2.1.3 NuMicro NUC442Kxxxx LQFP 128-pin EBI_AD12/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2 ECAP0_IC2/EBI_AD11/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3 LDO_CAP ECAP0_IC1/EBI_AD10/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4 PC.11/UART2_TXD/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3 ECAP0_IC0/EBI_MCLK/QEI0_A/CLKO/PC.5 PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2 EBI_AD9/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6 PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6 EBI_AD8/SPI0_MOSI0/TM1_EXT/PC.7 PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21 SPI0_CLK/TM0_EXT/PC.8 PD.12/SC3_CLK/I2C4_SDA SD0_DAT3/SPI3_SS0/PF.2 PD.11/SC3_RST/TM3_CNT_OUT SD0_DAT2/SPI3_CLK/PF.3 PD.10/SC3_DAT/I2C4_SCL SD0_DAT1/SPI3_MISO0/PF.4 PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3 SD0_DAT0/SPI3_MOSI0/PF.5 PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2 SD0_CDn/UART2_RXD/PF.6 PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1 SD0_CMD/UART2_TXD/PF.7 PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0 SD0_CLK/UART2_RTS/PF.8 NUC442 LQFP 128 PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20 LDO_CAP PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19...

  • Page 44: Figure 4.2-4 Numicro Nuc442Jxxxx Lqfp 144-Pin Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual  4.2.1.4 NuMicro NUC442Jxxxx LQFP 144-pin EBI_AD13/TM3_CNT_OUT/UART4_TXD/SC1_CLK/I2S1_BCLK/PC.1 EBI_AD12/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2 LDO_CAP ECAP0_IC2/EBI_AD11/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3 ECAP0_IC1/EBI_AD10/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4 PC.11/UART2_TXD/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3 ECAP0_IC0/EBI_MCLK/QEI0_A/CLKO/PC.5 PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2 PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6 EBI_AD9/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6 PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21 EBI_AD8/SPI0_MOSI0/TM1_EXT/PC.7 SPI0_CLK/TM0_EXT/PC.8 PD.12/SC3_CLK/I2C4_SDA SD0_DAT3/SPI3_SS0/PF.2 PD.11/SC3_RST/TM3_CNT_OUT PD.10/SC3_DAT/I2C4_SCL SD0_DAT2/SPI3_CLK/PF.3 PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3 SD0_DAT1/SPI3_MISO0/PF.4 SD0_DAT0/SPI3_MOSI0/PF.5 PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2 PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1 PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0 PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20 SD0_CDn/UART2_RXD/PF.6 SD0_CMD/UART2_TXD/PF.7 PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19 NUC442 LQFP 144 SD0_CLK/UART2_RTS/PF.8 PA.8/SC0_RST/SPI3_CLK/PWM1_2/EPWM0_4/EBI_A18...

  • Page 45: Numicro Nuc472 Pin Diagrams

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.2.2 NuMicro NUC472 Pin Diagrams  4.2.2.1 NuMicro NUC472Vxxxx LQFP 100-pin EBI_AD13/EMAC_MII_RXERR/TM3_CNT_OUT/UART4_TXD/SC1_CLK/I2S1_BCLK/PC.1 EBI_AD12/EMAC_MII_RXDV/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2 ECAP0_IC2/EBI_AD11/EMAC_MII_RXD1/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3 LDO_CAP ECAP0_IC1/EBI_AD10/EMAC_MII_RXD0/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4 PC.11/UART2_TXD/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3 ECAP0_IC0/EBI_MCLK/EMAC_MII_RXCLK/QEI0_A/CLKO/PC.5 PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2 EBI_AD9/EMAC_MII_TXD0/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6 PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6 EBI_AD8/EMAC_MII_TXD1/SPI0_MOSI0/TM1_EXT/PC.7 PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21 EMAC_MII_TXEN/SPI0_CLK/TM0_EXT/PC.8 PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3 LDO_CAP PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2 PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1 PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0 INT4/ADC0_0/PE.0 NUC472 LQFP 100 TM2_CNT_OUT/ADC0_1/PE.1 PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20 SPI0_MISO0/ACMP0_O/ADC0_2/PE.2 PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19...

  • Page 46: Figure 4.2-6 Numicro Nuc472Kxxxx Lqfp 128-Pin Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual  4.2.2.2 NuMicro NUC472Kxxxx LQFP 128-pin EBI_AD12/EMAC_MII_RXDV/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2 ECAP0_IC2/EBI_AD11/EMAC_MII_RXD1/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3 LDO_CAP ECAP0_IC1/EBI_AD10/EMAC_MII_RXD0/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4 PC.11/UART2_TXD/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3 ECAP0_IC0/EBI_MCLK/EMAC_MII_RXCLK/QEI0_A/CLKO/PC.5 PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2 EBI_AD9/EMAC_MII_TXD0/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6 PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6 EBI_AD8/EMAC_MII_TXD1/SPI0_MOSI0/TM1_EXT/PC.7 PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21 EMAC_MII_TXEN/SPI0_CLK/TM0_EXT/PC.8 PD.12/SC3_CLK/I2C4_SDA EMAC_MII_RXD3/SD0_DAT3/SPI3_SS0/PF.2 PD.11/SC3_RST/TM3_CNT_OUT EMAC_MII_RXD2/SD0_DAT2/SPI3_CLK/PF.3 PD.10/SC3_DAT/I2C4_SCL EMAC_MII_COL0/SD0_DAT1/SPI3_MISO0/PF.4 PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3 EMAC_MII_CRS/SD0_DAT0/SPI3_MOSI0/PF.5 PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2 EMAC_MII_TXCLK/SD0_CDn/UART2_RXD/PF.6 PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1 EMAC_MII_TXD3/SD0_CMD/UART2_TXD/PF.7 PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0 EMAC_MII_TXD2/SD0_CLK/UART2_RTS/PF.8 NUC472 LQFP 128 PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20 LDO_CAP PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19...

  • Page 47: Figure 4.2-7 Numicro Nuc472Jxxxx Lqfp 144-Pin Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual  4.2.2.3 NuMicro NUC472Jxxxx LQFP 144-pin EBI_AD13/EMAC_MII_RXERR/TM3_CNT_OUT/UART4_TXD/SC1_CLK/I2S1_BCLK/PC.1 EBI_AD12/EMAC_MII_RXDV/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2 LDO_CAP ECAP0_IC2/EBI_AD11/EMAC_MII_RXD1/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3 ECAP0_IC1/EBI_AD10/EMAC_MII_RXD0/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4 PC.11/UART2_TXD/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3 ECAP0_IC0/EBI_MCLK/EMAC_MII_RXCLK/QEI0_A/CLKO/PC.5 PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2 PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6 EBI_AD9/EMAC_MII_TXD0/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6 PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21 EBI_AD8/EMAC_MII_TXD1/SPI0_MOSI0/TM1_EXT/PC.7 EMAC_MII_TXEN/SPI0_CLK/TM0_EXT/PC.8 PD.12/SC3_CLK/I2C4_SDA EMAC_MII_RXD3/SD0_DAT3/SPI3_SS0/PF.2 PD.11/SC3_RST/TM3_CNT_OUT PD.10/SC3_DAT/I2C4_SCL EMAC_MII_RXD2/SD0_DAT2/SPI3_CLK/PF.3 PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3 EMAC_MII_COL0/SD0_DAT1/SPI3_MISO0/PF.4 EMAC_MII_CRS/SD0_DAT0/SPI3_MOSI0/PF.5 PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2 PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1 PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0 PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20 EMAC_MII_TXCLK/SD0_CDn/UART2_RXD/PF.6 EMAC_MII_TXD3/SD0_CMD/UART2_TXD/PF.7 PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19 NUC472 LQFP 144 EMAC_MII_TXD2/SD0_CLK/UART2_RTS/PF.8 PA.8/SC0_RST/SPI3_CLK/PWM1_2/EPWM0_4/EBI_A18...

  • Page 48: Figure 4.2-8 Numicro Nuc472Hxxxx Lqfp 176-Pin Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual  4.2.2.4 NuMicro NUC472Hxxxx LQFP 176-pin EBI_AD13/EMAC_MII_RXERR/TM3_CNT_OUT/UART4_TXD/SC1_CLK/I2S1_BCLK/PC.1 EBI_AD12/EMAC_MII_RXDV/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2 ECAP0_IC2/EBI_AD11/EMAC_MII_RXD1/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3 LDO_CAP ECAP0_IC1/EBI_AD10/EMAC_MII_RXD0/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4 PC.11/UART2_TXD/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3 ECAP0_IC0/EBI_MCLK/EMAC_MII_RXCLK/QEI0_A/CLKO/PC.5 PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2 EBI_AD9/EMAC_MII_TXD0/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6 PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6 EBI_AD8/EMAC_MII_TXD1/SPI0_MOSI0/TM1_EXT/PC.7 PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21 EMAC_MII_TXEN/SPI0_CLK/TM0_EXT/PC.8 PD.12/SC3_CLK/I2C4_SDA EMAC_MII_RXD3/SD0_DAT3/SPI3_SS0/PF.2 PD.11/SC3_RST/TM3_CNT_OUT EMAC_MII_RXD2/SD0_DAT2/SPI3_CLK/PF.3 PD.10/SC3_DAT/I2C4_SCL EMAC_MII_COL0/SD0_DAT1/SPI3_MISO0/PF.4 PI.10 EMAC_MII_CRS/SD0_DAT0/SPI3_MOSI0/PF.5 PI.9/I2C4_SCL PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3 PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2 EMAC_MII_TXCLK/SD0_CDn/UART2_RXD/PF.6 PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1 EMAC_MII_TXD3/SD0_CMD/UART2_TXD/PF.7 PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0 EMAC_MII_TXD2/SD0_CLK/UART2_RTS/PF.8 PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20 UART2_CTS/PH.2...

  • Page 49: Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual Pin Description 4.3.1 NuMicro NUC442 Package LQFP 64-pin Description MFP = Multi-function pin. Pin No. Pin Name Type MFP* Description PE.8 MFP0 General purpose digital I/O pin. ADC1_0 MPF1 ADC1 analog input. ADC0_8 MPF1 ADC0 analog input.
  • Page 50 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PE.11 MFP0 General purpose digital I/O pin. ADC1_3 MPF1 ADC1 analog input. ADC0_11 MPF1 ADC0 analog input. ACMP1_P2 MPF2 Analog comparator1 positive input pin. SPI0_MOSI1 MPF3 2nd SPI0 MOSI (Master Out, Slave In) pin.
  • Page 51 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_A8 MPF7 EBI address bus bit8. This pad is embedded with “Slew Rate Control” Slew capability. PD.5 MFP0 General purpose digital I/O pin. SC5_RST MPF1 SmartCard5 reset pin. UART3_TXD MPF2 Data transmitter output pin for UART3. CAP_VSYNC MPF5 Image capture interface VSYNC input pin.
  • Page 52 NuMicro NUC442/NUC472 Series Technical Reference Manual XT1_OUT MPF1 External 4~24 MHz (high-speed) crystal output pin. External reset input: active LOW, with an internal nRESET MFP0 pull-up. Set this pin low reset to initial state. PG.10 MFP0 General purpose digital I/O pin. ICE_CLK MPF1 Serial wired debugger clock pin...
  • Page 53 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PA.7 MFP0 General purpose digital I/O pin. SC0_CLK MPF2 SmartCard0 clock pin. SPI3_SS0 MPF3 General purpose digital I/O pin. PWM1_3 MPF4 PWM1_3 output/capture input. EPWM0_5 MPF5 PWM0_5 output/capture input.
  • Page 54 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM1_0 MPF4 PWM1_0 output/capture input. EPWM0_2 MPF5 PWM0_2 output/capture input. EBI_A20 MPF7 EBI address bus bit20. This pad is embedded with “Slew Rate Control” Slew capability. PA.11 MFP0 General purpose digital I/O pin. UART0_RTS MPF1 Request to Send output pin for UART0.
  • Page 55 NuMicro NUC442/NUC472 Series Technical Reference Manual UART0_TXD MPF1 Data transmitter output pin for UART0. SC3_CLK MPF3 SmartCard3 clock pin. PWM1_5 MPF4 PWM1_5 output/capture input. EBI_AD3 MPF7 EBI address/data bus bit 3. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 56 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI2_SS0 MPF2 General purpose digital I/O pin. USB1_D- MPF3 USB1 differential signal D+. EBI_AD4 MPF7 EBI address/data bus bit 4. This pad is embedded with “Slew Rate Control” Slew capability. PB.3 MFP0 General purpose digital I/O pin. UART1_TXD MPF1 Data transmitter output pin for UART1.
  • Page 57 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI2_MISO1 MPF2 2nd SPI2 MISO (Master In, Slave Out) pin. CAN0_RXD MPF3 CAN bus receiver0 input. EBI_AD14 MPF7 EBI address/data bus bit 1. This pad is embedded with “Slew Rate Control” Slew capability. PB.13 MFP0 General purpose digital I/O pin.
  • Page 58 NuMicro NUC442/NUC472 Series Technical Reference Manual PC.2 MFP0 General purpose digital I/O pin. I2S1_LRCK MPF1 I2S1 left right channel clock. SC1_PWR MPF2 SmartCard1 power pin. UART4_RTS MPF3 Request to Send output pin for UART4. SPI0_SS0 MPF4 General purpose digital I/O pin. EBI_AD12 MPF7 EBI address/data bus bit 12.
  • Page 59 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI0_MISO0 MPF4 1st SPI0 MISO (Master In, Slave Out) pin. TM2_CNT_OUT MPF5 Timer2 event counter input/toggle output. EBI_AD9 MPF7 EBI address/data bus bit 9. This pad is embedded with “Slew Rate Control” Slew capability. PC.7 MFP0 General purpose digital I/O pin.
  • Page 60 NuMicro NUC442/NUC472 Series Technical Reference Manual PE.6 MFP0 General purpose digital I/O pin. ADC0_6 MPF1 ADC0 analog input. ACMP0_P0 MPF2 Analog comparator0 positive input pin. SPI0_MISO0 MPF3 1st SPI0 MISO (Master In, Slave Out) pin. SD0_CMD MPF4 SD mode #0 – command/response EBI_nWR MPF7 EBI write enable output pin.

  • Page 61: Numicro Nuc442 Package Lqfp 100-Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.3.2 NuMicro NUC442 Package LQFP 100-pin Description MFP = Multi-function pin. Pin No. Pin Name Type MFP* Description PE.12 MFP0 General purpose digital I/O pin. ADC1_4 MPF1 ADC1 analog input. ACMP1_P3 MPF2 Analog comparator1 positive input pin. ACMP2_P2 MPF3 Analog comparator2 positive input pin.
  • Page 62 NuMicro NUC442/NUC472 Series Technical Reference Manual SC4_CD MPF2 SmartCard4 card detect pin. SD1_CDn MPF4 SD mode #1 – card detect CAP_DATA7 MPF5 Image data input bus bit 7. EBI_A0 MPF7 EBI address bus bit0. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 63 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PD.0 MFP0 General purpose digital I/O pin. SPI1_MISO0 MPF1 1st SPI1 MISO (Master In, Slave Out) pin. SC4_CLK MPF2 SmartCard4 clock pin. SD1_DAT2 MPF4 SD mode #1 data line bit 2.
  • Page 64 NuMicro NUC442/NUC472 Series Technical Reference Manual SC5_CD MPF1 SmartCard5 card detect pin. UART3_RXD MPF2 Data receiver input pin for UART3. ACMP1_O MPF3 Analog ccomparator1 output. CAP_SCLK MPF5 Image capture interface sensor clock pin. EBI_A8 MPF7 EBI address bus bit8. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 65 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PG.13 MFP0 General purpose digital I/O pin. XT1_IN MPF1 External 4~24 MHz (high-speed) crystal input pin. PG.12 MFP0 General purpose digital I/O pin. XT1_OUT MPF1 External 4~24 MHz (high-speed) crystal output pin.
  • Page 66 NuMicro NUC442/NUC472 Series Technical Reference Manual PA.1 MFP0 General purpose digital I/O pin. TAMPER1 MPF1 Tamper detect pin 1. SC5_CD MPF2 SmartCard5 card detect pin. CAN1_TXD MPF3 CAN bus transmitter1 input. EBI_A22 MPF7 EBI address bus bit22. PA.2 MFP0 General purpose digital I/O pin. SC2_DAT MPF1 SmartCard2 data pin.
  • Page 67 NuMicro NUC442/NUC472 Series Technical Reference Manual ECAP1_IC2 MPF8 Input 2 of enhanced capture unit 1. This pad is embedded with “Slew Rate Control” Slew capability. PA.5 MFP0 General purpose digital I/O pin. SC2_RST MPF1 SmartCard2 reset pin. SPI3_SS0 MPF2 General purpose digital I/O pin. I2S0_BCLK MPF3 I2S0 bit clock pin.
  • Page 68 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PA.8 MFP0 General purpose digital I/O pin. SC0_RST MPF2 SmartCard0 reset pin. SPI3_CLK MPF3 SPI3 serial clock pin. PWM1_2 MPF4 PWM1_2 output/capture input. EPWM0_4 MPF5 PWM0_4 output/capture input.
  • Page 69 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM0_5 MPF4 PWM0_5 output/capture input. EPWM0_1 MPF5 PWM0_1 output/capture input. EBI_AD0 MPF7 EBI address/data bus bit 0. This pad is embedded with “Slew Rate Control” Slew capability. PA.12 MFP0 General purpose digital I/O pin. UART0_CTS MPF1 Clear to Send input pin for UART0.
  • Page 70 NuMicro NUC442/NUC472 Series Technical Reference Manual UART2_RTS MPF2 Request to Send output pin for UART2. I2C0_SCL MPF4 I2C0 clock pin. EBI_A21 MPF7 EBI address bus bit21. This pad is embedded with “Slew Rate Control” Slew capability. PC.9 MFP0 General purpose digital I/O pin. STADC MPF1 ADC analog input.
  • Page 71 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_AD3 MPF7 EBI address/data bus bit 3. This pad is embedded with “Slew Rate Control” Slew capability. LDO_CAP MFP0 LDO output pin. MFP0 Ground pin for digital circuit. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital circuit.
  • Page 72 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.3 MFP0 General purpose digital I/O pin. UART1_TXD MPF1 Data transmitter output pin for UART1. SPI2_CLK MPF2 SPI2 serial clock pin. USB1_D+ MPF3 USB1 differential signal D+. EBI_AD5 MPF7 EBI address/data bus bit 5.
  • Page 73 NuMicro NUC442/NUC472 Series Technical Reference Manual EPWM1_0 MPF5 PWM1_0 output/capture input. EBI_AD8 MPF7 EBI address/data bus bit 8. This pad is embedded with “Slew Rate Control” Slew capability. PB.7 MFP0 General purpose digital I/O pin. I2C2_SDA MPF1 I2C2 data input/output pin. BRAKE00 MPF2 Brake input pin 0 of EPWMB.
  • Page 74 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.11 MFP0 General purpose digital I/O pin. UART5_RXD MPF1 Data receiver input pin for UART5. EPWM1_5 MPF5 PWM1_5 output/capture input. EBI_AD13 MPF7 EBI address/data bus bit 13. Slew This pad is embedded with “Slew Rate Control”...
  • Page 75 NuMicro NUC442/NUC472 Series Technical Reference Manual SC1_DAT MPF2 SmartCard1 data pin. BRAKE00 MPF4 Brake input pin 0 of EPWMB. This pad is embedded with “Slew Rate Control” Slew capability. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital circuit. PC.0 MFP0 General purpose digital I/O pin.
  • Page 76 NuMicro NUC442/NUC472 Series Technical Reference Manual PC.3 MFP0 General purpose digital I/O pin. I2S1_MCLK MPF1 I2S1 master clock output pin. SC1_CD MPF2 SmartCard1 card detect pin. UART4_CTS MPF3 Clear to Send input pin for UART4. SPI0_MISO1 MPF4 2nd SPI0 MISO (Master In, Slave Out) pin. QEI0_Z MPF5 Quadrature encoder phase Z input of QEI Unit 0.
  • Page 77 NuMicro NUC442/NUC472 Series Technical Reference Manual TM2_CNT_OUT MPF5 Timer2 event counter input/toggle output. EBI_AD9 MPF7 EBI address/data bus bit 9. This pad is embedded with “Slew Rate Control” Slew capability. PC.7 MFP0 General purpose digital I/O pin. TM1_EXT MPF1 Timer1 external counter input SPI0_MOSI0 MPF4 1st SPI0 MOSI (Master Out, Slave In) pin.
  • Page 78 NuMicro NUC442/NUC472 Series Technical Reference Manual PE.3 MFP0 General purpose digital I/O pin. ADC0_3 MPF1 ADC0 analog input. ACMP0_P3 MPF2 Analog comparator0 positive input pin. SPI0_MOSI0 MPF3 1st SPI0 MOSI (Master Out, Slave In) pin. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 79 NuMicro NUC442/NUC472 Series Technical Reference Manual ACMP0_N MPF2 Analog comparator0 negative input pin. SPI0_MOSI0 MPF3 1st SPI0 MOSI (Master Out, Slave In) pin. SD0_CLK MPF4 SD mode #0 – clock. EBI_nRD MPF7 EBI read enable output pin. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 80 NuMicro NUC442/NUC472 Series Technical Reference Manual ACMP1_P1 MPF2 Analog comparator1 positive input pin. SPI0_MISO1 MPF3 2nd SPI0 MISO (Master In, Slave Out) pin. SD0_DAT1 MPF4 SD mode #0 data line bit 1. EBI_nWRL MPF7 EBI write enable output pin. This pad is embedded with “Slew Rate Control” Slew capability.

  • Page 81: Numicro Nuc442 Package Lqfp 128-Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.3.3 NuMicro NUC442 Package LQFP 128-pin Description MFP = Multi-function pin. Pin No. Pin Name Type MFP* Description PE.12 MFP0 General purpose digital I/O pin. ADC1_4 MPF1 ADC1 analog input. ACMP1_P3 MPF2 Analog comparator1 positive input pin. ACMP2_P2 MPF3 Analog comparator2 positive input pin.
  • Page 82 NuMicro NUC442/NUC472 Series Technical Reference Manual PF.10 MFP0 General purpose digital I/O pin. OPA0_IN- MPF1 General purpose digital I/O pin. PWM0_1 MPF4 PWM0_1 output/capture input. This pad is embedded with “Slew Rate Control” Slew capability. PF.11 MFP0 General purpose digital I/O pin. OPA0_O MPF1 Operational amplifier output pin...
  • Page 83 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI1_MOSI1 MPF1 2nd SPI1 MOSI (Master Out, Slave In) pin. SC4_RST MPF2 SmartCard4 reset pin. SD1_CMD MPF4 SD mode #1 – command/response CAP_DATA6 MPF5 Image data input bus bit 7. EBI_A1 MPF7 EBI address bus bit1. This pad is embedded with “Slew Rate Control”...
  • Page 84 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_A4 MPF7 EBI address bus bit4. INT3 MPF8 External interrupt3 input pin. This pad is embedded with “Slew Rate Control” Slew capability. PD.1 MFP0 General purpose digital I/O pin. SPI1_CLK MPF1 SPI1 serial clock pin. TM0_CNT_OUT MPF3 Timer0 event counter inpu/toggle output.
  • Page 85 NuMicro NUC442/NUC472 Series Technical Reference Manual PD.4 MFP0 General purpose digital I/O pin. SC5_CD MPF1 SmartCard5 card detect pin. UART3_RXD MPF2 Data receiver input pin for UART3. ACMP1_O MPF3 Analog ccomparator1 output . CAP_SCLK MPF5 Image capture interface sensor clock pin. EBI_A8 MPF7 EBI address bus bit8.
  • Page 86 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PG.13 MFP0 General purpose digital I/O pin. XT1_IN MPF1 External 4~24 MHz (high-speed) crystal input pin. PG.12 MFP0 General purpose digital I/O pin. XT1_OUT MPF1 External 4~24 MHz (high-speed) crystal output pin.
  • Page 87 NuMicro NUC442/NUC472 Series Technical Reference Manual PA.1 MFP0 General purpose digital I/O pin. TAMPER1 MPF1 Tamper detect pin 1. SC5_CD MPF2 SmartCard5 card detect pin. CAN1_TXD MPF3 CAN bus transmitter1 input. EBI_A22 MPF7 EBI address bus bit22. PD.8 MFP0 General purpose digital I/O pin. SPI3_MISO1 MPF1 2nd SPI3 MISO (Master In, Slave Out) pin.
  • Page 88 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_A13 MPF7 EBI address bus bit13. This pad is embedded with “Slew Rate Control” Slew capability. PA.4 MFP0 General purpose digital I/O pin. SC2_PWR MPF1 SmartCard2 power pin. SPI3_CLK MPF2 SPI3 serial clock pin. I2S0_DI MPF3 I2S0 data input.
  • Page 89 NuMicro NUC442/NUC472 Series Technical Reference Manual ECAP1_IC0 MPF8 Input 0 of enhanced capture unit 1. This pad is embedded with “Slew Rate Control” Slew capability. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital circuit. MFP0 Ground pin for digital circuit.
  • Page 90 NuMicro NUC442/NUC472 Series Technical Reference Manual PA.10 MFP0 General purpose digital I/O pin. SC0_DAT MPF2 SmartCard0 data pin. SPI3_MOSI0 MPF3 1st SPI3 MOSI (Master Out, Slave In) pin. PWM1_0 MPF4 PWM1_0 output/capture input. EPWM0_2 MPF5 PWM0_2 output/capture input. EBI_A20 MPF7 EBI address bus bit20.
  • Page 91 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PA.14 MFP0 General purpose digital I/O pin. UART0_TXD MPF1 Data transmitter output pin for UART0. SC3_CLK MPF3 SmartCard3 clock pin. PWM1_5 MPF4 PWM1_5 output/capture input. EBI_AD3 MPF7 EBI address/data bus bit 3.
  • Page 92 NuMicro NUC442/NUC472 Series Technical Reference Manual I2C0_SDA MPF4 I2C0 data input/output pin. CAP_DATA1 MPF5 Image data input bus bit 7. I2C3_SCL MPF6 I2C3 clock pin. EBI_A22 MPF7 EBI address bus bit22. SD1_DAT0 MPF8 SD mode #1 data line bit 0. EBI_A6 MPF9 EBI address bus bit6.
  • Page 93 NuMicro NUC442/NUC472 Series Technical Reference Manual UART5_CTS MPF2 Clear to Send input pin for UART5. ECAP0_IC2 MPF3 Input 2 of enhanced capture unit 0. This pad is embedded with “Slew Rate Control” Slew capability. PD.14 MFP0 General purpose digital I/O pin. SPI1_CLK MPF1 SPI1 serial clock pin.
  • Page 94 NuMicro NUC442/NUC472 Series Technical Reference Manual USB0_OTG_ID MFP0 USB0OTG ID pin. PB.0 MFP0 General purpose digital I/O pin. USB0_VBUS_ST MPF1 USB0 external VBUS regulator status I2C4_SCL MPF2 I2C4 clock pin. INT1 MPF8 External interrupt1 input pin. PB.1 MFP0 General purpose digital I/O pin. USB0_VBUS_EN MPF1 USB0 external VBUS regulator enable...
  • Page 95 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI2_MISO0 MPF2 1st SPI2 MISO (Master In, Slave Out) pin. UART4_RXD MPF3 Data receiver input pin for UART4. TM0_CNT_OUT MPF4 Timer0 event counter input/toggle output. EBI_AD6 MPF7 EBI address/data bus bit 6. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 96 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.8 MFP0 General purpose digital I/O pin. UART5_CTS MPF1 Clear to Send input pin for UART5. EPWM1_2 MPF5 PWM1_2 output/capture input. EBI_AD10 MPF7 EBI address/data bus bit 1. Slew This pad is embedded with “Slew Rate Control”...
  • Page 97 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_AD14 MPF7 EBI address/data bus bit 14. This pad is embedded with “Slew Rate Control” Slew capability. PB.13 MFP0 General purpose digital I/O pin. UART4_CTS MPF1 Clear to Send input pin for UART4. SPI2_MOSI1 MPF2 2nd SPI2 MOSI (Master Out, Slave In) pin.
  • Page 98 NuMicro NUC442/NUC472 Series Technical Reference Manual INT2 MPF8 External interrupt2 input pin. This pad is embedded with “Slew Rate Control” Slew capability. PC.1 MFP0 General purpose digital I/O pin. I2S1_BCLK MPF1 I2S1 bit clock pin. SC1_CLK MPF2 SmartCard1 clock pin. UART4_TXD MPF3 Data transmitter output pin for UART4.
  • Page 99 NuMicro NUC442/NUC472 Series Technical Reference Manual PC.4 MFP0 General purpose digital I/O pin. I2S1_DO MPF1 I2S1 data output. SC1_RST MPF2 SmartCard1 reset pin. SPI0_MOSI1 MPF4 2nd SPI0 MOSI (Master Out, Slave In) pin. QEI0_B MPF5 Quadrature encoder phase B input of QEI Unit 0. EBI_AD10 MPF7 EBI address/data bus bit 10.
  • Page 100 NuMicro NUC442/NUC472 Series Technical Reference Manual PC.8 MFP0 General purpose digital I/O pin. TM0_EXT MPF1 Timer0 external counter input SPI0_CLK MPF4 SPI0 serial clock pin. This pad is embedded with “Slew Rate Control” Slew capability. PF.2 MFP0 General purpose digital I/O pin. SPI3_SS0 MPF1 General purpose digital I/O pin.
  • Page 101 NuMicro NUC442/NUC472 Series Technical Reference Manual UART2_TXD MPF1 Data transmitter output pin for UART2. SD0_CMD MPF4 SD mode #0 – command/response This pad is embedded with “Slew Rate Control” Slew capability. PF.8 MFP0 General purpose digital I/O pin. UART2_RTS MPF1 Request to Send output pin for UART2.
  • Page 102 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PE.4 MFP0 General purpose digital I/O pin. ADC0_4 MPF1 ADC0 analog input. ACMP0_P2 MPF2 Analog comparator0 positive input pin. SPI0_SS0 MPF3 General purpose digital I/O pin. Slew This pad is embedded with “Slew Rate Control”...
  • Page 103 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. AVSS MFP0 Ground pin for digital circuit. Vref MFP0 Voltage reference input for ADC. AVDD MFP0 Power supply for internal analog circuit. PE.8 MFP0 General purpose digital I/O pin.
  • Page 104 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PE.11 MFP0 General purpose digital I/O pin. ADC1_3 MPF1 ADC1 analog input. ADC0_11 MPF1 ADC0 analog input. ACMP1_P2 MPF2 Analog comparator1 positive input pin. SPI0_MOSI1 MPF3 2nd SPI0 MOSI (Master Out, Slave In) pin.

  • Page 105: Numicro Nuc442 Package Lqfp 144-Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.3.4 NuMicro NUC442 Package LQFP 144-pin Description MFP = Multi-function pin. Pin No. Pin Name Type MFP* Description PE.12 MFP0 General purpose digital I/O pin. ADC1_4 MPF1 ADC1 analog input. ACMP1_P3 MPF2 Analog comparator1 positive input pin. ACMP2_P2 MPF3 Analog comparator2 positive input pin.
  • Page 106 NuMicro NUC442/NUC472 Series Technical Reference Manual PF.10 MFP0 General purpose digital I/O pin. OPA0_IN- MPF1 General purpose digital I/O pin. PWM0_1 MPF4 PWM0_1 output/capture input. This pad is embedded with “Slew Rate Control” Slew capability. PF.11 MFP0 General purpose digital I/O pin. OPA0_O MPF1 Operational amplifier output pin...
  • Page 107 NuMicro NUC442/NUC472 Series Technical Reference Manual UART0_TXD MPF1 Data transmitter output pin for UART0. PC.12 MFP0 General purpose digital I/O pin. SPI1_SS0 MPF1 1st SPI1 slave select pin.. SC4_CD MPF2 SmartCard4 card detect pin. SD1_CDn MPF4 SD mode #1 – card detect CAP_DATA7 MPF5 Image data input bus bit 7.
  • Page 108 NuMicro NUC442/NUC472 Series Technical Reference Manual SD1_DAT3 MPF4 SD mode #1 data line bit 3; CAP_DATA4 MPF5 Image data input bus bit 7. EBI_A3 MPF7 EBI address bus bit3. This pad is embedded with “Slew Rate Control” Slew capability. PD.0 MFP0 General purpose digital I/O pin.
  • Page 109 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PD.3 MFP0 General purpose digital I/O pin. SC5_CLK MPF1 SmartCard5 clock pin. I2C3_SDA MPF2 I2C3 data input/output pin. ACMP2_O MPF3 Analog ccomparator2 output . SD0_CDn MPF4 SD mode #0 –...
  • Page 110 NuMicro NUC442/NUC472 Series Technical Reference Manual SD0_CMD MPF4 SD mode #0 – command/response CAP_HSYNC MPF5 Image capture interface HSYNC input pin. EBI_A10 MPF7 EBI address bus bit10. This pad is embedded with “Slew Rate Control” Slew capability. PD.7 MFP0 General purpose digital I/O pin. SC5_DAT MPF1 SmartCard5 data pin.
  • Page 111 NuMicro NUC442/NUC472 Series Technical Reference Manual I2C1_SCL MPF3 I2C1 clock pin. PG.14 MFP0 General purpose digital I/O pin. X32K_OUT MPF1 External 32.768 kHz (low-speed) crystal output pin. I2C1_SDA MPF3 I2C1 data input/output pin. VBAT MFP0 Battery power input pin. PA.0 MFP0 General purpose digital I/O pin.
  • Page 112 NuMicro NUC442/NUC472 Series Technical Reference Manual I2S0_MCLK MPF3 I2S0 master clock output pin. BRAKE11 MPF4 Brake input pin 1 of EPWMA. CAP_SFIELD MPF5 Video input interface SFIELD input pin. EBI_A12 MPF7 EBI address bus bit12. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 113 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_A15 MPF7 EBI address bus bit15. ECAP1_IC1 MPF8 Input 1 of enhanced capture unit 1. This pad is embedded with “Slew Rate Control” Slew capability. PA.6 MFP0 General purpose digital I/O pin. SC2_CD MPF1 SmartCard2 card detect pin.
  • Page 114 NuMicro NUC442/NUC472 Series Technical Reference Manual Power supply for I/O ports and LDO source for MFP0 internal PLL and digital circuit. MFP0 Ground pin for digital circuit. PA.7 MFP0 General purpose digital I/O pin. SC0_CLK MPF2 SmartCard0 clock pin. SPI3_SS0 MPF3 General purpose digital I/O pin.
  • Page 115 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI3_MOSI0 MPF3 1st SPI3 MOSI (Master Out, Slave In) pin. PWM1_0 MPF4 PWM1_0 output/capture input. EPWM0_2 MPF5 PWM0_2 output/capture input. EBI_A20 MPF7 EBI address bus bit20. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 116 NuMicro NUC442/NUC472 Series Technical Reference Manual PA.14 MFP0 General purpose digital I/O pin. UART0_TXD MPF1 Data transmitter output pin for UART0. SC3_CLK MPF3 SmartCard3 clock pin. PWM1_5 MPF4 PWM1_5 output/capture input. EBI_AD3 MPF7 EBI address/data bus bit 3. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 117 NuMicro NUC442/NUC472 Series Technical Reference Manual CAP_DATA1 MPF5 Image data input bus bit 7. I2C3_SCL MPF6 I2C3 clock pin. EBI_A22 MPF7 EBI address bus bit22. SD1_DAT0 MPF8 SD mode #1 data line bit 0. EBI_A6 MPF9 EBI address bus bit6. This pad is embedded with “Slew Rate Control”...
  • Page 118 NuMicro NUC442/NUC472 Series Technical Reference Manual ECAP0_IC2 MPF3 Input 2 of enhanced capture unit 0. This pad is embedded with “Slew Rate Control” Slew capability. PD.14 MFP0 General purpose digital I/O pin. SPI1_CLK MPF1 SPI1 serial clock pin. UART5_RTS MPF2 Request to Send output pin for UART5.
  • Page 119 NuMicro NUC442/NUC472 Series Technical Reference Manual PB.0 MFP0 General purpose digital I/O pin. USB0_VBUS_ST MPF1 USB0 external VBUS regulator status I2C4_SCL MPF2 I2C4 clock pin. INT1 MPF8 External interrupt1 input pin. PB.1 MFP0 General purpose digital I/O pin. USB0_VBUS_EN MPF1 USB0 external VBUS regulator enabled I2C4_SDA MPF2...
  • Page 120 NuMicro NUC442/NUC472 Series Technical Reference Manual PB.2 MFP0 General purpose digital I/O pin. UART1_RXD MPF1 Data receiver input pin for UART1. SPI2_SS0 MPF2 General purpose digital I/O pin. USB1_D- MPF3 USB1 differential signal D+. EBI_AD4 MPF7 EBI address/data bus bit 4. This pad is embedded with “Slew Rate Control”...
  • Page 121 NuMicro NUC442/NUC472 Series Technical Reference Manual PB.6 MFP0 General purpose digital I/O pin. I2C2_SCL MPF1 I2C2 clock pin. BRAKE01 MPF2 Brake input pin 1 of EPWMB. UART4_RTS MPF3 Request to Send output pin for UART4. PWM1_4 MPF4 PWM1_4 output/capture input. EPWM1_0 MPF5 PWM1_0 output/capture input.
  • Page 122 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.10 MFP0 General purpose digital I/O pin. UART5_TXD MPF1 Data transmitter output pin for UART5. EPWM1_4 MPF5 PWM1_4 output/capture input. EBI_AD12 MPF7 EBI address/data bus bit 12. Slew This pad is embedded with “Slew Rate Control”...
  • Page 123 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.13 MFP0 General purpose digital I/O pin. UART4_CTS MPF1 Clear to Send input pin for UART4. SPI2_MOSI1 MPF2 2nd SPI2 MOSI (Master Out, Slave In) pin. CAN0_TXD MPF3 CAN bus transmitter0 input.
  • Page 124 NuMicro NUC442/NUC472 Series Technical Reference Manual INT2 MPF8 External interrupt2 input pin. This pad is embedded with “Slew Rate Control” Slew capability. PC.1 MFP0 General purpose digital I/O pin. I2S1_BCLK MPF1 I2S1 bit clock pin. SC1_CLK MPF2 SmartCard1 clock pin. UART4_TXD MPF3 Data transmitter output pin for UART4.
  • Page 125 NuMicro NUC442/NUC472 Series Technical Reference Manual PC.4 MFP0 General purpose digital I/O pin. I2S1_DO MPF1 I2S1 data output. SC1_RST MPF2 SmartCard1 reset pin. SPI0_MOSI1 MPF4 2nd SPI0 MOSI (Master Out, Slave In) pin. QEI0_B MPF5 Quadrature encoder phase B input of QEI Unit 0. EBI_AD10 MPF7 EBI address/data bus bit 10.
  • Page 126 NuMicro NUC442/NUC472 Series Technical Reference Manual PC.8 MFP0 General purpose digital I/O pin. TM0_EXT MPF1 Timer0 external counter input SPI0_CLK MPF4 SPI0 serial clock pin. This pad is embedded with “Slew Rate Control” Slew capability. PF.2 MFP0 General purpose digital I/O pin. SPI3_SS0 MPF1 General purpose digital I/O pin.
  • Page 127 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PF.7 MFP0 General purpose digital I/O pin. UART2_TXD MPF1 Data transmitter output pin for UART2. SD0_CMD MPF4 SD mode #0 – command/response Slew This pad is embedded with “Slew Rate Control” capability.
  • Page 128 NuMicro NUC442/NUC472 Series Technical Reference Manual PE.3 MFP0 General purpose digital I/O pin. ADC0_3 MPF1 ADC0 analog input. ACMP0_P3 MPF2 Analog comparator0 positive input pin. SPI0_MOSI0 MPF3 1st SPI0 MOSI (Master Out, Slave In) pin. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 129 NuMicro NUC442/NUC472 Series Technical Reference Manual ACMP0_N MPF2 Analog comparator0 negative input pin. SPI0_MOSI0 MPF3 1st SPI0 MOSI (Master Out, Slave In) pin. SD0_CLK MPF4 SD mode #0– clock. EBI_nRD MPF7 EBI read enable output pin. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 130 NuMicro NUC442/NUC472 Series Technical Reference Manual ACMP1_P1 MPF2 Analog comparator1 positive input pin. SPI0_MISO1 MPF3 2nd SPI0 MISO (Master In, Slave Out) pin. SD0_DAT1 MPF4 SD mode #0 data line bit 1. EBI_nWRL MPF7 EBI write enable output pin. This pad is embedded with “Slew Rate Control” Slew capability.

  • Page 131: Numicro Nuc472 Package Lqfp 100-Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.3.5 NuMicro NUC472 Package LQFP 100-pin Description MFP = Multi-function pin. Pin No. Pin Name Type MFP* Description PE.12 MFP0 General purpose digital I/O pin. ADC1_4 MPF1 ADC1 analog input. ACMP1_P3 MPF2 Analog comparator1 positive input pin. ACMP2_P2 MPF3 Analog comparator2 positive input pin.
  • Page 132 NuMicro NUC442/NUC472 Series Technical Reference Manual SC4_CD MPF2 SmartCard4 card detect pin. SD1_CDn MPF4 SD mode #1 – card detect CAP_DATA7 MPF5 Image data input bus bit 7. EBI_A0 MPF7 EBI address bus bit0. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 133 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PD.0 MFP0 General purpose digital I/O pin. SPI1_MISO0 MPF1 1st SPI1 MISO (Master In, Slave Out) pin. SC4_CLK MPF2 SmartCard4 clock pin. SD1_DAT2 MPF4 SD mode #1 data line bit 2.
  • Page 134 NuMicro NUC442/NUC472 Series Technical Reference Manual SC5_CD MPF1 SmartCard5 card detect pin. UART3_RXD MPF2 Data receiver input pin for UART3. ACMP1_O MPF3 Analog ccomparator1 output. CAP_SCLK MPF5 Image capture interface sensor clock pin. EBI_A8 MPF7 EBI address bus bit8. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 135 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PG.13 MFP0 General purpose digital I/O pin. XT1_IN MPF1 External 4~24 MHz (high-speed) crystal input pin. PG.12 MFP0 General purpose digital I/O pin. XT1_OUT MPF1 External 4~24 MHz (high-speed) crystal output pin.
  • Page 136 NuMicro NUC442/NUC472 Series Technical Reference Manual PA.1 MFP0 General purpose digital I/O pin. TAMPER1 MPF1 Tamper detect pin 1. SC5_CD MPF2 SmartCard5 card detect pin. CAN1_TXD MPF3 CAN bus transmitter1 input. EBI_A22 MPF7 EBI address bus bit22. PA.2 MFP0 General purpose digital I/O pin. SC2_DAT MPF1 SmartCard2 data pin.
  • Page 137 NuMicro NUC442/NUC472 Series Technical Reference Manual ECAP1_IC2 MPF8 Input 2 of enhanced capture unit 1. This pad is embedded with “Slew Rate Control” Slew capability. PA.5 MFP0 General purpose digital I/O pin. SC2_RST MPF1 SmartCard2 reset pin. SPI3_SS0 MPF2 General purpose digital I/O pin. I2S0_BCLK MPF3 I2S0 bit clock pin.
  • Page 138 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PA.8 MFP0 General purpose digital I/O pin. SC0_RST MPF2 SmartCard0 reset pin. SPI3_CLK MPF3 SPI3 serial clock pin. PWM1_2 MPF4 PWM1_2 output/capture input. EPWM0_4 MPF5 PWM0_4 output/capture input.
  • Page 139 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM0_5 MPF4 PWM0_5 output/capture input. EPWM0_1 MPF5 PWM0_1 output/capture input. EBI_AD0 MPF7 EBI address/data bus bit 0. This pad is embedded with “Slew Rate Control” Slew capability. PA.12 MFP0 General purpose digital I/O pin. UART0_CTS MPF1 Clear to Send input pin for UART0.
  • Page 140 NuMicro NUC442/NUC472 Series Technical Reference Manual UART2_RTS MPF2 Request to Send output pin for UART2. I2C0_SCL MPF4 I2C0 clock pin. EBI_A21 MPF7 EBI address bus bit21. This pad is embedded with “Slew Rate Control” Slew capability. PC.9 MFP0 General purpose digital I/O pin. STADC MPF1 ADC analog input.
  • Page 141 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_AD3 MPF7 EBI address/data bus bit 3. This pad is embedded with “Slew Rate Control” Slew capability. LDO_CAP MFP0 LDO output pin. MFP0 Ground pin for digital circuit. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital circuit.
  • Page 142 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.3 MFP0 General purpose digital I/O pin. UART1_TXD MPF1 Data transmitter output pin for UART1. SPI2_CLK MPF2 SPI2 serial clock pin. USB1_D+ MPF3 USB1 differential signal D+. EBI_AD5 MPF7 EBI address/data bus bit 5.
  • Page 143 NuMicro NUC442/NUC472 Series Technical Reference Manual EPWM1_0 MPF5 PWM1_0 output/capture input. EBI_AD8 MPF7 EBI address/data bus bit 8. This pad is embedded with “Slew Rate Control” Slew capability. PB.7 MFP0 General purpose digital I/O pin. I2C2_SDA MPF1 I2C2 data input/output pin. BRAKE00 MPF2 Brake input pin 0 of EPWMB.
  • Page 144 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.11 MFP0 General purpose digital I/O pin. UART5_RXD MPF1 Data receiver input pin for UART5. EPWM1_5 MPF5 PWM1_5 output/capture input. EBI_AD13 MPF7 EBI address/data bus bit 13. Slew This pad is embedded with “Slew Rate Control”...
  • Page 145 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.15 MFP0 General purpose digital I/O pin. I2S1_DO MPF1 I2S1 data output. SC1_DAT MPF2 SmartCard1 data pin. BRAKE00 MPF4 Brake input pin 0 of EPWMB. EMAC_MII_MDIO MPF6 MII/RMII Management Data I/O.
  • Page 146 NuMicro NUC442/NUC472 Series Technical Reference Manual I2S1_LRCK MPF1 I2S1 left right channel clock. SC1_PWR MPF2 SmartCard1 power pin. UART4_RTS MPF3 Request to Send output pin for UART4. SPI0_SS0 MPF4 General purpose digital I/O pin. EMAC_MII_RXDV MPF6 MII Receive Data Valid / RMII CRS_DV Input. EBI_AD12 MPF7 EBI address/data bus bit 12.
  • Page 147 NuMicro NUC442/NUC472 Series Technical Reference Manual PC.5 MFP0 General purpose digital I/O pin. CLKO MFP1 Clock Output Pin. QEI0_A MPF5 Quadrature encoder phase A input of QEI Unit 0. EMAC_MII_RXCLK MPF6 MII Receive Clock Input. EBI_MCLK MPF7 EBI interface clock output pin. ECAP0_IC0 MPF8 Input 0 of enhanced capture unit 0.
  • Page 148 NuMicro NUC442/NUC472 Series Technical Reference Manual LDO_CAP MFP0 LDO output pin. MFP0 Ground pin for digital circuit. PE.0 MFP0 General purpose digital I/O pin. ADC0_0 MPF1 ADC0 analog input. INT4 MPF8 External interrupt4 input pin. PE.1 MFP0 General purpose digital I/O pin. ADC0_1 MPF1 ADC0 analog input.
  • Page 149 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI0_CLK MPF3 SPI0 serial clock pin. SD0_CDn MPF4 SD mode #0 – card detect This pad is embedded with “Slew Rate Control” Slew capability. PE.6 MFP0 General purpose digital I/O pin. ADC0_6 MPF1 ADC0 analog input. ACMP0_P0 MPF2 Analog comparator0 positive input pin.
  • Page 150 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_ALE MPF7 EBI address latch enable output pin. This pad is embedded with “Slew Rate Control” Slew capability. PE.9 MFP0 General purpose digital I/O pin. ADC1_1 MPF1 ADC1 analog input. ADC0_9 MPF1 ADC0 analog input. ACMP1_P0 MPF2 Analog comparator1 positive input pin.
  • Page 151 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. Note: Pin Type I = Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin May 23, 2014 Page 151 of 1386 Rev.1.05...

  • Page 152: Numicro Nuc472 Package Lqfp 128-Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.3.6 NuMicro NUC472 Package LQFP 128-pin Description MFP = Multi-function pin. Pin No. Pin Name Type MFP* Description PE.12 MFP0 General purpose digital I/O pin. ADC1_4 MPF1 ADC1 analog input. ACMP1_P3 MPF2 Analog comparator1 positive input pin. ACMP2_P2 MPF3 Analog comparator2 positive input pin.
  • Page 153 NuMicro NUC442/NUC472 Series Technical Reference Manual PF.10 MFP0 General purpose digital I/O pin. OPA0_IN- MPF1 General purpose digital I/O pin. PWM0_1 MPF4 PWM0_1 output/capture input. This pad is embedded with “Slew Rate Control” Slew capability. PF.11 MFP0 General purpose digital I/O pin. OPA0_O MPF1 Operational amplifier output pin...
  • Page 154 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI1_MOSI1 MPF1 2nd SPI1 MOSI (Master Out, Slave In) pin. SC4_RST MPF2 SmartCard4 reset pin. SD1_CMD MPF4 SD mode #1 – command/response CAP_DATA6 MPF5 Image data input bus bit 7. EBI_A1 MPF7 EBI address bus bit1. This pad is embedded with “Slew Rate Control”...
  • Page 155 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_A4 MPF7 EBI address bus bit4. INT3 MPF8 External interrupt3 input pin. This pad is embedded with “Slew Rate Control” Slew capability. PD.1 MFP0 General purpose digital I/O pin. SPI1_CLK MPF1 SPI1 serial clock pin. TM0_CNT_OUT MPF3 Timer0 event counter input/toggle output.
  • Page 156 NuMicro NUC442/NUC472 Series Technical Reference Manual PD.4 MFP0 General purpose digital I/O pin. SC5_CD MPF1 SmartCard5 card detect pin. UART3_RXD MPF2 Data receiver input pin for UART3. ACMP1_O MPF3 Analog ccomparator1 output . CAP_SCLK MPF5 Image capture interface sensor clock pin. EBI_A8 MPF7 EBI address bus bit8.
  • Page 157 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PG.13 MFP0 General purpose digital I/O pin. XT1_IN MPF1 External 4~24 MHz (high-speed) crystal input pin. PG.12 MFP0 General purpose digital I/O pin. XT1_OUT MPF1 External 4~24 MHz (high-speed) crystal output pin.
  • Page 158 NuMicro NUC442/NUC472 Series Technical Reference Manual PA.1 MFP0 General purpose digital I/O pin. TAMPER1 MPF1 Tamper detect pin 1. SC5_CD MPF2 SmartCard5 card detect pin. CAN1_TXD MPF3 CAN bus transmitter1 input. EBI_A22 MPF7 EBI address bus bit22. PD.8 MFP0 General purpose digital I/O pin. SPI3_MISO1 MPF1 2nd SPI3 MISO (Master In, Slave Out) pin.
  • Page 159 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_A13 MPF7 EBI address bus bit13. This pad is embedded with “Slew Rate Control” Slew capability. PA.4 MFP0 General purpose digital I/O pin. SC2_PWR MPF1 SmartCard2 power pin. SPI3_CLK MPF2 SPI3 serial clock pin. I2S0_DI MPF3 I2S0 data input.
  • Page 160 NuMicro NUC442/NUC472 Series Technical Reference Manual ECAP1_IC0 MPF8 Input 0 of enhanced capture unit 1. This pad is embedded with “Slew Rate Control” Slew capability. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital circuit. MFP0 Ground pin for digital circuit.
  • Page 161 NuMicro NUC442/NUC472 Series Technical Reference Manual PA.10 MFP0 General purpose digital I/O pin. SC0_DAT MPF2 SmartCard0 data pin. SPI3_MOSI0 MPF3 1st SPI3 MOSI (Master Out, Slave In) pin. PWM1_0 MPF4 PWM1_0 output/capture input. EPWM0_2 MPF5 PWM0_2 output/capture input. EBI_A20 MPF7 EBI address bus bit20.
  • Page 162 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PA.14 MFP0 General purpose digital I/O pin. UART0_TXD MPF1 Data transmitter output pin for UART0. SC3_CLK MPF3 SmartCard3 clock pin. PWM1_5 MPF4 PWM1_5 output/capture input. EBI_AD3 MPF7 EBI address/data bus bit 3.
  • Page 163 NuMicro NUC442/NUC472 Series Technical Reference Manual I2C0_SDA MPF4 I2C0 data input/output pin. CAP_DATA1 MPF5 Image data input bus bit 7. I2C3_SCL MPF6 I2C3 clock pin. EBI_A22 MPF7 EBI address bus bit22. SD1_DAT0 MPF8 SD mode #1 data line bit 0. EBI_A6 MPF9 EBI address bus bit6.
  • Page 164 NuMicro NUC442/NUC472 Series Technical Reference Manual UART5_CTS MPF2 Clear to Send input pin for UART5. ECAP0_IC2 MPF3 Input 2 of enhanced capture unit 0. This pad is embedded with “Slew Rate Control” Slew capability. PD.14 MFP0 General purpose digital I/O pin. SPI1_CLK MPF1 SPI1 serial clock pin.
  • Page 165 NuMicro NUC442/NUC472 Series Technical Reference Manual USB0_OTG_ID MFP0 USB0OTG ID pin. PB.0 MFP0 General purpose digital I/O pin. USB0_VBUS_ST MPF1 USB0 external VBUS regulator status I2C4_SCL MPF2 I2C4 clock pin. INT1 MPF8 External interrupt1 input pin. PB.1 MFP0 General purpose digital I/O pin. USB0_VBUS_EN MPF1 USB0 external VBUS regulator enable...
  • Page 166 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI2_MISO0 MPF2 1st SPI2 MISO (Master In, Slave Out) pin. UART4_RXD MPF3 Data receiver input pin for UART4. TM0_CNT_OUT MPF4 Timer0 event counter input/toggle output. EBI_AD6 MPF7 EBI address/data bus bit 6. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 167 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.8 MFP0 General purpose digital I/O pin. UART5_CTS MPF1 Clear to Send input pin for UART5. EPWM1_2 MPF5 PWM1_2 output/capture input. EBI_AD10 MPF7 EBI address/data bus bit 10. Slew This pad is embedded with “Slew Rate Control”...
  • Page 168 NuMicro NUC442/NUC472 Series Technical Reference Manual EMAC_MII_MDC MPF6 MII/RMII Management Data Clock. EBI_AD14 MPF7 EBI address/data bus bit 14. This pad is embedded with “Slew Rate Control” Slew capability. PB.13 MFP0 General purpose digital I/O pin. UART4_CTS MPF1 Clear to Send input pin for UART4. SPI2_MOSI1 MPF2 2nd SPI2 MOSI (Master Out, Slave In) pin.
  • Page 169 NuMicro NUC442/NUC472 Series Technical Reference Manual I2S1_DI MPF1 I2S1 data input. SC1_DAT MPF2 SmartCard1 data pin. UART4_RXD MPF3 Data receiver input pin for UART4. EMAC_REFCLK MPF6 EMAC RMII mode clock input EBI_MCLK MPF7 EBI interface clock output pin. INT2 MPF8 External interrupt2 input pin.
  • Page 170 NuMicro NUC442/NUC472 Series Technical Reference Manual UART4_CTS MPF3 Clear to Send input pin for UART4. SPI0_MISO1 MPF4 2nd SPI0 MISO (Master In, Slave Out) pin. QEI0_Z MPF5 Quadrature encoder phase Z input of QEI Unit 0. EMAC_MII_RXD1 MPF6 MII/RMII Receive Data Bus Bit 1. EBI_AD11 MPF7 EBI address/data bus bit 11.
  • Page 171 NuMicro NUC442/NUC472 Series Technical Reference Manual TM2_CNT_OUT MPF5 Timer2 event counter input/toggle output. EMAC_MII_TXD0 MPF6 MII/RMII Transmit Data Bus bit 0. EBI_AD9 MPF7 EBI address/data bus bit 9. This pad is embedded with “Slew Rate Control” Slew capability. PC.7 MFP0 General purpose digital I/O pin.
  • Page 172 NuMicro NUC442/NUC472 Series Technical Reference Manual PF.4 MFP0 General purpose digital I/O pin. SPI3_MISO0 MPF1 1st SPI3 MISO (Master In, Slave Out) pin. SD0_DAT1 MPF4 SD mode #0 data line bit 1. EMAC_MII_COL0 MPF6 MII Collision Detect Input Pin. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 173 NuMicro NUC442/NUC472 Series Technical Reference Manual LDO_CAP MFP0 LDO output pin. MFP0 Ground pin for digital circuit. Power supply for I/O ports and LDO source for MFP0 internal PLL and digital circuit. PE.0 MFP0 General purpose digital I/O pin. ADC0_0 MPF1 ADC0 analog input.
  • Page 174 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC0_5 MPF1 ADC0 analog input. ACMP0_P1 MPF2 Analog comparator0 positive input pin. SPI0_CLK MPF3 SPI0 serial clock pin. SD0_CDn MPF4 SD mode #0 – card detect This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 175 NuMicro NUC442/NUC472 Series Technical Reference Manual TM1_CNT_OUT MPF3 Timer1 event counter input/toggle output. SD0_DAT3 MPF4 SD mode #0 data line bit 3. EBI_ALE MPF7 EBI address latch enable output pin. This pad is embedded with “Slew Rate Control” Slew capability. PE.9 MFP0 General purpose digital I/O pin.
  • Page 176 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_nCS0 MPF7 EBI chip select 0 enable output pin. This pad is embedded with “Slew Rate Control” Slew capability. Note: Pin Type I = Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin May 23, 2014 Page 176 of 1386 Rev.1.05...

  • Page 177: Numicro Nuc472 Package Lqfp 144-Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.3.7 NuMicro NUC472 Package LQFP 144-pin Description MFP = Multi-function pin. Pin No. Pin Name Type MFP* Description PE.12 MFP0 General purpose digital I/O pin. ADC1_4 MPF1 ADC1 analog input. ACMP1_P3 MPF2 Analog comparator1 positive input pin. ACMP2_P2 MPF3 Analog comparator2 positive input pin.
  • Page 178 NuMicro NUC442/NUC472 Series Technical Reference Manual PF.10 MFP0 General purpose digital I/O pin. OPA0_IN- MPF1 General purpose digital I/O pin. PWM0_1 MPF4 PWM0_1 output/capture input. This pad is embedded with “Slew Rate Control” Slew capability. PF.11 MFP0 General purpose digital I/O pin. OPA0_O MPF1 Operational amplifier output pin...
  • Page 179 NuMicro NUC442/NUC472 Series Technical Reference Manual UART0_TXD MPF1 Data transmitter output pin for UART0. PC.12 MFP0 General purpose digital I/O pin. SPI1_SS0 MPF1 1st SPI1 slave select pin. SC4_CD MPF2 SmartCard4 card detect pin. SD1_CDn MPF4 SD mode #1 – card detect CAP_DATA7 MPF5 Image data input bus bit 7.
  • Page 180 NuMicro NUC442/NUC472 Series Technical Reference Manual SD1_DAT3 MPF4 SD mode #1 data line bit 3; CAP_DATA4 MPF5 Image data input bus bit 7. EBI_A3 MPF7 EBI address bus bit3. This pad is embedded with “Slew Rate Control” Slew capability. PD.0 MFP0 General purpose digital I/O pin.
  • Page 181 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PD.3 MFP0 General purpose digital I/O pin. SC5_CLK MPF1 SmartCard5 clock pin. I2C3_SDA MPF2 I2C3 data input/output pin. ACMP2_O MPF3 Analog ccomparator2 output . SD0_CDn MPF4 SD mode #0 –...
  • Page 182 NuMicro NUC442/NUC472 Series Technical Reference Manual SD0_CMD MPF4 SD mode #0 – command/response CAP_HSYNC MPF5 Image capture interface HSYNC input pin. EBI_A10 MPF7 EBI address bus bit10. This pad is embedded with “Slew Rate Control” Slew capability. PD.7 MFP0 General purpose digital I/O pin. SC5_DAT MPF1 SmartCard5 data pin.
  • Page 183 NuMicro NUC442/NUC472 Series Technical Reference Manual X32K_IN MPF1 External 32.768 kHz (low-speed) crystal input pin. I2C1_SCL MPF3 I2C1 clock pin. PG.14 MFP0 General purpose digital I/O pin. X32K_OUT MPF1 External 32.768 kHz (low-speed) crystal output pin. I2C1_SDA MPF3 I2C1 data input/output pin. VBAT MFP0 Battery power input pin.
  • Page 184 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI3_MISO0 MPF2 1st SPI3 MISO (Master In, Slave Out) pin. I2S0_MCLK MPF3 I2S0 master clock output pin. BRAKE11 MPF4 Brake input pin 1 of EPWMA. CAP_SFIELD MPF5 Video input interface SFIELD input pin. EBI_A12 MPF7 EBI address bus bit12.
  • Page 185 NuMicro NUC442/NUC472 Series Technical Reference Manual QEI1_B MPF5 Quadrature encoder phase B input of QEI Unit 1. EBI_A15 MPF7 EBI address bus bit15. ECAP1_IC1 MPF8 Input 1 of enhanced capture unit 1. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 186 NuMicro NUC442/NUC472 Series Technical Reference Manual SC1_CLK MPF3 SmartCard1 clock pin. Power supply for I/O ports and LDO source for MFP0 internal PLL and digital circuit. MFP0 Ground pin for digital circuit. PA.7 MFP0 General purpose digital I/O pin. SC0_CLK MPF2 SmartCard0 clock pin.
  • Page 187 NuMicro NUC442/NUC472 Series Technical Reference Manual SC0_DAT MPF2 SmartCard0 data pin. SPI3_MOSI0 MPF3 1st SPI3 MOSI (Master Out, Slave In) pin. PWM1_0 MPF4 PWM1_0 output/capture input. EPWM0_2 MPF5 PWM0_2 output/capture input. EBI_A20 MPF7 EBI address bus bit20. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 188 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PA.14 MFP0 General purpose digital I/O pin. UART0_TXD MPF1 Data transmitter output pin for UART0. SC3_CLK MPF3 SmartCard3 clock pin. PWM1_5 MPF4 PWM1_5 output/capture input. EBI_AD3 MPF7 EBI address/data bus bit 3.
  • Page 189 NuMicro NUC442/NUC472 Series Technical Reference Manual I2C0_SDA MPF4 I2C0 data input/output pin. CAP_DATA1 MPF5 Image data input bus bit 7. I2C3_SCL MPF6 I2C3 clock pin. EBI_A22 MPF7 EBI address bus bit22. SD1_DAT0 MPF8 SD mode #1 data line bit 0. EBI_A6 MPF9 EBI address bus bit6.
  • Page 190 NuMicro NUC442/NUC472 Series Technical Reference Manual UART5_CTS MPF2 Clear to Send input pin for UART5. ECAP0_IC2 MPF3 Input 2 of enhanced capture unit 0. This pad is embedded with “Slew Rate Control” Slew capability. PD.14 MFP0 General purpose digital I/O pin. SPI1_CLK MPF1 SPI1 serial clock pin.
  • Page 191 NuMicro NUC442/NUC472 Series Technical Reference Manual USB0_OTG_ID MFP0 USB0OTG ID pin. PB.0 MFP0 General purpose digital I/O pin. USB0_VBUS_ST MPF1 USB0 external VBUS regulator status I2C4_SCL MPF2 I2C4 clock pin. INT1 MPF8 External interrupt1 input pin. PB.1 MFP0 General purpose digital I/O pin. USB0_VBUS_EN MPF1 USB0 external VBUS regulator enabled...
  • Page 192 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.2 MFP0 General purpose digital I/O pin. UART1_RXD MPF1 Data receiver input pin for UART1. SPI2_SS0 MPF2 General purpose digital I/O pin. USB1_D- MPF3 USB1 differential signal D+.
  • Page 193 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PB.6 MFP0 General purpose digital I/O pin. I2C2_SCL MPF1 I2C2 clock pin. BRAKE01 MPF2 Brake input pin 1 of EPWMB. UART4_RTS MPF3 Request to Send output pin for UART4. PWM1_4 MPF4 PWM1_4 output/capture input.
  • Page 194 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_AD11 MPF7 EBI address/data bus bit 11. This pad is embedded with “Slew Rate Control” Slew capability. PB.10 MFP0 General purpose digital I/O pin. UART5_TXD MPF1 Data transmitter output pin for UART5. EPWM1_4 MPF5 PWM1_4 output/capture input.
  • Page 195 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_AD14 MPF7 EBI address/data bus bit 14. This pad is embedded with “Slew Rate Control” Slew capability. PB.13 MFP0 General purpose digital I/O pin. UART4_CTS MPF1 Clear to Send input pin for UART4. SPI2_MOSI1 MPF2 2nd SPI2 MOSI (Master Out, Slave In) pin.
  • Page 196 NuMicro NUC442/NUC472 Series Technical Reference Manual I2S1_DI MPF1 I2S1 data input. SC1_DAT MPF2 SmartCard1 data pin. UART4_RXD MPF3 Data receiver input pin for UART4. EMAC_REFCLK MPF6 EMAC RMII mode clock input EBI_MCLK MPF7 EBI interface clock output pin. INT2 MPF8 External interrupt2 input pin.
  • Page 197 NuMicro NUC442/NUC472 Series Technical Reference Manual UART4_CTS MPF3 Clear to Send input pin for UART4. SPI0_MISO1 MPF4 2nd SPI0 MISO (Master In, Slave Out) pin. QEI0_Z MPF5 Quadrature encoder phase Z input of QEI Unit 0. EMAC_MII_RXD1 MPF6 MII/RMII Receive Data Bus Bit 1. EBI_AD11 MPF7 EBI address/data bus bit 11.
  • Page 198 NuMicro NUC442/NUC472 Series Technical Reference Manual TM2_CNT_OUT MPF5 Timer2 event counter input/toggle output. EMAC_MII_TXD0 MPF6 MII/RMII Transmit Data Bus bit 0. EBI_AD9 MPF7 EBI address/data bus bit 9. This pad is embedded with “Slew Rate Control” Slew capability. PC.7 MFP0 General purpose digital I/O pin.
  • Page 199 NuMicro NUC442/NUC472 Series Technical Reference Manual PF.4 MFP0 General purpose digital I/O pin. SPI3_MISO0 MPF1 1st SPI3 MISO (Master In, Slave Out) pin. SD0_DAT1 MPF4 SD mode #0 data line bit 1. EMAC_MII_COL0 MPF6 MII Collision Detect Input Pin. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 200 NuMicro NUC442/NUC472 Series Technical Reference Manual EMAC_MII_TXD2 MPF6 MII Transmit Data Bus bit 2. This pad is embedded with “Slew Rate Control” Slew capability. PH.2 MFP0 General purpose digital I/O pin. UART2_CTS MPF1 Clear to Send input pin for UART2. LDO_CAP MFP0 LDO output pin.
  • Page 201 NuMicro NUC442/NUC472 Series Technical Reference Manual ACMP0_P2 MPF2 Analog comparator0 positive input pin. SPI0_SS0 MPF3 General purpose digital I/O pin. This pad is embedded with “Slew Rate Control” Slew capability. PE.5 MFP0 General purpose digital I/O pin. ADC0_5 MPF1 ADC0 analog input. ACMP0_P1 MPF2 Analog comparator0 positive input pin.
  • Page 202 NuMicro NUC442/NUC472 Series Technical Reference Manual AVDD MFP0 Power supply for internal analog circuit. PE.8 MFP0 General purpose digital I/O pin. ADC1_0 MPF1 ADC1 analog input. ADC0_8 MPF1 ADC0 analog input. ACMP1_N MPF2 Analog comparator1 negative input pin. TM1_CNT_OUT MPF3 Timer1 event counter input/toggle output.
  • Page 203 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC0_11 MPF1 ADC0 analog input. ACMP1_P2 MPF2 Analog comparator1 positive input pin. SPI0_MOSI1 MPF3 2nd SPI0 MOSI (Master Out, Slave In) pin. SD0_DAT0 MPF4 SD mode #0 data line bit 0. ACMP2_P3 MPF5 Analog comparator2 positive input pin. EBI_nCS0 MPF7 EBI chip select 0 enable output pin.

  • Page 204: Numicro Nuc472 Package Lqfp 176-Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.3.8 NuMicro NUC472 Package LQFP 176-pin Description MFP = Multi-function pin. Pin No. Pin Name Type MFP* Description PE.12 MFP0 General purpose digital I/O pin. ADC1_4 MPF1 ADC1 analog input. ACMP1_P3 MPF2 Analog comparator1 positive input pin. ACMP2_P2 MPF3 Analog comparator2 positive input pin.
  • Page 205 NuMicro NUC442/NUC472 Series Technical Reference Manual PF.10 MFP0 General purpose digital I/O pin. OPA0_IN- MPF1 General purpose digital I/O pin. PWM0_1 MPF4 PWM0_1 output/capture input. This pad is embedded with “Slew Rate Control” Slew capability. PF.11 MFP0 General purpose digital I/O pin. OPA0_O MPF1 Operational amplifier output pin...
  • Page 206 NuMicro NUC442/NUC472 Series Technical Reference Manual UART0_TXD MPF1 Data transmitter output pin for UART0. PC.12 MFP0 General purpose digital I/O pin. SPI1_SS0 MPF1 1st SPI1 slave select pin. SC4_CD MPF2 SmartCard4 card detect pin. SD1_CDn MPF4 SD mode #1 – card detect CAP_DATA7 MPF5 Image data input bus bit 7.
  • Page 207 NuMicro NUC442/NUC472 Series Technical Reference Manual SD1_DAT3 MPF4 SD mode #1 data line bit 3. CAP_DATA4 MPF5 Image data input bus bit 7. EBI_A3 MPF7 EBI address bus bit3. This pad is embedded with “Slew Rate Control” Slew capability. PD.0 MFP0 General purpose digital I/O pin.
  • Page 208 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. PH.11 MFP0 General purpose digital I/O pin. UART3_RXD MPF1 Data receiver input pin for UART3. PH.12 MFP0 General purpose digital I/O pin. UART3_TXD MPF1 Data transmitter output pin for UART3.
  • Page 209 NuMicro NUC442/NUC472 Series Technical Reference Manual UART3_TXD MPF2 Data transmitter output pin for UART3. CAP_VSYNC MPF5 Image capture interface VSYNC input pin. EBI_A9 MPF7 EBI address bus bit9. This pad is embedded with “Slew Rate Control” Slew capability. PD.6 MFP0 General purpose digital I/O pin.
  • Page 210 NuMicro NUC442/NUC472 Series Technical Reference Manual PG.13 MFP0 General purpose digital I/O pin. XT1_IN MPF1 External 4~24 MHz (high-speed) crystal input pin. PG.12 MFP0 General purpose digital I/O pin. XT1_OUT MPF1 External 4~24 MHz (high-speed) crystal output pin. External reset input: active LOW, with an internal nRESET MFP0 pull-up.
  • Page 211 NuMicro NUC442/NUC472 Series Technical Reference Manual SC5_CD MPF2 SmartCard5 card detect pin. CAN1_TXD MPF3 CAN bus transmitter1 input. EBI_A22 MPF7 EBI address bus bit22. PI.3 MFP0 General purpose digital I/O pin. SPI3_SS0 MPF1 General purpose digital I/O pin. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 212 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI3_MISO0 MPF2 1st SPI3 MISO (Master In, Slave Out) pin. I2S0_MCLK MPF3 I2S0 master clock output pin. BRAKE11 MPF4 Brake input pin 1 of EPWMA. CAP_SFIELD MPF5 Video input interface SFIELD input pin. EBI_A12 MPF7 EBI address bus bit12.
  • Page 213 NuMicro NUC442/NUC472 Series Technical Reference Manual QEI1_B MPF5 Quadrature encoder phase B input of QEI Unit 1. EBI_A15 MPF7 EBI address bus bit15. ECAP1_IC1 MPF8 Input 1 of enhanced capture unit 1. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 214 NuMicro NUC442/NUC472 Series Technical Reference Manual PG.4 MFP0 General purpose digital I/O pin. PS2_DAT MPF1 PS2 data pin. I2S1_DI MPF2 I2S1 data input. SC1_PWR MPF3 SmartCard1 power pin. PG.5 MFP0 General purpose digital I/O pin. I2S1_BCLK MPF2 I2S1 bit clock pin. SC1_DAT MPF3 SmartCard1 data pin.
  • Page 215 NuMicro NUC442/NUC472 Series Technical Reference Manual PA.9 MFP0 General purpose digital I/O pin. SC0_PWR MPF2 SmartCard0 power pin. SPI3_MISO0 MPF3 1st SPI3 MISO (Master In, Slave Out) pin. PWM1_1 MPF4 PWM1_1 output/capture input. EPWM0_3 MPF5 PWM0_3 output/capture input. EBI_A19 MPF7 EBI address bus bit19.
  • Page 216 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_AD1 MPF7 EBI address/data bus bit 1. This pad is embedded with “Slew Rate Control” Slew capability. PA.13 MFP0 General purpose digital I/O pin. UART0_RXD MPF1 Data receiver input pin for UART0. SC3_DAT MPF3 SmartCard3 data pin.
  • Page 217 NuMicro NUC442/NUC472 Series Technical Reference Manual PA.15 MFP0 General purpose digital I/O pin. SC3_PWR MPF1 SmartCard3 power pin. UART2_RTS MPF2 Request to Send output pin for UART2. I2C0_SCL MPF4 I2C0 clock pin. EBI_A21 MPF7 EBI address bus bit21. This pad is embedded with “Slew Rate Control” Slew capability.
  • Page 218 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM0_3 MPF4 PWM0_3 output/capture input. EBI_A24 MPF6 EBI address bus bit24. EBI_AD3 MPF7 EBI address/data bus bit 3. This pad is embedded with “Slew Rate Control” Slew capability. LDO_CAP MFP0 LDO output pin. MFP0 Ground pin for digital circuit.
  • Page 219 NuMicro NUC442/NUC472 Series Technical Reference Manual INT5 MPF8 External interrupt5 input pin. This pad is embedded with “Slew Rate Control” Slew capability. VRES MFP0 USB PHY VRES ground input pin. Add an 8.2K ohm resistor to VSSA. VBUS MFP0 USB PHY VBUS power input pin. USB_VDD33_CAP MFP0 Internal power regulator output 3.3V decoupling pin.
  • Page 220 NuMicro NUC442/NUC472 Series Technical Reference Manual I2S1_DO MPF2 I2S1 data output. UART4_RTS MPF3 Request to Send output pin for UART4. SC3_DAT MPF4 SmartCard3 data pin. This pad is embedded with “Slew Rate Control” Slew capability. PG.9 MFP0 General purpose digital I/O pin. SPI2_CLK MPF1 SPI2 serial clock pin.
  • Page 221 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew capability. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital circuit. MFP0 Ground pin for digital circuit. PB.2 MFP0 General purpose digital I/O pin. UART1_RXD MPF1 Data receiver input pin for UART1.
  • Page 222 NuMicro NUC442/NUC472 Series Technical Reference Manual UART4_TXD MPF3 Data transmitter output pin for UART4. EBI_AD7 MPF7 EBI address/data bus bit 7. This pad is embedded with “Slew Rate Control” Slew capability. PB.6 MFP0 General purpose digital I/O pin. I2C2_SCL MPF1 I2C2 clock pin.
  • Page 223 NuMicro NUC442/NUC472 Series Technical Reference Manual UART5_RTS MPF1 Request to Send output pin for UART5. EPWM1_3 MPF5 PWM1_3 output/capture input. EBI_AD11 MPF7 EBI address/data bus bit 11. This pad is embedded with “Slew Rate Control” Slew capability. PB.10 MFP0 General purpose digital I/O pin. UART5_TXD MPF1 Data transmitter output pin for UART5.
  • Page 224 NuMicro NUC442/NUC472 Series Technical Reference Manual CAN0_RXD MPF3 CAN bus receiver0 input. EMAC_MII_MDC MPF6 MII/RMII Management Data Clock. EBI_AD14 MPF7 EBI address/data bus bit 14. This pad is embedded with “Slew Rate Control” Slew capability. PB.13 MFP0 General purpose digital I/O pin. UART4_CTS MPF1 Clear to Send input pin for UART4.
  • Page 225 NuMicro NUC442/NUC472 Series Technical Reference Manual LDO_CAP MFP0 LDO output pin. PC.0 MFP0 General purpose digital I/O pin. I2S1_DI MPF1 I2S1 data input. SC1_DAT MPF2 SmartCard1 data pin. UART4_RXD MPF3 Data receiver input pin for UART4. EMAC_REFCLK MPF6 EMAC RMII mode clock input EBI_MCLK MPF7 EBI interface clock output pin.
  • Page 226 NuMicro NUC442/NUC472 Series Technical Reference Manual I2S1_MCLK MPF1 I2S1 master clock output pin. SC1_CD MPF2 SmartCard1 card detect pin. UART4_CTS MPF3 Clear to Send input pin for UART4. SPI0_MISO1 MPF4 2nd SPI0 MISO (Master In, Slave Out) pin. QEI0_Z MPF5 Quadrature encoder phase Z input of QEI Unit 0.
  • Page 227 NuMicro NUC442/NUC472 Series Technical Reference Manual TM2_EXT MPF1 Timer2 external counter input SPI0_MISO0 MPF4 1st SPI0 MISO (Master In, Slave Out) pin. TM2_CNT_OUT MPF5 Timer2 event counter input/toggle output. EMAC_MII_TXD0 MPF6 MII/RMII Transmit Data Bus bit 0. EBI_AD9 MPF7 EBI address/data bus bit 9. This pad is embedded with “Slew Rate Control”...
  • Page 228 NuMicro NUC442/NUC472 Series Technical Reference Manual EMAC_MII_RXD2 MPF6 MII Receive Data Bus Bit 2. This pad is embedded with “Slew Rate Control” Slew capability. PF.4 MFP0 General purpose digital I/O pin. SPI3_MISO0 MPF1 1st SPI3 MISO (Master In, Slave Out) pin. SD0_DAT1 MPF4 SD mode #0 data line bit 1.
  • Page 229 NuMicro NUC442/NUC472 Series Technical Reference Manual UART2_RTS MPF1 Request to Send output pin for UART2. SD0_CLK MPF4 SD mode #0 – clock. EMAC_MII_TXD2 MPF6 MII Transmit Data Bus bit 2. This pad is embedded with “Slew Rate Control” Slew capability. PH.2 MFP0 General purpose digital I/O pin.
  • Page 230 NuMicro NUC442/NUC472 Series Technical Reference Manual PH.10 MFP0 General purpose digital I/O pin. SPI2_MOSI1 MPF1 2nd SPI2 MOSI (Master Out, Slave In) pin. This pad is embedded with “Slew Rate Control” Slew capability. LDO_CAP MFP0 LDO output pin. MFP0 Ground pin for digital circuit. MFP0 Power supply for I/O ports and LDO source for internal PLL and digital circuit.
  • Page 231 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI0_SS0 MPF3 General purpose digital I/O pin. This pad is embedded with “Slew Rate Control” Slew capability. PE.5 MFP0 General purpose digital I/O pin. ADC0_5 MPF1 ADC0 analog input. ACMP0_P1 MPF2 Analog comparator0 positive input pin. SPI0_CLK MPF3 SPI0 serial clock pin.
  • Page 232 NuMicro NUC442/NUC472 Series Technical Reference Manual PE.8 MFP0 General purpose digital I/O pin. ADC1_0 MPF1 ADC1 analog input. ADC0_8 MPF1 ADC0 analog input. ACMP1_N MPF2 Analog comparator1 negative input pin. TM1_CNT_OUT MPF3 Timer1 event counter input/toggle output. SD0_DAT3 MPF4 SD mode #0 data line bit 3. EBI_ALE MPF7 EBI address latch enable output pin.
  • Page 233 NuMicro NUC442/NUC472 Series Technical Reference Manual ACMP1_P2 MPF2 Analog comparator1 positive input pin. SPI0_MOSI1 MPF3 2nd SPI0 MOSI (Master Out, Slave In) pin. SD0_DAT0 MPF4 SD mode #0 data line bit 0. ACMP2_P3 MPF5 Analog comparator2 positive input pin. EBI_nCS0 MPF7 EBI chip select 0 enable output pin.

  • Page 234: Summary Gpio Multi-Function Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.3.9 Summary GPIO Multi-function Pin Description MFP* = Multi-function pin. (Reference section 6.2.5) MPF1 MPF2 MPF3 MPF4 MPF5 MPF6 MPF7 MPF8 MPF9 PA.0 TAMPER0 SC0_CD CAN1_RXD INT0 PA.1 TAMPER1 SC5_CD CAN1_TXD EBI_A22 SPI3_MIS CAP_SFIEL PA.2 SC2_DAT I2S0_MCLK BRAKE11 EBI_A12...
  • Page 235 NuMicro NUC442/NUC472 Series Technical Reference Manual PB.6 I2C2_SCL BRAKE01 UART4_RTS PWM1_4 EPWM1_0 EBI_AD8 PB.7 I2C2_SDA BRAKE00 UART4_CTS PWM1_5 EPWM1_1 EBI_AD9 EBI_AD1 PB.8 UART5_CTS EPWM1_2 EBI_AD1 PB.9 UART5_RTS EPWM1_3 PB.1 EBI_AD1 UART5_TXD EPWM1_4 PB.1 EBI_AD1 UART5_RXD EPWM1_5 PB.1 SPI2_MIS EMAC_MII_MD EBI_AD1 UART4_RTS CAN0_RXD PB.1...
  • Page 236 NuMicro NUC442/NUC472 Series Technical Reference Manual PC.1 SD1_CM SPI1_MOSI1 SC4_RST CAP_DATA6 EBI_A1 PC.1 SC4_PW SPI1_MISO1 TM3_EXT SD1_CLK CAP_DATA5 EBI_A2 PC.1 SD1_DAT SPI1_MOSI0 SC4_DAT CAP_DATA4 EBI_A3 SD1_DAT PD.0 SPI1_MISO0 SC4_CLK CAP_DATA3 EBI_A4 INT3 TM0_CNT_ SD1_DAT PD.1 SPI1_CLK CAP_DATA2 EBI_A5 SD1_DAT PD.2 STADC I2C3_SCL CAP_DATA1 EBI_A6...
  • Page 237 NuMicro NUC442/NUC472 Series Technical Reference Manual ACMP0_P PE.5 ADC0_5 SPI0_CLK SD0_CDn ACMP0_P SD0_CM EBI_nW PE.6 ADC0_6 SPI0_MISO0 EBI_nR PE.7 ADC0_7 ACMP0_N SPI0_MOSI0 SD0_CLK ADC1_0/ TM1_CNT_ SD0_DAT PE.8 ACMP1_N EBI_ALE ADC0_8 ADC1_1/ADC0 ACMP1_P SD0_DAT EBI_nW PE.9 PE.1 ADC1_2/ADC0 ACMP1_P SD0_DAT EBI_nW SPI0_MISO1 PE.1 ADC1_3/ADC0...
  • Page 238 NuMicro NUC442/NUC472 Series Technical Reference Manual PF.1 UART1_C OPA1_IN+ PF.1 UART1_T OPA1_IN- PF.1 UART1_R OPA1_O PF.1 UART0_RTS PG.0 UART0_CTS INT6 PG.1 UART0_RXD PG.2 UART0_TXD PG.3 PS2_CLK I2S1_DO SC1_RST PG.4 PS2_DAT I2S1_DI SC1_PWR I2S1_BCL PG.5 SC1_DAT I2S1_LRC PG.6 SC1_CLK I2S1_MCL PG.7 SPI2_MISO0 SC1_CD SC3_RST PG.8 SPI2_MOSI0...
  • Page 239 NuMicro NUC442/NUC472 Series Technical Reference Manual PH.7 SPI2_MISO0 PH.8 SPI2_MOSI0 PH.9 SPI2_MISO1 PH.1 SPI2_MOSI1 PH.1 UART3_RXD PH.1 UART3_TXD PH.1 UART3_RTS PH.1 UART3_CTS PH.1 SC5_CLK PI.0 SC5_RST SC5_PW PI.1 PI.2 SC5_DAT PI.3 SPI3_SS0 PI.4 SPI3_CLK PI.5 SPI3_MISO0 PI.6 SPI3_MOSI0 SPI3_MIS PI.7 I2C2_SCL SPI3_MO PI.8 I2C2_SDA PI.9...

  • Page 240: Summary Function Pin Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 4.3.10 Summary Function Pin Description Group Pin Name GPIO *MFP Type Description ACMP0 ACMP0_N PE.7 MPF2 Analog comparator0 negative input pin. ACMP0 ACMP0_O PE.2 MPF2 Analog ccomparator0 output . ACMP0 ACMP0_P0 PE.6 MPF2 Analog comparator0 positive input pin. ACMP0 ACMP0_P1 PE.5...
  • Page 241 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC1 ADC1_1 PE.9 MPF1 ADC1 analog input. ADC1 ADC1_2 PE.10 MPF1 ADC1 analog input. ADC1 ADC1_3 PE.11 MPF1 ADC1 analog input. ADC1 ADC1_4 PE.12 MPF1 ADC1 analog input. ADC1 ADC1_5 PE.13 MPF1 ADC1 analog input. ADC1 ADC1_6 PE.14...
  • Page 242 NuMicro NUC442/NUC472 Series Technical Reference Manual CAN1 CAN1_TXD PH.1 MPF3 CAN bus transmitter1 input. CLKO CLKO PC.5 MPF1 Clock Output Pin. EBI_A0 PC.12 MPF7 EBI address bus bit0. EBI_A1 PC.13 MPF7 EBI address bus bit1. EBI_A10 PD.6 MPF7 EBI address bus bit10. EBI_A11 PD.7 MPF7...
  • Page 243 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_AD13 PB.11 MPF7 EBI address/data bus bit 13. EBI_AD13 PC.1 MPF7 EBI address/data bus bit 13. EBI_AD14 PB.12 MPF7 EBI address/data bus bit 14. EBI_AD15 PB.13 MPF7 EBI address/data bus bit 15. EBI_AD2 PA.13 MPF7 EBI address/data bus bit 2.
  • Page 244 NuMicro NUC442/NUC472 Series Technical Reference Manual EBI_AD EBI_AD11 PB.9 MPF7 EBI address/data bus bit 1. EBI_AD EBI_AD11 PC.3 MPF7 EBI address/data bus bit 1. EBI_AD EBI_AD12 PB.10 MPF7 EBI address/data bus bit 1. EBI_AD EBI_AD12 PC.2 MPF7 EBI address/data bus bit 1. EBI_AD EBI_AD13 PB.11...
  • Page 245 NuMicro NUC442/NUC472 Series Technical Reference Manual ECAP0 ECAP0_IC2 PD.13 MPF3 Input 2 of enhanced capture unit 0. ECAP1 ECAP1_IC0 PA.6 MPF8 Input 0 of enhanced capture unit 1. ECAP1 ECAP1_IC1 PA.5 MPF8 Input 1 of enhanced capture unit 1. ECAP1 ECAP1_IC2 PA.4 MPF8...
  • Page 246 NuMicro NUC442/NUC472 Series Technical Reference Manual EMAC_RMII EMAC_REFCLK PC.0 MPF6 EMAC RMII mode clock input EPWMA EPWM0_0 PA.12 MPF5 I/O PWM0_0 output/capture input. EPWMA EPWM0_1 PA.11 MPF5 I/O PWM0_1 output/capture input. EPWMA EPWM0_2 PA.10 MPF5 I/O PWM0_2 output/capture input. EPWMA EPWM0_3 PA.9 MPF5...
  • Page 247 NuMicro NUC442/NUC472 Series Technical Reference Manual I2S0 I2S0_BCLK PA.5 MPF3 I2S0 bit clock pin. I2S0 I2S0_DI PA.4 MPF3 I2S0 data input. I2S0 I2S0_DO PA.3 MPF3 I2S0 data output. I2S0 I2S0_LRCK PA.6 MPF3 I2S0 left right channel clock. I2S0 I2S0_MCLK PA.2 MPF3 I2S0 master clock output pin.
  • Page 248 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO PA.10 PA.10 MFP0 I/O General purpose digital I/O pin. GPIO PA.11 PA.11 MFP0 I/O General purpose digital I/O pin. GPIO PA.12 PA.12 MFP0 I/O General purpose digital I/O pin. GPIO PA.13 PA.13 MFP0 I/O General purpose digital I/O pin.
  • Page 249 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO PC.14 PC.14 MFP0 I/O General purpose digital I/O pin. GPIO PC.15 PC.15 MFP0 I/O General purpose digital I/O pin. GPIO PC.2 PC.2 MFP0 I/O General purpose digital I/O pin. GPIO PC.3 PC.3 MFP0 I/O General purpose digital I/O pin.
  • Page 250 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO PE.3 PE.3 MFP0 I/O General purpose digital I/O pin. GPIO PE.4 PE.4 MFP0 I/O General purpose digital I/O pin. GPIO PE.5 PE.5 MFP0 I/O General purpose digital I/O pin. GPIO PE.6 PE.6 MFP0 I/O General purpose digital I/O pin.
  • Page 251 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO PG.6 PG.6 MFP0 I/O General purpose digital I/O pin. GPIO PG.7 PG.7 MFP0 I/O General purpose digital I/O pin. GPIO PG.8 PG.8 MFP0 I/O General purpose digital I/O pin. GPIO PG.9 PG.9 MFP0 I/O General purpose digital I/O pin.
  • Page 252 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO PI.9 PI.9 MFP0 I/O General purpose digital I/O pin. OTG_PHY USB0_D- USB0_D- USB0 differential signal D+. OTG_PHY USB0_D+ USB0_D+ USB0 differential signal D+. USB0_OTG OTG_PHY USB0_OTG_ID USB0OTG ID pin. OTG_PHY VBUS VBUS USB PHY VBUS power input pin. Vref Vref Voltage reference input for ADC.
  • Page 253 NuMicro NUC442/NUC472 Series Technical Reference Manual QEI1 QEI1_A PA.6 MPF5 Quadrature encoder phase A input of QEI Unit 1. QEI1 QEI1_B PA.5 MPF5 Quadrature encoder phase B input of QEI Unit 1. QEI1 QEI1_Z PA.4 MPF5 Quadrature encoder phase Z input of QEI Unit 1. SC0_CD PA.0 MPF2...
  • Page 254 NuMicro NUC442/NUC472 Series Technical Reference Manual SC3_RST PC.9 MPF3 SmartCard3 reset pin. SC3_RST PD.11 MPF1 SmartCard3 reset pin. SC3_RST PG.7 MPF4 SmartCard3 reset pin. SC4_CD PC.12 MPF2 SmartCard4 card detect pin. SC4_CLK PD.0 MPF2 SmartCard4 clock pin. SC4_DAT PC.15 MPF2 I/O SmartCard4 data pin.
  • Page 255 NuMicro NUC442/NUC472 Series Technical Reference Manual SDHOST1 SD1_CDn PC.12 MPF4 SD mode #1 – card detect SDHOST1 SD1_CLK PC.14 MPF4 SD mode #1– clock; SDHOST1 SD1_CMD PC.13 MPF4 I/O SD mode #1 – command/response SDHOST1 SD1_DAT0 PD.2 MPF4 I/O SD mode #1 data line bit 0; SDHOST1 SD1_DAT1 PD.1...
  • Page 256 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew PB.7 Slew capability. This pad is embedded with “Slew Rate Control” Slew PB.8 Slew capability. This pad is embedded with “Slew Rate Control” Slew PB.9 Slew capability.
  • Page 257 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew PC.14 Slew capability. This pad is embedded with “Slew Rate Control” Slew PC.15 Slew capability. This pad is embedded with “Slew Rate Control” Slew PD.0 Slew capability.
  • Page 258 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew PE.10 Slew capability. This pad is embedded with “Slew Rate Control” Slew PE.11 Slew capability. This pad is embedded with “Slew Rate Control” Slew PE.12 Slew capability.
  • Page 259 NuMicro NUC442/NUC472 Series Technical Reference Manual This pad is embedded with “Slew Rate Control” Slew PH.9 Slew capability. This pad is embedded with “Slew Rate Control” Slew PH.10 Slew capability. This pad is embedded with “Slew Rate Control” Slew PI.3 Slew capability.
  • Page 260 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI1 SPI1_MOSI1 PC.13 MPF1 I/O 2nd SPI1 MOSI (Master Out, Slave In) pin. SPI1 SPI1_SS0 PC.12 MPF1 I/O 1st SPI1 slave select pin. SPI1 SPI1_SS0 PD.13 MPF1 I/O 1st SPI1 slave select pin. SPI2 SPI2_CLK PB.3 MPF2...
  • Page 261 NuMicro NUC442/NUC472 Series Technical Reference Manual SPI3 SPI3_MOSI0 PI.6 MPF1 I/O 1st SPI3 MOSI (Master Out, Slave In) pin. SPI3 SPI3_MOSI1 PA.12 MPF3 I/O 2nd SPI3 MOSI (Master Out, Slave In) pin. SPI3 SPI3_MOSI1 PD.9 MPF1 I/O 2nd SPI3 MOSI (Master Out, Slave In) pin. SPI3 SPI3_MOSI1 PI.8...
  • Page 262 NuMicro NUC442/NUC472 Series Technical Reference Manual UART1 UART1_RXD PF.14 MPF2 Data receiver input pin for UART1. UART1 UART1_TXD PB.3 MPF1 Data transmitter output pin for UART1. UART1 UART1_TXD PF.13 MPF2 Data transmitter output pin for UART1. UART2 UART2_CTS PC.9 MPF2 Clear to Send input pin for UART2.
  • Page 263 NuMicro NUC442/NUC472 Series Technical Reference Manual UART5 UART5_RTS PB.9 MPF1 Request to Send output pin for UART5. UART5 UART5_RTS PD.14 MPF2 Request to Send output pin for UART5. UART5 UART5_RXD PB.11 MPF1 Data receiver input pin for UART5. UART5 UART5_RXD PF.0 MPF2 Data receiver input pin for UART5.

  • Page 264: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual BLOCK DIAGRAM NuMicro NUC442 Series Block Diagram Figure 5.1-1 NuMicro NUC442 Series Block Diagram May 23, 2014 Page 264 of 1386 Rev.1.05...

  • Page 265: Numicro Nuc472 Series Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual NuMicro NUC472 Series Block Diagram Figure 5.2-1 NuMicro NUC472 Series Block Diagram May 23, 2014 Page 265 of 1386 Rev.1.05...

  • Page 266: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual FUNCTIONAL DESCRIPTION ® ® Cortex -M4 Core ® The Cortex -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA AHB-Lite interfaces for best parallel performance and includes an NVIC component. The processor with optional hardware debug functionality can execute Thumb code and is compatible ®...
  • Page 267 NuMicro NUC442/NUC472 Series Technical Reference Manual  Banked Stack Pointer (SP)  Hardware integer divide instructions, SDIV and UDIV  Handler and Thread modes  Thumb and Debug states  Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low interrupt latency ...
  • Page 268 NuMicro NUC442/NUC472 Series Technical Reference Manual  Debug access to all memory and registers in the system, including access to memory mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is asserted.

  • Page 269: System Manager

    NuMicro NUC442/NUC472 Series Technical Reference Manual System Manager 6.2.1 Overview System management includes the following sections:  System Resets  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset , multi-functional pin control ...

  • Page 270: System Power Distribution

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.3 System Power Distribution In this chip, power distribution is divided into three segments:  Analog power from AVDD and AVSS provides the power for analog components operation.  Digital power from VDD and VSS supplies the power to the internal regulator which provides a fixed 1.8 V power for digital operation and I/O pins.

  • Page 271: System Memory Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.4 System Memory Map The NUC442/NUC472 series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the following table. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on-chip peripherals.
  • Page 272 NuMicro NUC442/NUC472 Series Technical Reference Manual 0x4005_0000 – 0x4005_0FFF TMR01_BA Timer0/Timer1 Control Registers 0x4005_1000 – 0x4005_1FFF TMR23_BA Timer2/Timer3 Control Registers 0x4005_8000 – 0x4005_8FFF PWM0_BA PWM0_0/1/2/3/4/5 Control Registers 0x4005_9000 – 0x4005_9FFF PWM1_BA PWM1_0/1/2/3/4/5 Control Registers 0x4005_C000 – 0x4005_CFFF EPWM0_BA Enhanced PWM0_0/1/2/3/4/5 Control Registers 0x4005_D000 –...

  • Page 273: Table 6.2-1 Address Space Assignments For On-Chip Controllers

    NuMicro NUC442/NUC472 Series Technical Reference Manual (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers Table 6.2-1 Address Space Assignments for On-Chip Controllers May 23, 2014 Page 273 of 1386 Rev.1.05...

  • Page 274: System Control Registers

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.5 System Control Registers R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value SYS Base Address: SYS_BA = 0x4000_0000 SYS_PDID SYS_BA+0x00 Part Device Identification Number Register 0x0014_0018 SYS_RSTSTS SYS_BA+0x04 R/W System Reset Source Register...
  • Page 275 NuMicro NUC442/NUC472 Series Technical Reference Manual SYS_GPG_MFP SYS_BA+0x60 R/W Port G Low Byte Multi-function Control Register 0x0000_0000 SYS_GPG_MFP SYS_BA+0x64 R/W Port G High Byte Multi-function Control Register 0xXXXX_1100 SYS_GPH_MFP SYS_BA+0x68 R/W Port H Low Byte Multi-function Control Register 0x0000_0000 SYS_GPH_MFP SYS_BA+0x6C R/W Port H High Byte Multi-function Control Register 0x0000_0000...
  • Page 276 NuMicro NUC442/NUC472 Series Technical Reference Manual Part Device ID Code Register (SYS_PDID) Register Offset Description Reset Value SYS_PDID SYS_BA+0x00 Part Device Identification Number Register 0x0014_0018 [1] Every part number has a unique default reset value. Part Number [31:24] Part Number [23:16] Part Number [15:8] Part Number [7:0] Bits...
  • Page 277 NuMicro NUC442/NUC472 Series Technical Reference Manual System Reset Source Register (SYS_RSTSTS) This register provides specific information for software to identify this chip’s reset source from last operation. Register Offset Description Reset Value SYS_RSTSTS SYS_BA+0x04 System Reset Source Register 0x0000_014B Reserved Reserved Reserved CPURF...
  • Page 278 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description LVR Reset Flag The LVR reset flag is set by the “Reset Signal” from the Low Voltage Reset Controller to indicate the previous reset source. LVRF 0 = No reset from LVR. 1 = LVR controller had issued the reset signal to reset the system.
  • Page 279 NuMicro NUC442/NUC472 Series Technical Reference Manual Peripheral Reset Control Register1 (SYS_IPRST0)-AHB BUS Register Offset Description Reset Value SYS_IPRST0 SYS_BA+0x08 Peripheral Controller Reset Control Register 1 0x0000_0000 Reserved Reserved Reserved CRYPTORST Reserved CAPRST CRCRST SDHRST EMACRST USBHRST EBIRST PDMARST CPURST CHIPRST Bits Description [31:13]...
  • Page 280 NuMicro NUC442/NUC472 Series Technical Reference Manual This bit is a write protected bit, It means programming this bit needs to write “59h”, “16h”, “88h” to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100 0 = SD HOST controller normal operation. 1 = SD HOST controller reset.
  • Page 281 NuMicro NUC442/NUC472 Series Technical Reference Manual SYS_REGLCTL at address GCR_BA+0x100 0 = Chip normal operation. 1 = Chip one shot reset. May 23, 2014 Page 281 of 1386 Rev.1.05...
  • Page 282 NuMicro NUC442/NUC472 Series Technical Reference Manual Peripheral Reset Control Register2 (SYS_IPRST1) APB BUS Setting these bits 1 will generate asynchronous reset signals to the corresponding IP controller. Users need to set these bits to 0 to release corresponding IP controller from reset state. Register Offset Description...
  • Page 283 NuMicro NUC442/NUC472 Series Technical Reference Manual [23:22] Reserved Reserved. UART2 Controller Reset UART5RST 0 = UART5 controller normal operation. [21] 1 = UART5 controller reset. UART4 Controller Reset UART4RST [20] 0 = UART4 controller normal operation. 1 = UART4 controller reset. UART3 Controller Reset [19] UART3RST...
  • Page 284 NuMicro NUC442/NUC472 Series Technical Reference Manual Timer3 Controller Reset TMR3RST 0 = Timer3 controller normal operation. 1 = Timer3 controller reset. Timer2 Controller Reset TMR2RST 0 = Timer2 controller normal operation. 1 = Timer2 controller reset. Timer1 Controller Reset TMR1RST 0 = Timer1 controller normal operation.
  • Page 285 NuMicro NUC442/NUC472 Series Technical Reference Manual Peripheral Reset Control Register 3 (SYS_IPRST2) APB BUS Setting these bits 1 will generate asynchronous reset signals to the corresponding IP controller. Users need to set these bits to 0 to release corresponding IP controller from reset state. Register Offset Description...
  • Page 286 NuMicro NUC442/NUC472 Series Technical Reference Manual SC4 Controller Reset SC4RST 0 = SC4 controller normal operation. 1 = SC4 controller reset. SC3 Controller Reset SC3RST 0 = SC3 controller normal operation. 1 = SC3 controller reset. SC2 Controller Reset SC2RST 0 = SC2 controller normal operation.
  • Page 287 NuMicro NUC442/NUC472 Series Technical Reference Manual Brown-out Detector Control Register (SYS_BODCTL) Partial of the SYS_BODCTL control registers values are initiated by the flash configuration and partial bits are write-protected bit. Programming write-protected bits needs to write “59h”, “16h”, “88h” to address 0x4000_0100 to disable register protection.
  • Page 288 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description Brown-Out Detector Interrupt Flag 0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. BODINTF 1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
  • Page 289 NuMicro NUC442/NUC472 Series Technical Reference Manual Temperature Sensor Control Register (SYS_TEMPCTL) Register Offset Description Reset Value SYS_TEMPCTL SYS_BA+0x1C Temperature Sensor Control Register 0x0000_0000 Reserved Reserved Reserved Reserved VTEMPEN Bits Description [31:1] Reserved Reserved. Temperature Sensor Enable Bit This bit is used to enable/disable temperature sensor function. 0 = Temperature sensor function Disabled (default).
  • Page 290 NuMicro NUC442/NUC472 Series Technical Reference Manual Version Control ID Register (SYS_VCID) Register Offset Description Reset Value SYS_VCID SYS_BA+0x20 Hardware Version Control Register 0x0000_0000 Reserved Reserved VCID[15:8] VCID[7:0] Bits Description [31:16] Reserved Reserved. Hardware Version Control (Ready Only) These registers repress hardware version. These bits are the read protected bits.
  • Page 291 NuMicro NUC442/NUC472 Series Technical Reference Manual Power-on-Reset Control Register (SYS_PORCTL) Register Offset Description Reset Value SYS_PORCTL SYS_BA+0x24 Power-On-Reset Controller Register 0x0000_0000 Reserved Reserved POROFF[15:8] POROFF[7:0] Bits Description [31:16] Reserved Reserved. Power-On-Reset Enable Bit (Write Protect) When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
  • Page 292 NuMicro NUC442/NUC472 Series Technical Reference Manual VREF Control Register (SYS_VREFCTL) Register Offset Description Reset Value SYS_VREFCTL SYS_BA+0x28 ADC VREF Control Register 0x0000_0000 Reserved Reserved PWMSYNCMO ADCMODESE Reserved Reserved VREFCTL Bits Description [31:10] Reserved Reserved. PWM SYNC MODE (Write Protect) PWMSYNCMODE 0 = PWM SYNC MODE Disabled;...
  • Page 293 NuMicro NUC442/NUC472 Series Technical Reference Manual USBPHY Control Register (SYS_USBPHY) Register Offset Description Reset Value SYS_USBPHY SYS_BA+0x2C USB PHY Control Register 0x0000_000X Reserved Reserved Reserved LDO33EN Reserved USBROLE Bits Description [31:9] Reserved Reserved. LDO33 Enable Bit (Write Protect) LDO33EN 0 = USB LDO33 Disabled. 1 = USB LDO33 Enabled.
  • Page 294 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOA Low Byte Control Register (SYS_GPA_MFPL) Register Offset Description Reset Value SYS_GPA_MF SYS_BA+0x30 Port A Low Byte Multi-function Control Register 0x0000_0000 PA7MFP PA6MFP PA5MFP PA4MFP PA3MFP PA2MFP PA1MFP PA0MFP Bits Description [31:28] PA7MFP[3:0] PA.7 Multi-function Pin Selection PA6MFP[3:0] PA.6 Multi-function Pin Selection...
  • Page 295 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOA High Byte Control Register (SYS_GPA_MFPH) Register Offset Description Reset Value SYS_GPA_MF SYS_BA+0x34 Port A High Byte Multi-function Control Register 0x0000_0000 PA15MFP PA14MFP PA13MFP PA12MFP PA11MFP PA10MFP PA9MFP PA8MFP Bits Description [31:28] PA15MFP[3:0] PA.15 Multi-function Pin Selection PA14MFP[3:0] PA.14 Multi-function Pin Selection...
  • Page 296 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOB Low Byte Control Register (SYS_GPB_MFPL) Register Offset Description Reset Value SYS_GPB_MF SYS_BA+0x38 Port B Low Byte Multi-function Control Register 0x0000_0000 PB7MFP PB6MFP PB5MFP PB4MFP PB3MFP PB2MFP PB1MFP PB0MFP Bits Description [31:28] PB7MFP[3:0] PB.7 Multi-function Pin Selection PB6MFP[3:0] PB.6 Multi-function Pin Selection...
  • Page 297 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOB high byte Control Register (SYS_GPB_MFPH) Register Offset Description Reset Value SYS_GPB_MF SYS_BA+0x3C Port B High Byte Multi-function Control Register 0x0000_0000 PB15MFP PB14MFP PB13MFP PB12MFP PB11MFP PB10MFP PB9MFP PB8MFP Bits Description [31:28] PB15MFP[3:0] PB.15 Multi-function Pin Selection PB14MFP[3:0] PB.14 Multi-function Pin Selection...
  • Page 298 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOC Low Byte Control Register (SYS_GPC_MFPL) Register Offset Description Reset Value SYS_GPC_MF SYS_BA+0x40 Port C Low Byte Multi-function Control Register 0x0000_0000 PC7MFP PC6MFP PC5MFP PC4MFP PC3MFP PC2MFP PC1MFP PC0MFP Bits Description [31:28] PC7MFP[3:0] PC.7 Multi-function Pin Selection PC6MFP[3:0] PC.6 Multi-function Pin Selection...
  • Page 299 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOC high byte Control Register (SYS_GPC_MFPH) Register Offset Description Reset Value SYS_GPC_MF SYS_BA+0x44 Port C High Byte Multi-function Control Register 0x0000_0000 PC15MFP PC14MFP PC13MFP PC12MFP PC11MFP PC10MFP PC9MFP PC8MFP Bits Description [31:28] PC15MFP[3:0] PC.15 Multi-function Pin Selection PC14MFP[3:0] PC.14 Multi-function Pin Selection...
  • Page 300 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOD Low Byte Control Register (SYS_GPD_MFPL) Register Offset Description Reset Value SYS_GPD_MF SYS_BA+0x48 Port D Low Byte Multi-function Control Register 0x0000_0000 PD7MFP PD6MFP PD5MFP PD4MFP PD3MFP PD2MFP PD1MFP PD0MFP Bits Description [31:28] PD7MFP[3:0] PD.7 Multi-function Pin Selection PD6MFP[3:0] PD.6 Multi-function Pin Selection...
  • Page 301 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOD high byte Control Register (SYS_GPD_MFPH) Register Offset Description Reset Value SYS_GPD_MF SYS_BA+0x4C Port D High Byte Multi-function Control Register 0x0000_0000 PD15MFP PD14MFP PD13MFP PD12MFP PD11MFP PD10MFP PD9MFP PD8MFP Bits Description [31:28] PD15MFP[3:0] PD.15 Multi-function Pin Selection PD14MFP[3:0] PD.14 Multi-function Pin Selection...
  • Page 302 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOE Low Byte Control Register (SYS_GPE_MFPL) Register Offset Description Reset Value SYS_GPE_MF SYS_BA+0x50 Port E Low Byte Multi-function Control Register 0x0000_0000 PE7MFP PE6MFP PE5MFP PE4MFP PE3MFP PE2MFP PE1MFP PE0MFP Bits Description [31:28] PE7MFP[3:0] PE.7 Multi-function Pin Selection PE6MFP[3:0] PE.6 Multi-function Pin Selection...
  • Page 303 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOE high byte Control Register (SYS_GPE_MFPH) Register Offset Description Reset Value SYS_GPE_MF SYS_BA+0x54 Port E High Byte Multi-function Control Register 0x0000_0000 PE15MFP PE14MFP PE13MFP PE12MFP PE11MFP PE10MFP PE9MFP PE8MFP Bits Description [31:28] PE15MFP[3:0] PE.15 Multi-function Pin Selection PE14MFP[3:0] PE.14 Multi-function Pin Selection...
  • Page 304 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOF Low Byte Control Register (SYS_GPF_MFPL) Register Offset Description Reset Value SYS_GPF_MF SYS_BA+0x58 Port F Low Byte Multi-function Control Register 0x0000_0000 PF7MFP PF6MFP PF5MFP PF4MFP PF3MFP PF2MFP PF1MFP PF0MFP Bits Description [31:28] PF7MFP[3:0] PF.7 Multi-function Pin Selection PF6MFP[3:0] PF.6 Multi-function Pin Selection...
  • Page 305 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOF high byte Control Register (SYS_GPF_MFPH) Register Offset Description Reset Value SYS_GPF_MF SYS_BA+0x5C Port F High Byte Multi-function Control Register 0x0000_0000 PF15MFP PF14MFP PF13MFP PF12MFP PF11MFP PF10MFP PF9MFP PF8MFP Bits Description [31:28] PF15MFP[3:0] PF.15 Multi-function Pin Selection PF14MFP[3:0] PF.14 Multi-function Pin Selection...
  • Page 306 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOG Low Byte Control Register (SYS_GPG_MFPL) Register Offset Description Reset Value SYS_GPG_M SYS_BA+0x60 Port G Low Byte Multi-function Control Register 0x0000_0000 PG7MFP PG6MFP PG5MFP PG4MFP PG3MFP PG2MFP PG1MFP PG0MFP Bits Description [31:28] PG7MFP[3:0] PG.7 Multi-function Pin Selection PG6MFP[3:0] PG.6 Multi-function Pin Selection...
  • Page 307 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOG high byte Control Register (SYS_GPG_MFPH) Register Offset Description Reset Value SYS_GPG_M SYS_BA+0x64 Port G High Byte Multi-function Control Register 0xXXXX_1100 PG15MFP PG14MFP PG13MFP PG12MFP PG11MFP PG10MFP PG9MFP PG8MFP Bits Description [31:28] PG15MFP[3:0] PG.15 Multi-function Pin Selection PG14MFP[3:0] PG.14 Multi-function Pin Selection...
  • Page 308 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOH Low Byte Control Register (SYS_GPH_MFPL) Register Offset Description Reset Value SYS_GPH_MF SYS_BA+0x68 Port H Low Byte Multi-function Control Register 0x0000_0000 PH7MFP PH6MFP PH5MFP PH4MFP PH3MFP PH2MFP PH1MFP PH0MFP Bits Description [31:28] PH7MFP[3:0] PH.7 Multi-function Pin Selection PH6MFP[3:0] PH.6 Multi-function Pin Selection...
  • Page 309 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOH high byte Control Register (SYS_GPH_MFPH) Register Offset Description Reset Value SYS_GPH_MF SYS_BA+0x6C Port H High Byte Multi-function Control Register 0x0000_0000 PH15MFP PH14MFP PH13MFP PH12MFP PH11MFP PH10MFP PH9MFP PH8MFP Bits Description [31:28] PH15MFP[3:0] PH.15 Multi-function Pin Selection PH14MFP[3:0] PH.14 Multi-function Pin Selection...
  • Page 310 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOI Low Byte Control Register (SYS_GPI_MFPL) Register Offset Description Reset Value SYS_GPI_MF SYS_BA+0x70 Port I Low Byte Multi-function Control Register 0x0000_0000 PI7MFP PI6MFP PI5MFP PI4MFP PI3MFP PI2MFP PI1MFP PI0MFP Bits Description [31:28] PI7MFP[3:0] PI.7 Multi-function Pin Selection PI6MFP[3:0] PI.6 Multi-function Pin Selection...
  • Page 311 NuMicro NUC442/NUC472 Series Technical Reference Manual Multi-function GPIOI high byte Control Register (SYS_GPI_MFPH) Register Offset Description Reset Value SYS_GPI_MF SYS_BA+0x74 Port I High Byte Multi-function Control Register 0x0000_0000 PI15MFP PI14MFP PI13MFP PI12MFP PI11MFP PI10MFP PI9MFP PI8MFP Bits Description [31:28] PI15MFP[3:0] PI.15 Multi-function Pin Selection PI14MFP[3:0] PI.14 Multi-function Pin Selection...
  • Page 312 NuMicro NUC442/NUC472 Series Technical Reference Manual SRAM Failed Interrupt Enable Control Register (SYS_SRAM_INTCTL) Register Offset Description Reset Value SYS_SRAM_INT SYS_BA+0xC0 SRAM Failed Interrupt Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved PERRIEN Bits Description [31:1] Reserved Reserved. SRAM Parity Check Fail Interrupt Enable Bit PERRIEN 0 = SRAMF INT Disabled.
  • Page 313 NuMicro NUC442/NUC472 Series Technical Reference Manual SRAM Parity Check Error Flag (SYS_SRAM_STATUS) Register Offset Description Reset Value SYS_SRAM_ST SYS_BA+0xC4 SRAM Parity Check Error Flag 0x0000_0000 ATUS Reserved Reserved Reserved Reserved PERRIF1 PERRIF0 Bits Description [31:2] Reserved Reserved. SRAM Parity Check Fail Flag PERRIF1 0 = 2nd SRAM fail.
  • Page 314 NuMicro NUC442/NUC472 Series Technical Reference Manual SRAM Parity Check Error First Address1 (SYS_SRAM0_ERRADDR) Register Offset Description Reset Value SYS_SRAM0_ER SYS_BA+0xC8 SRAM Parity Check Error First Address1 0x0000_0000 RADDR PERRADDR [31:24] PERRADDR [23:16] PERRADDR [15:8] PERRADDR [7:0] Bits Description First SRAM Parity Check Fail Address [31:0] PERRADDR This register shows the first system SRAM parity error byte address.
  • Page 315 NuMicro NUC442/NUC472 Series Technical Reference Manual SRAM Parity Check Error First Address2 (SYS_SRAM1_ERRADDR) Register Offset Description Reset Value SYS_SRAM1_ER SYS_BA+0xCC SRAM Parity Check Error First Address2 0x0000_0000 RADDR PERRADDR [31:24] PERRADDR [23:16] PERRADDR [15:8] PERRADDR [7:0] Bits Description Second SRAM Parity Check Fail Address [31:0] PERRADDR This register shows the second system SRAM parity error byte address.
  • Page 316 NuMicro NUC442/NUC472 Series Technical Reference Manual HIRC Trim Control Register (SYS_IRCTCTL) Register Offset Description Reset Value SYS_IRCTCTL SYS_BA+0xF0 IRC Trim Control Register 0x0000_0000 Reserved Reserved Reserved CESTOPEN RETRYCNT LOOPSEL Reserved FREQSEL Bits Description [31:9] Reserved Reserved. Clock Error Stop Enable Bit CESTOPEN 0 = The trim operation is keep going if clock is inaccuracy.
  • Page 317 NuMicro NUC442/NUC472 Series Technical Reference Manual During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 00 = Disable HIRC auto trim function. 01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
  • Page 318 NuMicro NUC442/NUC472 Series Technical Reference Manual HIRC Trim Interrupt Enable Control Register (SYS_IRCTIEN) Register Offset Description Reset Value SYS_IRCTIEN SYS_BA+0xF4 IRC Trim Interrupt Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKEIEN TFAILIEN Reserved Bits Description [31:3] Reserved Reserved. Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
  • Page 319 NuMicro NUC442/NUC472 Series Technical Reference Manual HIRC Trim Interrupt Status Register (SYS_IRCTISTS) Register Offset Description Reset Value SYS_IRCTISTS SYS_BA+0xF8 IRC Trim Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved CLKERRIF TFAILIF FREQLOCK Bits Description [31:3] Reserved Reserved. Clock Error Interrupt Status When the frequency of external 32.768 kHz low-speed crystal or HIRC is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy...
  • Page 320 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Write-Protection Control Register (SYS_REGLCTL) Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are protected after the power on reset till user to disable register protection.
  • Page 321 NuMicro NUC442/NUC472 Series Technical Reference Manual CLKSEL1 bit[1:0]: address 0x4000_0214 (for watchdog clock source select) NMI_SEL]: address 0x4000_0300 (for NMI source select) ISPCON: address 0x4000_5000 (Flash ISP Control register) ISPTRG: address 0x4000_5010 (ISP Trigger Control register) WTCR: address 0x4004_0000 FATCON: address 0x4000_5018 TAMPER: address 0x400E_1000 May 23, 2014 Page 321 of 1386...

  • Page 322: System Timer (Systick)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.6 System Timer (SysTick) ® The Cortex -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, and then decrement on subsequent clocks.
  • Page 323 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.6.2 System Timer Control Register Description SysTick Control and Status (SYST_CSR) Register Offset Description Reset Value SYST_CSR SCS_BA+0x10 SysTick Control and Status Register 0x0000_0000 Reserved Reserved COUNTFLAG Reserved Reserved CLKSRC TICKINT ENABLE Bits Description Reserved [31:17] Reserved.
  • Page 324 NuMicro NUC442/NUC472 Series Technical Reference Manual SysTick Reload Value Register (SYST_RVR) Register Offset Description Reset Value SYST_RVR SCS_BA+0x14 SysTick Reload Value Register 0xXXXX_XXXX Reserved RELOAD[23:16] RELOAD[15:8] RELOAD[7:0] Bits Description [31:24] Reserved Reserved. System Tick Reload Value RELOAD [23:0] Value to load into the Current Value register when the counter reaches 0. May 23, 2014 Page 324 of 1386 Rev.1.05...
  • Page 325 NuMicro NUC442/NUC472 Series Technical Reference Manual SysTick Current Value Register (SYST_CVR) Register Offset Description Reset Value SYST_CVR SCS_BA+0x18 SysTick Current Value Register 0xXXXX_XXXX Reserved CURRENT [23:16] CURRENT [15:8] CURRENT[7:0] Bits Description [31:24] Reserved Reserved. System Tick Current Value Current counter value. This is the value of the counter at the time it is sampled. The CURRENT [23:0] counter does not provide read-modify-write protection.

  • Page 326: Nested Vectored Interrupt Controller (Nvic)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.7 Nested Vectored Interrupt Controller (NVIC) The NVIC and the processor core interface are closely coupled to enable low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail-chaining of interrupts.

  • Page 327: Table 6.2-2 Exception Model

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.7.1 Exception Model and System Interrupt Map The following table lists the exception model supported by NUC4xx series. Software can set 16 levels of priority on some of these exceptions as well as on all interrupts. The highest user-configurable priority is denoted as “0x00”...
  • Page 328 NuMicro NUC442/NUC472 Series Technical Reference Manual Reserved RTC_INT Real time clock interrupt TAMPER TAMPER interrupt EINT0 External signal interrupt from PA.0 pin EINT1 External signal interrupt from PB.0 pin EINT2 External signal interrupt from PC.0 pin EINT3 External signal interrupt from PD.0 pin EINT4 External signal interrupt from PE.0 pin EINT5...
  • Page 329 NuMicro NUC442/NUC472 Series Technical Reference Manual EADC2 Enhanced ADC 2 interrupt EADC3 Enhanced ADC 3 interrupt 68 ~ 71 52 ~ 55 Reserved ACMP_INT Analog Comparator-0 or Comaprator-1 interrupt 73 ~ 75 57 ~ 59 Reserved OPA0_INT Analog OP0 interrupt OPA1_INT Analog OP1 interrupt ICAP0...
  • Page 330 NuMicro NUC442/NUC472 Series Technical Reference Manual EMAC_RX Ethernet MAC receive interrupt 110 ~ 111 94 ~ 95 Reserved SPI0_INT SPI0 interrupt SPI1_INT SPI1 interrupt SPI2_INT SPI2 interrupt SPI3_INT SPI3 interrupt 116 ~ 119 100 ~ 103 Reserved UART0_INT UART0 interrupt UART1_INT UART1 interrupt UART2_INT...

  • Page 331: Table 6.2-3 Interrupt Number Table

    NuMicro NUC442/NUC472 Series Technical Reference Manual PS2_INT PS/2 interrupt Image capture interface interrupt CRYPTO Crypto interrupt Table 6.2-3 Interrupt Number Table May 23, 2014 Page 331 of 1386 Rev.1.05...
  • Page 332 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.7.2 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set- Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write- 1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts.
  • Page 333 NuMicro NUC442/NUC472 Series Technical Reference Manual IRQ0 ~ IRQ159 Set-Enable Control Register (NVIC_ISERn) Register Offset Description Reset Value NVIC_ISERn NVIC_BA+0x4*n IRQ0 ~ IRQ159 Set-Enable Control Register 0x0000_0000 n=0,1..4 SETENA[31:24] SETENA[23:16] SETENA[15:8] SETENA[7:0] Bits Description Interrupt Set Enable Bit The NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled Write: 0 = No effect.
  • Page 334 NuMicro NUC442/NUC472 Series Technical Reference Manual IRQ0 ~ IRQ159 Clear-Enable Control Register (NVIC_ICERn) Register Offset Description Reset Value NVIC_ICERn NVIC_BA+0x80 IRQ0 ~ IRQ159 Clear-Enable Control Register 0x0000_0000 +0x4*n n=0,1..4 CLRENA[31:24] CLRENA[23:16] CLRENA[15:8] CLRENA[7:0] Bits Description Interrupt Clear Enable Control The NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.
  • Page 335 NuMicro NUC442/NUC472 Series Technical Reference Manual IRQ0 ~ IRQ159 Set-Pending Control Register (NVIC_ISPRn) Register Offset Description Reset Value NVIC_ISPRn NVIC_BA+0x100 IRQ0 ~ IRQ159 Set-Pending Control Register 0x0000_0000 +0x4*n n=0,1..4 SETPEND[31:24] SETPEND[23:16] SETPEND[15:8] SETPEND[7:0] Bits Description Interrupt Set-Pending The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending Write: 0 = No effect.
  • Page 336 NuMicro NUC442/NUC472 Series Technical Reference Manual IRQ0 ~ IRQ159 Clear-Pending Control Register (NVIC_ICPRn) Register Offset Description Reset Value NVIC_ICPRn NVIC_BA+0x180 IRQ0 ~ IRQ159 Clear-Pending Control Register 0x0000_0000 +0x4*n n=0,1..4 CLRPEND[31:24] CLRPEND[23:16] CLRPEND[15:8] CLRPEND[7:0] Bits Description Interrupt Clear-Pending The NVIC_ICPR0-NCVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending Write: 0 = No effect.
  • Page 337 NuMicro NUC442/NUC472 Series Technical Reference Manual IRQ0 ~ IRQ159 Active Bit Register (NVIC_IABRn) Register Offset Description Reset Value NVIC_IABRn NVIC_BA+0x200 IRQ0 ~ IRQ159 Active Bit Register 0x0000_0000 +0x4*n n=0,1..4 ACTIVE[31:24] ACTIVE[23:16] ACTIVE[15:8] ACTIVE[7:0] Bits Description Interrupt Active Flags The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. [31:0] ACTIVE 0 = interrupt not active.
  • Page 338 NuMicro NUC442/NUC472 Series Technical Reference Manual IRQ0 ~ IRQ159 Interrupt Priority Register (NVIC_IPRn) Register Offset Description Reset Value NVIC_IPRn NVIC_BA+0x300 IRQ0 ~ IRQ159 Interrupt Priority Control Register 0x0000_0000 +0x4*n n=0,1..31 PRI_4n[3] Reserved PRI_4n[2] Reserved PRI_4n[1] Reserved PRI_4n[0] Reserved Bits Description Priority Of IRQ_4n+3 [31:28] PRI_4n[3]...
  • Page 339 NuMicro NUC442/NUC472 Series Technical Reference Manual Software Trigger Interrupt Register (NVIC_STIR) Register Offset Description Reset Value NVIC_STIR NVIC_BA+0xE00 Software Trigger Interrupt Registers 0x0000_0000 Reserved Reserved Reserved INTID [8] INTID [7:0] Bits Description [31:9] Reserved Reserved. Interrupt ID Write to the STIR To Generate An Interrupt from Software When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access INTID [8:0]...
  • Page 340 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.7.4 NMI Control Registers R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value NMI Base Address: NMI_BA = 0x4000_0300 NMIEN NMI_BA+0x00 NMI source interrupt Enable Control Register 0x0000_0000 NMISTS NMI_BA+0x04...
  • Page 341 NuMicro NUC442/NUC472 Series Technical Reference Manual NMI source Interrupt Enable Control Register (NMIEN) Register Offset Description Reset Value NMIEN NMI_BA+0x00 NMI source interrupt Enable Control Register 0x0000_0000 Reserved Reserved EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 TAMPER Reserved CLKFAIL SRAMFAIL PWRWK Bits...
  • Page 342 NuMicro NUC442/NUC472 Series Technical Reference Manual External Interrupt 0 NMI Source Enable EINT0 0 = External interrupt 0 NMI source Disabled. 1 = External interrupt 0 NMI source Enabled. TAMPER_INT NMI Source Enable TAMPER 0 = Backup register tamper detected interrupt.NMI source Disabled. 1 = Backup register tamper detected interrupt.NMI source Enabled.
  • Page 343 NuMicro NUC442/NUC472 Series Technical Reference Manual NMI source Interrupt Status Register (NMISTS) Register Offset Description Reset Value NMISTS NMI_BA+0x04 NMI source interrupt Status Register 0x0000_0000 Reserved Reserved EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 EINT0 TAMPER Reserved CLKFAIL SRAMFAIL PWRWK Bits Description [31:16]...
  • Page 344 NuMicro NUC442/NUC472 Series Technical Reference Manual TAMPER_INT Interrupt Flag (Read Only) TAMPER 0 = Backup register tamper detected interrupt is deasserted. 1 = Backup register tamper detected interrupt is asserted. RTC Interrupt Flag (Read Only) 0 = RTC interrupt is deasserted. 1 = RTC interrupt is asserted.

  • Page 345: System Control Register Map And Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.2.8 System Control Register Map and Description ® The Cortex -M4 status and operation mode control are managed by System Control Registers. ® Including CPUID, Cortex -M4 interrupt priority and power management can be controlled through these system control register ®...
  • Page 346 NuMicro NUC442/NUC472 Series Technical Reference Manual Interrupt Control State Register (ICSR) Register Offset Description Reset Value ICSR SCS_BA+0xD04 Interrupt Control and State Register 0x0000_0000 NMIPENDSET Reserved PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR Reserved ISRPENDIN ISRPREEMPT Reserved VECTPENDING[5:4] VECTPENDING[3:0] Reserved Reserved VECTACTIVE[5:0] Bits Description NMI Set-Pending Bit Write:...
  • Page 347 NuMicro NUC442/NUC472 Series Technical Reference Manual SysTick Exception Set-Pending Bit Write: 0 = No effect. [26] PENDSTSET 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending. SysTick Exception Clear-Pending Bit Write: 0 = No effect.
  • Page 348 NuMicro NUC442/NUC472 Series Technical Reference Manual Application Interrupt and Reset Control Register (AIRCR) Register Offset Description Reset Value AIRCR SCS_BA+0xD0C Application Interrupt and Reset Control Register 0xFA05_0000 VECTORKEY[15:8] VECTORKEY[7:0] ENDIANNESS Reserved PRIGROUP SYSRESETRE VECTCLKAC Reserved VECTRESET TIVE Bits Description Register Access Key When writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable.

  • Page 349: Table 6.2-4 Priority Grouping

    NuMicro NUC442/NUC472 Series Technical Reference Manual Group Number Group PRIGROUP Binary Point Subpriority Bits Subpriorities Priorities Priority Bits 0b000 bxxxxxxx.y [7:1] 0b001 bxxxxxx.yy [7:2] [1:0] 0b010 bxxxxx.yyy [7:3] [2:0] 0b011 bxxxx.yyyy [7:4] [3;0] 0b100 bxxx.yyyyy [7:5] [4:0] 0b101 bxx.yyyyyy [7:6] [5:0] 0b110 bx.yyyyyyy...
  • Page 350 NuMicro NUC442/NUC472 Series Technical Reference Manual System Control Register (SCR) Register Offset Description Reset Value SCS_BA+0xD10 System Control Register 0x0000_0000 Reserved Reserved Reserved Reserved SEVONPEND Reserved SLEEPDEEP SLEEPONEXIT Reserved Bits Description Reserved [31:5] Reserved. Send Event On Pending 0 = Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded.
  • Page 351 NuMicro NUC442/NUC472 Series Technical Reference Manual System Handler Priority Register 1 (SHPR1) Register Offset Description Reset Value SHPR1 SCS_BA+0xD18 System Handler Priority Register 1 0x0000_0000 PRI_11 Reserved PRI_6 PRI_5 PRI_4 Bits Description [31:24] Reserved Reserved. [23:16] PRI_6 Priority of system handler 6, UsageFault [15:8] PRI_5 Priority of system handler 5, BusFault...
  • Page 352 NuMicro NUC442/NUC472 Series Technical Reference Manual System Handler Priority Register 2 (SHPR2) Register Offset Description Reset Value SHPR2 SCS_BA+0xD1C System Handler Priority Register 2 0x0000_0000 PRI_11 Reserved Reserved Reserved Reserved Bits Description Priority Of System Handler 11 – SVCall PRI_11 [31:30] “0”...
  • Page 353 NuMicro NUC442/NUC472 Series Technical Reference Manual System Handler Priority Register 3 (SHPR3) Register Offset Description Reset Value SHPR3 SCS_BA+0xD20 System Handler Priority Register 3 0x0000_0000 PRI_15 Reserved PRI_14 Reserved Reserved Reserved Bits Description Priority Of System Handler 15 – SysTick [31:30] PRI_15 “0”...

  • Page 354: Clock Controller

    NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Controller 6.3.1 Overview The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode until CPU sets the power-down enable bit (PWR_DOWN_EN) and ®...

  • Page 355: Figure 6.3-1 Clock Generator Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.3-1 Clock Generator Block Diagram May 23, 2014 Page 355 of 1386 Rev.1.05...
  • Page 356 NuMicro NUC442/NUC472 Series Technical Reference Manual HIRC CPUCLK PLL2FOUT LIRC 1/(HCLKDIV+1) HCLK PDMA PLLFOUT ACMP PCLK I2C 0~1 PCLK SPI 0-3 HIRC CLK_CLKSEL0[2:0] TMR 0 PCLK TMR 1 HIRC TMR 2 PLLFOUT TMR 3 HIRC CLK_PLLCTL[19] CLKSEL1[22:20] CLKSEL1[18:16] HIRC CLKSEL1[14:12] CLKSEL1[10:8] HCLK CPUCLK...
  • Page 357 NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.3-2 Clock Generator Global View Diagram May 23, 2014 Page 357 of 1386 Rev.1.05...

  • Page 358: System Clock And Systick Clock

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.3.2 System Clock and SysTick Clock The system clock has 5 clock sources, which were generated from clock generator block. The clock source switch depends on the register HCLKSEL (CLK_CLKSEL0 [2:0]). The block diagram is shown in the following figure.

  • Page 359: Figure 6.3-3 System Clock Switch Procedure

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.3-3 System Clock Switch Procedure ® The clock source of SysTick in Cortex -M4 core can use CPU clock or external clock (SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]).

  • Page 360: Peripherals Clock

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.3.4 Peripherals Clock The peripherals clock had different clock source switch setting, which depends on the different peripheral. Please refer the CLK_CLKSEL1 and CLK_CLKSEL2 register description in 5.3.7. 6.3.5 Power-down Mode Clock When entering Power-down mode, system clocks, some clock sources, and some peripheral clocks are disabled.

  • Page 361: Figure 6.3-6 Block Diagram Of Frequency Divider

    NuMicro NUC442/NUC472 Series Technical Reference Manual DIVIDER_EN (CLK_CLKOCTL[4]) Enable FSEL divide-by-2 counter 16 chained (CLK_CLKOCTL[3:0]) divide-by-2 counter FRQDIV_CLK DIVIDER1* …... (CLK_CLKOCTL[5]) 16 to 1 Figure 6.3-6 Block Diagram of Frequency Divider May 23, 2014 Page 361 of 1386 Rev.1.05...

  • Page 362: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.3.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CLK Base Address: CLK_BA = 0x4000_0200 CLK_PWRCTL CLK_BA+0x00 System Power-down Control Register 0x0000_001X CLK_AHBCLK CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x0000_0005 CLK_APBCLK0 CLK_BA+0x08...

  • Page 363: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.3.8 Register Description Power-down Control Register (CLK_PWRCTL) Except the BIT[6], all the other bits are protected, program these bits need to write “59h”, “16h”, “88h” to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
  • Page 364 NuMicro NUC442/NUC472 Series Technical Reference Manual 1 = Chip enters Power-down mode instant or waits CPU sleep command WFI. Power-Down Mode Wake-Up Interrupt Status Set by “power-down wake-up event”, it indicates that resume from Power-down mode” The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD, RTC or SDHOST wake- PDWKIF up occurred Note1: Write 1 to clear the bit to 0.

  • Page 365: Table 6.3-1 Power-Down Mode Control Table

    NuMicro NUC442/NUC472 Series Technical Reference Manual Register/Instruction PWR_DOWN_EN PDEN Clock Disable Instruction Mode Normal operation All clocks are disabled by control register. Idle mode Only CPU clock is disabled. (CPU enters Sleep mode) Power-down mode Most clocks are disabled except kHz/32.768 kHz;...
  • Page 366 NuMicro NUC442/NUC472 Series Technical Reference Manual AHB Devices Clock Enable Control Register (CLK_AHBCLK) These bits for this register are used to enable/disable clock for system clock, AHB bus devices clock. Register Offset Description Reset Value CLK_AHBCL CLK_BA+0x04 AHB Devices Clock Enable Control Register 0x0000_0005 Reserved Reserved...
  • Page 367 NuMicro NUC442/NUC472 Series Technical Reference Manual 1 = Ethernet Controller engine clock Enabled. USB HOST Controller Clock Enable Bit USBHCKEN 0 = USB HOST engine clock Disabled. 1 = USB HOST engine clock Enabled. EBI Controller Clock Enable Bit EBICKEN 0 = EBI engine clock Disabled.
  • Page 368 NuMicro NUC442/NUC472 Series Technical Reference Manual APB Devices Clock Enable Control Register (CLK_APBCLK0) The bits of this register are used to enable/disable clock for peripheral controller clocks. Register Offset Description Reset Value CLK_APBCL CLK_BA+0x08 APB Devices Clock Enable Control Register 0 0x0000_0001 PS2CKEN I2S1CKEN...
  • Page 369 NuMicro NUC442/NUC472 Series Technical Reference Manual [23:22] Reserved Reserved. UART5 Clock Enable Bit UART5CKEN 0 = UART5 clock Disabled. [21] 1 = UART5 clock Enabled. UART4 Clock Enable Bit UART4CKEN [20] 0 = UART4 clock Disabled. 1 = UART4 clock Enabled. UART3 Clock Enable Bit [19] UART3CKEN...
  • Page 370 NuMicro NUC442/NUC472 Series Technical Reference Manual 1 = I C0 Clock Enabled. Analog Comparator Clock Enable Bit ACMPCKEN 0 = Analog Comparator Clock Disabled. 1 = Analog Comparator Clock Enabled. Frequency Divider Output Clock Enable Bit FDIVCKEN 0 = FDIV Clock Disabled. 1 = FDIV Clock Enabled.
  • Page 371 NuMicro NUC442/NUC472 Series Technical Reference Manual APB Devices Clock Enable Control Register 1 (CLK_APBCLK1) The bits of this register are used to enable/disable clock for peripheral controller clocks. Register Offset Description Reset Value CLK_APBCL CLK_BA+0x0C APB Devices Clock Enable Control Register 1 0x0000_0000 EADCCKEN OPACKEN...
  • Page 372 NuMicro NUC442/NUC472 Series Technical Reference Manual Quadrature Encoder Interface (QEI0) Clock Enable Bit [22] QEI0CKEN 0 = QEI0 clock Disabled. 1 = QEI0 clock Enabled. PWM1_45 Clock Enable Bit [21] PWM1CH45CKEN 0 = PWM1_45 Clock Disabled. 1 = PWM1_45 Clock Enabled. PWM1_23 Clock Enable Bit PWM1CH23CKEN [20]...
  • Page 373 NuMicro NUC442/NUC472 Series Technical Reference Manual 0 = SC0 Clock Disabled. 1 = SC0 Clock Enabled. May 23, 2014 Page 373 of 1386 Rev.1.05...
  • Page 374 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Source Select Control Register 0 (CLK_CLKSEL0) Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x10 Clock Source Select Control Register 0 0x0033_053X Reserved Reserved SDHSEL Reserved ICAPSEL Reserved USBHSEL Reserved PCLKSEL STCLKSEL HCLKSEL Bits Description [31:22] Reserved Reserved.
  • Page 375 NuMicro NUC442/NUC472 Series Technical Reference Manual “88h” to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100. 0 = Clock source from HCLK. 1 = Clock source from HCLK/2. ® Cortex -M4 SysTick Clock Source Selection (Write Protect) If SYST_CSR[2]=0, SysTick uses listed clock source below.
  • Page 376 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Source Select Control Register 1 (CLK_CLKSEL1) Before clock switching, the related clock sources (pre-selected and newly-selected) must be turned Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x14 Clock Source Select Control Register 1 0xB377_77FF WWDTSEL CLKOSEL Reserved...
  • Page 377 NuMicro NUC442/NUC472 Series Technical Reference Manual Others = reserved. Reserved [19] Reserved. TIMER2 Clock Source Selection 000 = Clock source from HXT clock. 001 = Clock source from LXT clock. 010 = Clock source from PCLK. [18:16] TMR2SEL 011 = Clock source from external trigger. 101 = Clock source from LIRC clock.
  • Page 378 NuMicro NUC442/NUC472 Series Technical Reference Manual 11 = Clock source from HIRC clock. Watchdog Timer Clock Source Selection (Write Protect) These bits are protected bit,and programming this needs to write “59h”, “16h”, “88h” to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
  • Page 379 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Source Select Control Register 2 (CLK_CLKSEL2) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x18 Clock Source Select Control Register 2 0x0077_7777 Reserved Reserved...
  • Page 380 NuMicro NUC442/NUC472 Series Technical Reference Manual prescaler. The Engine clock source of PWM1_0 and PWM1_1 is defined by PWM1CH01SEL[2:0] 000 = Clock source from HXT clock. 001 = Clock source from LXT clock. 010 = Clock source from PCLK. 011 = Clock source from HIRC clock. 100 = Clock source from LIRC clock.
  • Page 381 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Source Select Control Register 3 (CLK_CLKSEL3) Before clock switching, the related clock sources (pre-select and new-select) must be turned on. Register Offset Description Reset Value CLK_CLKSEL CLK_BA+0x1C Clock Source Select Control Register 3 0x000F_0FFF Reserved Reserved...
  • Page 382 NuMicro NUC442/NUC472 Series Technical Reference Manual 00 = Clock source from HXT clock. 01 = Clock source from PLL clock. 10 = PCLK. 11 = Clock source from HIRC clock. SC2 Clock Source Selection 00 = Clock source from HXT clock. [5:4] SC2SEL 01 = Clock source from PLL clock.
  • Page 383 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Divider Register 0 (CLK_CLKDIV0) Register Offset Description Reset Value CLK_CLKDIV CLK_BA+0x20 Clock Divider Number Register 0 0x0000_0000 SDHDIV ADCDIV Reserved UARTDIV USBHDIV HCLKDIV Bits Description SDHOST Clock Divide Number From SDHOST Clock Source [31:24] SDHDIV SDHOST clock frequency = (SDHOST clock source frequency) / (SDHDIV + 1).
  • Page 384 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Divider Register 1 (CLK_CLKDIV1) Register Offset Description Reset Value CLK_CLKDIV CLK_BA+0x24 Clock Divider Number Register 1 0x0000_0000 SC3DIV SC2DIV SC1DIV SC0DIV Bits Description SC3 Clock Divide Number From SC3 Clock Source [31:24] SC3DIV SC3 clock frequency = (SC3 clock source frequency ) / (SC3DIV+ 1).
  • Page 385 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Divider Register 2 (CLK_CLKDIV2) Register Offset Description Reset Value CLK_CLKDIV2 CLK_BA+0x28 Clock Divider Number Register 2 0x0000_0000 Reserved Reserved SC5DIV SC4DIV Bits Description [31:16] Reserved Reserved. SC5 Clock Divide Number From SC5 Clock Source [15:8] SC5DIV SC5 clock frequency = (SC5 clock source frequency ) / (SC5DIV + 1).
  • Page 386 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Divider Register 3 (CLK_CLKDIV3) Register Offset Description Reset Value CLK_CLKDIV CLK_BA+0x2C Clock Divider Number Register 3 0x0000_0000 Reserved EMACDIV VSENSEDIV CAPDIV Bits Description [31:24] Reserved Reserved. Ethernet Clock Divide Number Form HCLK (NUC472 Only) [23:16] EMACDIV EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1).
  • Page 387 NuMicro NUC442/NUC472 Series Technical Reference Manual PLL Control Register (CLK_PLLCTL) The PLL reference clock input is from the HXT clock input or from the HIRC. These registers are used to control the PLL output frequency and PLL operation mode. Programming these bits needs to write “59h”, “16h”, “88h” to address 0x4000_0100 to disable register protection.
  • Page 388 NuMicro NUC442/NUC472 Series Technical Reference Manual PLL Input Divider Control Pins [13:9] INDIV Refer to the formulas below the table. PLL Feedback Divider Control Pins [8:0] FBDIV Refer to the formulas below the table. ���� Output Clock Frequency Setting is: FOU = FIN ×...
  • Page 389 NuMicro NUC442/NUC472 Series Technical Reference Manual PLL2 Control Register (CLK_PLL2CTL) The PLL2 reference clock input is from the HXT clock input. The PLL2 is from USB_PHY and enables fixed 20X. The registers are used to control the PLL output frequency and PLL operation mode. Programming these bits needs to write “59h”, “16h”, “88h”...
  • Page 390 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Status Register (CLK_STATUS) These bits of this register are used to monitor if the chip clock source is stable or not, and whether the clock switch is failed. Register Offset Description Reset Value CLK_STATUS CLK_BA+0x50 R/W Clock Status Monitor Register...
  • Page 391 NuMicro NUC442/NUC472 Series Technical Reference Manual 1 = Internal PLL clock is stable. Note: This bit is read only. 32.768 KHz External Low-Speed Crystal Clock(LXT) Source Stable Flag 0 = LXT clock is not stable or disabled. LXTSTB 1 = LXT clock is stabled. Note: This is read only.
  • Page 392 NuMicro NUC442/NUC472 Series Technical Reference Manual Frequency Divider Control Register (CLK_CLKOCTL) Register Offset Description Reset Value CLK_CLKOC CLK_BA+0x60 Frequency Divider Control Register 0x0000_0000 Reserved Reserved Reserved Reserved DIV1EN CLKOEN FSEL Bits Description [31:6] Reserved Reserved. Frequency Divider 1 Enable Bit DIV1EN 0 = Divider output frequency is dependent on FSEL value when FDIVEN is enabled.
  • Page 393 NuMicro NUC442/NUC472 Series Technical Reference Manual Clock Stop Detector Control Register (CLK_CLKDCTL) Register Offset Description Reset Value CLK_CLKDCT CLK_BA+0x70 Clock Fail Detector Control Register 0x0000_0100 Reserved Reserved Reserved IRCFIF IRCFIEN IRCDEN Reserved SYSFIF SYSFIEN SYSFDEN Bits Description [31:11] Reserved Reserved. Internal RC Clock Fail Flag [10] IRCFIF...

  • Page 394: Analog Comparator Controller (Acmp)

    NuMicro NUC442/NUC472 Series Technical Reference Manual Analog Comparator Controller (ACMP) 6.4.1 Overview The NUC442/NUC472 contains three comparators which can be used in a number of different configurations. The comparator output is a logical one when positive input is greater than negative input;...

  • Page 395: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.4.3 Block Diagram ACMP_CTL0[7] ACMP0_P0 ACMP0_P1 ACMP_CTL0[0] ACMP_CTL0[3] ACMP0_P2 from OPA0 ACMP0_P3 ACMP_CTL0[6:5] ACMP0_N ACMP_CTL0[2] INTREF ACMP_CTL0[4] ACMP_CTL1[7] ACMP1_P0 ACMP1_P1 ACMP1_P2 ACMP_CTL1[3] ACMP_CTL1[0] from OPA1 ACMP1_P3 ACMP_CTL1[6:5] ACMP1_N ACMP_CTL1[2] INTREF ACMP_CTL1[4] ACMP_CTL2[7] ACMP2_P0 ACMP2_P1 ACMP2_P2 ACMP_CTL2[0] ACMP_CTL2[3]...

  • Page 396: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.4.4 Functional Description 6.4.4.1 Interrupt Sources The output of comparators are sampled by PCLK and reflected at ACMPO0 (ACMP_STATUS[3]), ACMPO1(ACMP_STATUS [4]) and ACMPO2(ACMP_STATUS [5]). If ACMPIE (ACMP_CTLx[1]) is set to 1, the comparator interrupt will be enabled. As the output state of comparator is changed, comparator interrupt will...

  • Page 397: Comparator Reference Voltage (Crv)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.4.5 Comparator Reference Voltage (CRV) 6.4.5.1 Introduction The comparator reference voltage (CRV) module is responsible for generating reference voltage for comparators. The CRV module consists of resisters ladder and analog switch. User can set the CRV output voltage by setting the CRVCTL[3:0] (ACMP_VREF[3:0]) and select the reference voltage to comparator by setting NEGSEL (ACMP_CTLx[4]) and IREFSEL (ACMP_VREF[7]).

  • Page 398: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.4.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value ACMP Base Address: ACMP_BA = 0x4004_5000 ACMP_CTL0 ACMP_BA+0x00 Analog Comparator 0 Control Register 0x0000_0000 ACMP_CTL1 ACMP_BA+0x04 Analog Comparator 1 Control Register 0x0000_0000...

  • Page 399: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.4.7 Register Description Analog Comparator 0 Control Register (ACMP_CR0) Register Offset Description Reset Value ACMP_CTL0 ACMP_BA+0x00 Analog Comparator 0 Control Register 0x0000_0000 Reserved Reserved Reserved POSSEL NEGSEL ACMPOINV HYSEN ACMPIE ACMPEN Bits Description [31:8] Reserved Reserved.
  • Page 400 NuMicro NUC442/NUC472 Series Technical Reference Manual Note: The comparator output needs to wait 2 us stable time after ACMPEN is set. May 23, 2014 Page 400 of 1386 Rev.1.05...
  • Page 401 NuMicro NUC442/NUC472 Series Technical Reference Manual Analog Comparator 1 Control Register (ACMP_CR1) Register Offset Description Reset Value ACMP_CTL1 ACMP_BA+0x04 Analog Comparator 1 Control Register 0x0000_0000 Reserved Reserved Reserved POSSEL NEGSEL ACMPOINV HYSEN ACMPIE ACMPEN Bits Description [31:8] Reserved Reserved. Comparator 1 Positive Input Selection 000= Input from ACMP1_P0.
  • Page 402 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description The comparator output needs to wait 2 us stable time after ACMPEN is set. May 23, 2014 Page 402 of 1386 Rev.1.05...
  • Page 403 NuMicro NUC442/NUC472 Series Technical Reference Manual Analog Comparator 2 Control Register (ACMP_CR2) Register Offset Description Reset Value ACMP_CTL2 ACMP_BA+0x08 Analog Comparator 2 Control Register 0x0000_0000 Reserved Reserved Reserved POSSEL NEGSEL ACMPOINV HYSEN ACMPIE ACMPEN Bits Description [31:8] Reserved Reserved. Comparator 2 Positive Input Selection 000= Input from ACMP2_P0.
  • Page 404 NuMicro NUC442/NUC472 Series Technical Reference Manual Analog Comparator Status Register (ACMP_STATUS) Register Offset Description Reset Value ACMP_STAT ACMP_BA+0x0C Analog Comparator Status Register 0x0000_0000 Reserved Reserved Reserved Reserved ACMPO2 ACMPO1 ACMPO0 ACMPIF2 ACMPIF1 ACMPIF0 Bits Description [31:6] Reserved Reserved. Comparator 2 Output ACMPO2 Synchronized to the APB clock to allow reading by software.
  • Page 405 NuMicro NUC442/NUC472 Series Technical Reference Manual ACMP Reference Voltage Control Register (ACMP_VREF) Register Offset Description Reset Value ACMP_VREF ACMP_BA+0x10 Analog Comparator Reference Voltage Control Register 0x0000_0000 Reserved Reserved Reserved IREFSEL CRVSSEL Reserved CRVCTL Bits Description [31:8] Reserved Reserved. Internal Reference Selection IREFSEL 0 = Band-gap voltage is selected as internal reference.

  • Page 406: Analog-To-Digital Converter (Adc)

    NuMicro NUC442/NUC472 Series Technical Reference Manual Analog-to-Digital Converter (ADC) 6.5.1 Overview The NUC442/NUC472 contains one 12-bit successive approximation analog-to-digital converters (SAR A/D converter) with 12 external input channels. The A/D converter supports three operation modes －Single Mode, Single-cycle Scan Mode and Continuous Scan Mode. The A/D converters can be started by software, external pin (STADC) or PWM trigger.

  • Page 407: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.5.3 Block Diagram VALID & OVERRUN PDMA STADC request Digital Control Logics ADC_INT & PWM trigger ADCIF ADC Clock Generator RESULT[11:0] Successive INT_VREF Approximations Register VREF 12-bit DAC ADC0_CH0 ADC0_CH1 Analog Control Logics ADC0_CH11 Comparator Sample and Hold Analog Macro...

  • Page 408: Figure 6.5-2 Adc Clock Control

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.5.4.1 ADC Clock Generator The maximum sampling rate is up to 800 kSPS. The ADC engine has four clock sources selected by 2-bit EADCSEL (CLK_CLKDIV1[3:2]), the ADC clock frequency is divided by an 8-bit prescaler with the formula: The ADC clock frequency = (ADC clock source frequency) / (ADCDIV+1);...

  • Page 409: Figure 6.5-3 Single Mode Conversion Timing Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual ADC_CLK SWTRG sample ADC_DATx RESULT[11:0] Figure 6.5-3 Single Mode Conversion Timing Diagram 6.5.4.3 Single-Cycle Scan Mode In Single-cycle Scan Mode, A/D conversion will sample and convert the specified channels once in the sequence from the smallest number enabled channel to the largest number enabled channel.

  • Page 410: Figure 6.5-4 Single-Cycle Scan On Enabled Channels Timing Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual SWTRG chsel[3:0] 0x0000 0x0010 0x0011 0x0111 sample SAR[11:0] ADC_DAT0 ADC_DAT2 ADC_DAT3 ADC_DAT7 Single-cycle scan on channel 0, 2, 3 and 7 (CHEN[11:0] = 000010001101b) Figure 6.5-4 Single-Cycle Scan on Enabled Channels Timing Diagram 6.5.4.4 Continuous Scan Mode In continuous scan mode, A/D conversion is performed sequentially on the specified channels that enabled by CHEN (ADCHER[11:0]) bits.

  • Page 411: Figure 6.5-5 Continuous Scan On Enabled Channels Timing Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual SWTRG Software clear SWTRG chsel[3:0] 0x0000 0x0010 0x0011 0x0111 0x0000 0x0010 0x0011 0x0111 0x0000 sample ADC_DAT0 ADC_DAT2 ADC_DAT3 ADC_DAT7 Continuous scan on channel 0, 2, 3 and 7 (CHEN[11:0] = 000010001101b) Figure 6.5-5 Continuous Scan on Enabled Channels Timing Diagram 6.5.4.5 External hardware trigger ADC has two external hardware trigger sources: external pin (STADC) trigger and PWM trigger.

  • Page 412: Figure 6.5-6 A/D Conversion Result Monitor Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual than specified value or greater than (equal to) value specified in CMPDAT (ADC_CMPx[27:16]). When the conversion of the channel specified by CMPCH (ADC_CMPx[6:3]) is completed, the comparing action will be triggered one time automatically. When the compare result meets the setting, compare match counter will increase 1, otherwise, the compare match counter will be clear to 0.
  • Page 413 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.5.4.10 Peripheral DMA Request A/D controller supports PDMA transfer for A/D conversion result of channel 0 to channel 11. When A/D conversion is finished, the conversion result will be loaded into ADC_DAT register and VALID (ADC_DATx[17]) bit will be set to 1.

  • Page 414: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.5.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value ADC Base Address: ADC_BA = 0x4004_3000 ADC_DAT0 ADC_BA+0x00 ADC Data Register 0 0x0000_0000 ADC_DAT1 ADC_BA+0x04 ADC Data Register 1 0x0000_0000...

  • Page 415: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.5.6 Register Description ADC Data Registers (ADC_DAT0 ~ ADC_DAT 13) Register Offset Description Reset Value ADC_DAT0 ADC_BA+0x00 ADC Data Register 0 0x0000_0000 ADC_DAT1 ADC_BA+0x04 ADC Data Register 1 0x0000_0000 ADC_DAT2 ADC_BA+0x08 ADC Data Register 2 0x0000_0000 ADC_DAT3 ADC_BA+0x0C...

  • Page 416: Figure 6.5-8 Conversion Result Mapping Diagram Of Single-End Input

    NuMicro NUC442/NUC472 Series Technical Reference Manual Valid Flag (Read Only) 0 = Data in RESULT (ADC_DATx[15:0]) bits is not valid. VALID [17] 1 = Data in RESULT (ADC_DATx[15:0]) bits is valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.

  • Page 417: Figure 6.5-9 Conversion Result Mapping Diagram Of Differential Input

    NuMicro NUC442/NUC472 Series Technical Reference Manual ADC result in ADC result in RESULT[11:0] RESULT[15:0] (DMOF = 0) (DMOF = 1) 1111_1111_1111 0000_0111_1111_1111 1111_1111_1110 0000_0111_1111_1110 1111_1111_1101 0000_0111_1111_1101 1000_0000_0001 0000_0000_0000_0001 1000_0000_0000 0000_0000_0000_0000 0111_1111_1111 1111_1111_1111_1111 1 LSB = Vref/4096 1 LSB = Vref/4096 0000_0000_0010 1111_1000_0000_0010 0000_0000_0001...
  • Page 418 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC Control Register (ADC_CTL) Register Offset Description Reset Value ADC_CTL ADC_BA+0x40 ADC Control Register 0x0000_0000 DMOF Reserved PWMTRGDLY Reserved SWTRG DIFFEN PDMAEN HWTRGEN HWTRGCOND HWTRGSEL OPMODE ADCIEN ADCEN Bits Description ADC Differential Input Mode Output Format 0 = A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with [31] DMOF...
  • Page 419 NuMicro NUC442/NUC472 Series Technical Reference Manual Differential Input Mode Enable Bit 0 = Single-end analog input mode. 1 = Differential analog input mode. The A/D analog input ADC0_CH0/ADC0_CH1 consists of a differential pair. So as ADC0_CH2/ADC0_CH3, ADC0_CH4/ADC0_CH5, ADC0_CH6/ADC0_CH7, ADC0_CH8/ADC0_CH9 and ADC0_CH10/ADC0_CH11. The even channel defines as [10] DIFFEN plus analog input voltage (V...
  • Page 420 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC Operation Mode 00 = Single conversion. 01 = Reserved. [3:2] OPMODE 10 = Single-cycle scan. 11 = Continuous scan. When changing the operation mode, software should disable SWTRG (ADC_CTL[11]) bit firstly. ADC Interrupt Enable Bit 0 = ADC interrupt function Disabled.
  • Page 421 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC Channel Enable Control Register (ADC_CHEN) Register Offset Description Reset Value ADC_CHEN ADC_BA+0x44 ADC Channel Enable Control Register 0x0000_0000 Reserved Reserved ADTSEN ADBGEN Reserved CHEN[11:8] CHEN[7:0] Bits Description [31:18] Reserved Reserved. Internal Temperature Sensor Selection 0 = Internal temperature sensor is not selected to be the analog input source of ADC.
  • Page 422 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC Compare Register 0/1 (ADC_CMP0/1) Register Offset Description Reset Value ADC_CMP0 ADC_BA+0x48 ADC Compare Register 0 0x0000_0000 ADC_CMP1 ADC_BA+0x4C ADC Compare Register 1 0x0000_0000 Reserved CMPDAT[11:8] CMPDAT[7:0] Reserved CMPMCNT Reserved CMPCH CMPCOND ADCMPIE ADCMPEN Bits Description [31:28]...
  • Page 423 NuMicro NUC442/NUC472 Series Technical Reference Manual Compare Channel Selection 0000 = Channel 0 conversion result is selected to be compared. 0001 = Channel 1 conversion result is selected to be compared. 0010 = Channel 2 conversion result is selected to be compared. 0011 = Channel 3 conversion result is selected to be compared.
  • Page 424 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC Status Register 0 (ADC_STATUS0) Register Offset Description Reset Value ADC_STATUS ADC_BA+0x50 ADC Status Register 0 0x0000_0000 Reserved Reserved Reserved CHANNEL BUSY ADCMPF1 ADCMPF0 ADIF Bits Description [31:8] Reserved Reserved. Current Conversion Channel (Read Only) [7:4] CHANNEL This field reflects the current conversion channel when BUSY (ADC_STATUS0[3]) = 1.
  • Page 425 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC Status Register 1 (ADC_STATUS1) Register Offset Description Reset Value ADC_STATUS ADC_BA+0x54 ADC Status Register 1 0x0000_0000 Reserved OV[13:8] OV[7:0] Reserved VALID[13:8] VALID[7:0] Bits Description [31:30] Reserved Reserved. Overrun Flag (Read Only) [29:16] It is a mirror to OV (ADC_DATx[16]) bit. [15:14] Reserved Reserved.

  • Page 426: 12-Bit Analog-To-Digital Converter (Enhanced Adc)

    NuMicro NUC442/NUC472 Series Technical Reference Manual ADC PDMA Current Transfer Data Register (ADC_CURDAT) Register Offset R/W Description Reset Value ADC_CURDAT ADC_BA+0x60 ADC PDMA Current Transfer Data Register 0x0000_0000 Reserved Reserved CURDAT[17:16] CURDAT[15:8] CURDAT[7:0] Bits Description [31:18] Reserved Reserved. ADC PDMA Current Transfer Data Biit (Read Only) [17:0] CURDAT When PDMA transferring, read this register can monitor current PDMA transfer data.
  • Page 427 NuMicro NUC442/NUC472 Series Technical Reference Manual  Supports conversion rate 400 kSPS while VREF is between 2.5V~5.5V and up to 800 kSPS while VREF is between 4.5V~5.5V in single-end mode.  Double buffer for channel 0~3 of each ADC0 and ADC1 ...

  • Page 428: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.6.3 Block Diagram VREF 12-bit DAC Analog Control Logics ADC0_CH0 Comparator ADC0_CH7 VTEMP Successive AVSS Approximations Register Sample and Hold A chselA[3:0] SAR[11:0] Analog Macro A/D SAMPLE modeul 00 Result Register (EADC_AD0DAT0) Digatal Control Logics A/D SAMPLE module &...

  • Page 429: Operation Procedure

    NuMicro NUC442/NUC472 Series Technical Reference Manual VREF 12-bit DAC Analog Control Logics Comparator ADC1_CH0 ADC1_CH1 ADC1_CH7 Successive Approximations Register Sample and Hold B chselB[3:0] SAR[11:0] Analog Macro A/D SAMPLE module 10 Result Register (EADC_AD1DAT0) Digatal Control Logics A/D SAMPLE module &...
  • Page 430 NuMicro NUC442/NUC472 Series Technical Reference Manual control modules, and the A/D converter operates by successive approximation with 12-bit resolution. The A/D operation is based on SAMPLE00~SAMPLE07 (ADC0 converter) and SAMPLE10~ SAMPLE17 (ADC1 converter) control logic modules, each of them has its configuration to decide which trigger source to starts the conversion, which channel to convert.

  • Page 431: Figure 6.6-4 Single Sampling Mode Conversion Timing Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual ADC_CLK SWTRGx sampling EADC_AD0DATx EADC_AD0DATx [11:0] [11:0] ADIFn Figure 6.6-4 Single Sampling Mode Conversion Timing Diagram SAMPLE module 03, SAMPLE module 13 SAMPLE module 00, SAMPLE module 10 Disable hardware Trigger ADC STADC pin signal *¹...

  • Page 432: Figure 6.6-6 Sample04~Sample07 And Sample14~Sample17 Control Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual SAMPLE module 07, SAMPLE moduel 17 SAMPLE module 04, SAMPLE module 14 CHSEL4[2:0] Disable hardware Trigger ADC STADC pin signal SAMPLE SWTRG4 Software trigger *¹ module x4 ADINT0 interrupt EOC pulse *¹ Sample and Result ADINT1 interrupt EOC pulse Priority...

  • Page 433: Figure 6.6-7 Sample Module Conversion Priority Arbitrator Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual converter, SAMPLE10~SAMPLE17 priority group is for ADC1 converter. SAMPLE module with lower number has higher priority than the higher number SAMPLE module, if two SAMPLE modules are triggered at the same time, the SAMPLE module with lower number will start to convert ADC first.

  • Page 434: Figure 6.6-8 Pwm-Triggered Adc Start Conversion

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.6-8 PWM-triggered ADC Start Conversion May 23, 2014 Page 434 of 1386 Rev.1.05...

  • Page 435: Figure 6.6-9 Sample Module A/D Eoc Signal For Adint0 Interrupt

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.6.4.6 ADC SAMPLE End of Conversion Interrupt Operation There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address configured select specific SAMPLE module pulse (SAMPLE00~SAMPLE07, SAMPLE10~SAMPLE17 End of conversion pulses) as its interrupt trigger source.

  • Page 436: Figure 6.6-10 Sample Module A/D Eoc Signal For Adint1 Interrupt

    NuMicro NUC442/NUC472 Series Technical Reference Manual ADINT1 ADFOV1 SAMPLE module 00 EOC IESPL00 ADIF1 ADC Interrupt ADINT1 control Logic SAMPLE module 17 EOC IESPL17 ADIE1 Figure 6.6-10 SAMPLE module A/D EOC Signal for ADINT1 Interrupt ADINT2 ADFOV2 SAMPLE module 00 EOC IESPL00 ADIF2 ADC Interrupt...

  • Page 437: Figure 6.6-12 Sample Module A/D Eoc Signal For Adint3 Interrupt

    NuMicro NUC442/NUC472 Series Technical Reference Manual ADINT3 ADFOV3 SAMPLE module 00 EOC IESPL00 ADIF3 ADC Interrupt ADINT3 control Logic SAMPLE module 17 EOC IESPL17 ADIE3 Figure 6.6-12 SAMPLE module A/D EOC Signal for ADINT3 Interrupt 6.6.4.7 Input Sampling and A/D Conversion Time The A/D converter sample the analog input when A/D conversion start delay time (Td) has passed after SWTRGx (EADC_SWTRG [15:0]) bit is set to 1, then start conversion.

  • Page 438: Figure 6.6-13 Conversion Start Delay Timing Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual A/D conversion time A/D conversion start delay time (Td) Analog input sampling time PCLK Synchronous to ADC clock delay 1 ADC clock up to 1 ADC clcok PWRITE SWTRGx A/D start First ADC clock Analog input sampling signal A/D converter...

  • Page 439: Figure 6.6-14 A/D Extend Sampling Timing Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual Extend Sampling Time A/D Conversion (N ADC clocks) (20 ADC clocks) A/D clock A/D converter start A/D converter channel select A/D converter Hold Sample Hold Sample Sample/Hold A/D converter finish Figure 6.6-14 A/D Extend Sampling Timing Diagram 6.6.4.9 Conversion Result Monitor by Compare Mode The NUC442/NUC472 controller provides two sets of compare register EADC_CMP0 and 1 to monitor...

  • Page 440: Figure 6.6-16 A/D Controller Interrupts

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.6.4.10 Interrupt Sources The A/D converter generates a conversion end ADIFn (EADC_STATUS1 [3:0]) bit register upon the end of specific SAMPLE module A/D conversion. If ADIEn (EADC_CTL [5:2]) bit is set then conversion end interrupt request ADINTn is generated. ADIF0 ADINT0 ADIE0...

  • Page 441: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.6.5 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset Description Reset Value EADC Base Address: EADC_BA = 0x4004_4000 EADC_AD0DAT0 EADC_BA+0x00 A/D Data Register 0 for SAMPLE00 0x0000_0000 EADC_AD0DAT1...
  • Page 442 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value EADC Base Address: EADC_BA = 0x4004_4000 EADC_AD0SPCTL4 EADC_BA+0x68 A/D SAMPLE04 Control Register 0x0000_0000 EADC_AD0SPCTL5 EADC_BA+0x6C A/D SAMPLE05 Control Register 0x0000_0000 EADC_AD0SPCTL6 EADC_BA+0x70 A/D SAMPLE06 Control Register 0x0000_0000 EADC_AD0SPCTL7 EADC_BA+0x74 A/D SAMPLE07 Control Register 0x0000_0000 EADC_AD1SPCTL0 EADC_BA+0x78...
  • Page 443 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value EADC Base Address: EADC_BA = 0x4004_4000 EADC_INTSRC0 EADC_BA+0x134 R/W A/D Interrupt 0 Source Enable Control Register 0x0000_0000 EADC_INTSRC1 EADC_BA+0x138 R/W A/D Interrupt 1 Source Enable Control Register 0x0000_0000 EADC_INTSRC2 EADC_BA+0x13C R/W A/D Interrupt 2 Source Enable Control Register 0x0000_0000...

  • Page 444: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.6.6 Register Description A/D Data Registers (EADC_AD0DAT0~EADC_AD0DAT7, EADC_AD1DAT0~EADC_AD1DAT7) Register Offset Description Reset Value EADC_AD0 EADC_BA+0x00 A/D Data Register 0 for SAMPLE00 0x0000_0000 DAT0 EADC_AD0 EADC_BA+0x04 A/D Data Register 1 for SAMPLE01 0x0000_0000 DAT1 EADC_AD0 EADC_BA+0x08 A/D Data Register 2 for SAMPLE02 0x0000_0000...
  • Page 445 NuMicro NUC442/NUC472 Series Technical Reference Manual RESULT[7:0] May 23, 2014 Page 445 of 1386 Rev.1.05...
  • Page 446 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description [31:18] Reserved Reserved. Valid Flag 0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid. 1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid. VALID [17] This bit is set to 1 when corresponding SAMPLE module channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
  • Page 447 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D Control Register (EADC_CTL) Register Offset Description Reset Value EADC_CTL EADC_BA+0x40 A/D Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ADCIEN3 ADCIEN2 ADCIEN1 ADCIEN0 ADCRST ADCEN Bits Description [31:6] Reserved Reserved. Specific SAMPLE MODULE A/D ADINT3 Interrupt Enable Bit 0 = Specific SAMPLE MODULE A/D ADINT3 interrupt function Disabled.
  • Page 448 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description ADC0, ADC1 A/D Converter Control Circuits Reset 0 = No effect. ADCRST 1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. The ADCRST (EADC_CTL [1]) bit remains 1 during ADC reset, when ADC reset end, the ADCRST (EADC_CTL [1]) bit is automatically cleared to 0.
  • Page 449 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D SAMPLE MODULE Software Start Register (EADC_SWTRG) Register Offset Description Reset Value EADC_SWTRG EADC_BA+0x48 A/D SAMPLE MODULE Software Start Register 0x0000_0000 Reserved Reserved SWTRG[15:8] SWTRG[7:0] Bits Description [31:16] Reserved Reserved. A/D SAMPLE17~SAMPLE10 Software Force To Start ADC Conversion 0 = No effect.
  • Page 450 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D SAMPLE MODULE Start of Conversion Pending Flag Register (EADC_PENDSTS) Register Offset R/W Description Reset Value EADC_PENDST EADC_BA+0x4C A/D Start of Conversion Pending Flag Register 0x0000_0000 Reserved Reserved STPF[15:8] STPF[7:0] Bits Description [31:16] Reserved Reserved.
  • Page 451 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D Interrupt Flag Overrun Register (EADC_ADIFOV) Register Offset Description Reset Value EADC_ADIFOV EADC_BA+0x50 A/D ADINT3~0 Interrupt Flag Overrun Register 0x0000_0000 Reserved Reserved Reserved Reserved ADFOV[3:0] Bits Description [31:4] Reserved Reserved. A/D ADINT3 Interrupt Flag Overrun 0 = ADINT3 interrupt flag is not overwritten to 1.
  • Page 452 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D SAMPLE MODULE Overrun Flag Register (EADC_OVSTS) Register Offset Description Reset Value A/D SAMPLE MODULE Start of Conversion Overrun Flag EADC_OVSTS EADC_BA+0x54 0x0000_0000 Register Reserved Reserved SPOVF[15:8] SPOVF[7:0] Bits Description [31:16] Reserved Reserved. A/D SAMPLE17~SAMPLE10 Start Of Conversion Overrun Flag 0 = No SAMPLE1x event overrun.
  • Page 453 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D SAMPLEn0~SAMPLEn3 Control Registers (EADC_AD0SPCTL0 ~ EADC_AD0SPCTL3, EADC_AD1SPCTL0 ~ EADC_AD1SPCTL3) Register Offset Description Reset Value EADC_AD0SPC EADC_BA+0x58 A/D SAMPLE00 Control Register 0x0000_0000 EADC_AD0SPC EADC_BA+0x5C A/D SAMPLE01 Control Register 0x0000_0000 EADC_AD0SPC EADC_BA+0x60 A/D SAMPLE02 Control Register 0x0000_0000 EADC_AD0SPC EADC_BA+0x64...
  • Page 454 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection Trigger delay clock frequency: 00 = ADC_CLK/1. [17:16] TRGDLYDIV[1:0] 01 = ADC_CLK/2. 10 = ADC_CLK/4. 11 = ADC_CLK/16. A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time [15:8] TRGDLYCNT[7:0] Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
  • Page 455 NuMicro NUC442/NUC472 Series Technical Reference Manual SAMPLEn4~7 Control Registers (EADC_AD0SPCTL4 EADC_AD0SPCTL7, EADC_AD1SPCTL4 ~ EADC_AD1SPCTL7) Register Offset Description Reset Value EADC_AD0SPCTL4 EADC_BA+0x68 A/D SAMPLE04 Control Register 0x0000_0000 EADC_AD0SPCTL5 EADC_BA+0x6C A/D SAMPLE05 Control Register 0x0000_0000 EADC_AD0SPCTL6 EADC_BA+0x70 A/D SAMPLE06 Control Register 0x0000_0000 EADC_AD0SPCTL7 EADC_BA+0x74 A/D SAMPLE07 Control Register 0x0000_0000...
  • Page 456 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection 000 = Disable hardware trigger. 001 = External pin (STADC) trigger. 010 = ADC ADINT0 interrupt EOC pulse trigger. [6:4] TRGSEL 011 = ADC ADINT1 interrupt EOC pulse trigger. 100 = Timer0 overflow pulse trigger.
  • Page 457 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D Simultaneous Sampling Mode Select Register (EADC_SIMUSEL) Register Offset Description Reset Value A/D SAMPLE MODULE Simultaneous Sampling Mode EADC_SIMUSEL EADC_BA+0xA4 0x0000_0000 Select Register Reserved Reserved Reserved SIMUSEL7 SIMUSEL6 SIMUSEL5 SIMUSEL4 SIMUSEL3 SIMUSEL2 SIMUSEL1 SIMUSEL0 Bits Description [31:8]...
  • Page 458 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description A/D SAMPLE04, SAMPLE14 Simultaneous Sampling Mode Selection 0 = SAMPLE04, SAMPLE14 are in single sampling mode, both SAMPLE04 and SAMPLE14’s 3 bits of CHSEL define the ADC channels to be converted. 1 = SAMPLE04, SAMPLE14 are in simultaneous sampling mode, Only SAMPLE04 can SIMUSEL4 trigger the both ADC conversions of SAMPLE04 and SAMPLE14, SAMPLE14 trigger select TRGSEL is ignored.
  • Page 459 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D Result Compare Register 0/1 (EADC_CMP0/1) Register Offset Description Reset Value EADC_CMP0 EADC_BA+0xA8 A/D Result Compare Register 0 0x0000_0000 EADC_CMP1 EADC_BA+0xAC A/D Result Compare Register 1 0x0000_0000 Reserved CMPDAT[11:8] CMPDAT[7:0] Reserved CMPMCNT Reserved CMPSPL CMPCOND ADCMPIE ADCMPEN...
  • Page 460 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description Compare Condition 0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one. 1= Set the compare condition as that when a 12-bit A/D conversion result is greater or CMPCOND equal to the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one.
  • Page 461 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D Status Register 0 (EADC_STATUS0) Register Offset Description Reset Value EADC_STATUS0 EADC_BA+0xB0 A/D Status Register 0 0x0000_0000 OV[15:8] OV[7:0] VALID[15:8] VALID[7:0] Bits Description ADDR17~ADDR10 Overrun Flag (Read Only) [31:24] OV[15:8] It is a mirror to OV bit in SAMPLE 1 A/D result data register EADC_AD0DAT1x. Note: x = 0~7.
  • Page 462 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D Status Register 1 (EADC_STATUS1) Register Offset Description Reset Value EADC_STATUS1 EADC_BA+0xB4 A/D Status Register 1 0x0000_0000 Reserved AVALID STOVF ADOVIF CHANNEL1 Reserved BUSY1 CHANNEL0 Reserved BUSY0 ADCMPF1 ADCMPF0 ADCMPO1 ADCMPO0 ADIF3 ADIF2 ADIF1 ADIF0 Bits Description...
  • Page 463 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description Current Conversion Channel (Read Only) This filed reflects ADC1 current conversion channel when BUSY1 (EADC_STATUS1 [16]) = 1. When BUSY1 (EADC_STATUS1 [16]) = 0, it shows the last converted channel. 0000 = ADC1_CH0. 0001 = ADC1_CH1.
  • Page 464 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description ADC Compare 0 Flag When the specific SAMPLE MODULE A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. ADCMPF0 0 = Conversion result in ADDR does not meet EADC_CMP0 setting. 1 = Conversion result in ADDR meets EADC_CMP0 setting.
  • Page 465 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D Timing Control Register (EADC_EXTSMPT) Register Offset Description Reset Value EADC_EXTSMPT EADC_BA+0xB8 A/D Timing Control Register 0x0000_0000 Reserved EXTSMPT1 Reserved EXTSMPT0 Bits Description [31:24] Reserved Reserved. ADC1 Extend Sampling Time When A/D converting at high conversion rate, the sampling time of analog input voltage [23:16] EXTSMPT1 may not enough if input channel loading is heavy, SW can extend A/D sampling time...
  • Page 466 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D Double Data Registers for A/D Data Registers (EADC_AD0DAT0~EADC_AD0DAT3, EADC_AD1DAT0~EADC_AD1DAT3) Register Offset Description Reset Value EADC_AD0DDAT0 EADC_BA+0x100 A/D double Data Register 0 for SAMPLE00 0x0000_0000 EADC_AD0DDAT1 EADC_BA+0x104 A/D double Data Register 1 for SAMPLE01 0x0000_0000 EADC_AD0DDAT2 EADC_BA+0x108 A/D double Data Register 2 for SAMPLE02...
  • Page 467 NuMicro NUC442/NUC472 Series Technical Reference Manual A/D Double Buffer Mode select (EADC_DBMEN) Register Offset Description Reset Value EADC_DBMEN EADC_BA+0x130 A/D Double Buffer Mode select 0x0000_0000 Reserved Reserved Reserved AD1DBM3 AD1DBM2 AD1DBM1 AD1DBM0 Reserved AD0DBM3 AD0DBM2 AD0DBM1 AD0DBM0 Bits Description [31:12] Reserved Reserved.
  • Page 468 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description Double Buffer Mode For SAMPLE00 AD0DBM0 0 = SAMPLE00 has one sample result register. (default). 1 =SAMPLE00 has two sample result registers. May 23, 2014 Page 468 of 1386 Rev.1.05...
  • Page 469 NuMicro NUC442/NUC472 Series Technical Reference Manual ADC interrupt Source Enable Control Register (EADC_INTSRC0 ~ EADC_INTSRC3) Register Offset Description Reset Value EADC_INTSRC0 EADC_BA+0x134 A/D Interrupt 0 Source Enable Control Register 0x0000_0000 EADC_INTSRC1 EADC_BA+0x138 A/D Interrupt 1 Source Enable Control Register 0x0000_0000 EADC_INTSRC2 EADC_BA+0x13C A/D Interrupt 2 Source Enable Control Register...
  • Page 470 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description SAMPLE11 Interrupt Mask Enable Bit AD1SPIE1 0 = SAMPLE11 interrupt mask Disabled. 1 = SAMPLE11 interrupt mask Enabled. SAMPLE10 Interrupt Mask Enable Bit AD1SPIE0 0 = SAMPLE10 interrupt mask Disabled. 1 = SAMPLE10 interrupt mask Enabled. SAMPLE07 Interrupt Mask Enable Bit AD0SPIE7 0 = SAMPLE07 interrupt mask Disabled.
  • Page 471 NuMicro NUC442/NUC472 Series Technical Reference Manual SAMPLE MODULE Trigger Condition Enable Control Register (EADC_AD0TRGEN0 ~ EADC_AD0TRGEN3, EADC_AD1TRGEN0 ~ EADC_AD1TRGEN3) Register Offset Description Reset Value EADC_AD0TRGEN0 EADC_BA+0x144 A/D trigger condition for SAMPLE00 0x0000_0000 EADC_AD0TRGEN1 EADC_BA+0x148 A/D trigger condition for SAMPLE01 0x0000_0000 EADC_AD0TRGEN2 EADC_BA+0x14C A/D trigger condition for SAMPLE02 0x0000_0000...
  • Page 472 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description PWM0_CH0 Center Trigger Enable Bit PWM00CEN 0 = Disabled. [27] 1 = Enabled. PWM0_CH0 Period Trigger Enable Bit PWM00PEN [26] 0 = Disabled. 1 = Enabled. PWM0_CH0 Falling Edge Trigger Enable Bit [25] PWM00FEN 0 = Disabled.
  • Page 473 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description EPWM1_CH0 Period Trigger Enable Bit EPWM10PEN 0 = Disabled. [14] 1 = Enabled. EPWM1_CH0 Falling Edge Trigger Enable Bit EPWM10FEN [13] 0 = Disabled. 1 = Enabled. EPWM1_CH0 Rising Edge Trigger Enable Bit [12] EPWM10REN 0 = Disabled.
  • Page 474 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description EPWM0_CH0 Falling Edge Trigger Enable Bit EPWM00FEN 0 = Disabled. 1 = Enabled. EPWM0_CH0 Rising Edge Trigger Enable Bit EPWM00REN 0 = Disabled. 1 = Enabled. May 23, 2014 Page 474 of 1386 Rev.1.05...

  • Page 475: Controller Area Network (Can)

    NuMicro NUC442/NUC472 Series Technical Reference Manual Controller Area Network (CAN) 6.7.1 Overview The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and Module Interface (Refer to Figure 6.7-1). The CAN Core performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s.

  • Page 476: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.7.3 Block Diagram The C_CAN interfaces with the AMBA APB bus. The following figure shows the block diagram of the C_CAN.  CAN Core CAN Protocol Controller and Rx/Tx Shift Register for serial/parallel conversion of messages. ...

  • Page 477: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.7.4 Functional Description 6.7.4.1 Software Initialization The software initialization is started by setting the Init bit in the CAN Control Register, either by a software or a hardware reset, or by going to Bus_Off state. While the Init bit is set, all messages transfer to and from the CAN bus are stopped and the status of the CAN_TX output pin is recessive (HIGH).

  • Page 478: Test Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.7.4.3 Disabled Automatic Retransmission In accordance with the CAN Specification (see ISO11898, 6.3.3 Recovery Management), the C_CAN provides means for automatic retransmission of frames that have lost arbitration or have been disturbed by errors during transmission. The frame transmission service will not be confirmed to the user before the transmission is successfully completed.

  • Page 479: Figure 6.7-3 Can Core In Loop Back Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.7.5.2 Loop Back Mode The CAN Core can be set in Loop Back Mode by programming the Test Register bit LBack to one. In Loop Back Mode, the CAN Core treats its own transmitted messages as received messages and stores them in a Receive Buffer (if they pass acceptance filtering).Figure 5-78 shows the connection of signals, CAN_TX and CAN_RX, to the CAN Core in Loop Back Mode.

  • Page 480: Can Communications

    NuMicro NUC442/NUC472 Series Technical Reference Manual The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1 Registers is requested by writing the Busy bit of the IF1 Command Request Register to one. The IF1 Registers are locked while the Busy bit is set. The Busy bit indicates that the transmission is pending.
  • Page 481 NuMicro NUC442/NUC472 Series Technical Reference Manual data flow of the C_CAN. Received messages that pass the acceptance filtering are stored into the Message RAM, messages with pending transmission request are loaded into the CAN_Core’s Shift Register and are transmitted through the CAN bus. The application software reads received messages and updates messages to be transmitted through the IFn Interface Registers.

  • Page 482: Figure 6.7-5 Data Transfer Between If N Registers And Message

    NuMicro NUC442/NUC472 Series Technical Reference Manual START Write Command Request Register Busy = 1 WR/RD = 1 Read Message Object to IFn Read Message Object to IFn Write IFn to Message RAM Busy = 0 Figure 6.7-5 Data transfer between IF n Registers and Message After a partial write of a Message Object, the Message Buffer Registers that are not selected in the Command Mask Register will set the actual contents of the selected Message Object.
  • Page 483 NuMicro NUC442/NUC472 Series Technical Reference Manual After a successful transmission and also if no new data was written to the Message Object (NewDat = ‘0’) since the start of the transmission, the TxRqst bit of the Message Control register (CAN_IFn_MCR) will be reset. If TxIE bit of the Message Control register (CAN_IFn_MCR) is set, IntPnd bit of the Interrupt Identifier register will be set after a successful transmission.

  • Page 484: Table 6.7-1 Initialization Of A Transmit Object

    NuMicro NUC442/NUC472 Series Technical Reference Manual At the reception of a matching Remote Frame, the TxRqst bit of this Message Object is reset. The arbitration and control field (Identifier + IDE + RTR + DLC) from the shift register is stored in the Message Object of the Message RAM and the NewDat bit of this Message Object is set.

  • Page 485: Table 6.7-2 Initialization Of A Receive Object

    NuMicro NUC442/NUC472 Series Technical Reference Manual When only the (eight) data bytes are updated, first 0x0087 is written to the Command Mask Register and then the number of the Message Object is written to the Command Request Register, concurrently updating the data bytes and setting TxRqst. To prevent the reset of TxRqst at the end of a transmission that may already be in progress while the data is updated, NewDat has to be set together with TxRqst.
  • Page 486 NuMicro NUC442/NUC472 Series Technical Reference Manual automatically reset. By means of a Remote Frame, the software may request another CAN node to provide new data for a receive object. Setting the TxRqst bit of a receive object will cause the transmission of a Remote Frame with the receive object’s identifier.

  • Page 487: Figure 6.7-6 Application Software Handling Of A Fifo Buffer

    NuMicro NUC442/NUC472 Series Technical Reference Manual START Read Interrupt Pointer Case Interrupt Pointer 0x8000 else 0x0000 Status Change Interrupt Handing Message Num = Interrupt Pointer Write Message Num to IFn Command Register (Read Message to IFn Registers, Reset NewDat = 0, Reset IntPnd = 0) Read IFn to Message Control NewDat = 1 Read Data from IFn Data A, B...
  • Page 488 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.7.6.14 Handling Interrupts If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it The Status Interrupt has the highest priority.

  • Page 489: Figure 6.7-7 Bit Timing

    NuMicro NUC442/NUC472 Series Technical Reference Manual node, creating a common bit rate even though the oscillator periods of the CAN nodes (f osc ) may be different. The frequencies of these oscillators are not absolutely stable, small variations are caused by changes in temperature or voltage and by deteriorating components.

  • Page 490: Figure 6.7-8 Propagation Time Segment

    NuMicro NUC442/NUC472 Series Technical Reference Manual This table describes the minimum programmable ranges required by the CAN protocol Table 6.7-3 CAN Bit Time Parameters A given bit rate may be met by different bit time configurations, but for the proper function of the CAN network the physical delay times and the oscillator’s tolerance range have to be considered.
  • Page 491 NuMicro NUC442/NUC472 Series Technical Reference Manual (B_to_A). Due to oscillator tolerances, the actual position of node A’s Sample Point can be anywhere inside the nominal range of node A’s Phase Buffer Segments, so the bit transmitted by node B must arrive at node A before the start of Phase_Seg1. This condition defines the length of Prop_Seg.

  • Page 492: Figure 6.7-9 Synchronization On "Late" And "Early" Edges

    NuMicro NUC442/NUC472 Series Technical Reference Manual lengthened. If the magnitude of the phase error is less than SJW, Phase_Seg1 is lengthened by the magnitude of the phase error, else it is lengthened by SJW. When the phase error of the edge, which causes Re-synchronization is negative, Phase_Seg2 is shortened.

  • Page 493: Figure 6.7-10 Filtering Of Short Dominant Spikes

    NuMicro NUC442/NUC472 Series Technical Reference Manual In the first example an edge from recessive to dominant occurs at the end of Prop_Seg. The edge is “late” since it occurs after the Sync_Seg. Reacting to the “late” edge, Phase_Seg1 is lengthened so that the distance from the edge to the Sample Point is the same as it would have been from the Sync_Seg to the Sample Point if no edge had occurred.
  • Page 494 NuMicro NUC442/NUC472 Series Technical Reference Manual synchronize on edges from dominant to recessive became obsolete, only edges from recessive to dominant are considered for synchronization. The protocol update to version 2.0 (A and B) had no influence on the oscillator tolerance. The tolerance range df for an oscillator frequency f osc around the nominal frequency f nom is: 1 –...

  • Page 495: Figure 6.7-11 Structure Of The Can Core's Can Protocol Controller

    NuMicro NUC442/NUC472 Series Technical Reference Manual Configuration (BRP) Configuration (BRP) APB Clock APB Clock Scaled_Clock (tq) Scaled_Clock (tq) Baudrate_ Baudrate_ Prescaler Prescaler Sample_Point Sample_Point Control Control Received_Data Received_Data Sample_Bit Sample_Bit Sync_Mode Sync_Mode Status Status Transmit_Data Transmit_Data Bit_to_send Bit_to_send Timing Timing Stream Stream Bus_Off...
  • Page 496 NuMicro NUC442/NUC472 Series Technical Reference Manual the Baud Rate Prescaler with t q = (Baud Rate Prescaler)/f . Several combinations may lead apb_clk to the desired bit time, allowing iterations of the following steps. First part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times measured in the APB clock.
  • Page 497 NuMicro NUC442/NUC472 Series Technical Reference Manual Example for Bit Timing at High Baud Rate In this example , the frequency of APB_CLK is 10 MHz, BRP is 0, the bit rate is 1 MBit/s. APB_CLK delay of bus driver delay of receiver circuit delay of bus line (40m) = 6 •...
  • Page 498 NuMicro NUC442/NUC472 Series Technical Reference Manual Example for Bit Timing at Low Baud Rate In this example, the frequency of APB_CLK is 2 MHz, BRP is 1, the bit rate is 100 Kbit/s. s = 2 •t APB_CLK delay of bus driver delay of receiver circuit delay of bus line (40m) s = 1 •t...

  • Page 499: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.7.7 Register Description The C_CAN allocates an address space of 256 bytes. The registers are organized as 16-bit registers. The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.

  • Page 500: Can Interface Reset State

    NuMicro NUC442/NUC472 Series Technical Reference Manual CAN_IF2_CMASK CANx_BA+0x84 IF2 Command Mask Register 0x0000_0000 CAN_IF2_MASK1 CANx_BA+0x88 IF2 Mask 1 Register 0x0000_FFFF CAN_IF2_MASK2 CANx_BA+0x8C IF2 Mask 2 Register 0x0000_FFFF CAN_IF2_ARB1 CANx_BA+0x90 IF2 Arbitration 1 Register 0x0000_0000 CAN_IF2_ARB2 CANx_BA+0x94 IF2 Arbitration 2 Register 0x0000_0000 CAN_IF2_MCON CANx_BA+0x98...
  • Page 501 NuMicro NUC442/NUC472 Series Technical Reference Manual CAN Register Map for Each Bit Function Addr Register Offset Name CAN_CON Reserved Init CAN_STATUS Reserved CAN_ERR REC6-0 TEC7-0 CAN_BTIME TSeg2 TSeg1 CAN_IIDR IntId15-8 IntId7-0 CAN_TEST Reserved Reserved CAN_BRPE Reserved BRPE CAN_IF1_CR Busy Reserved Message Number CAN_IF1_CM Reserved...
  • Page 502 NuMicro NUC442/NUC472 Series Technical Reference Manual Addr Register Name Offset CAN_IF1_MCO Reserved DLC3-0 CAN_IF1_DAT Data(1) Data(0) CAN_IF1_DAT Data(3) Data(2) CAN_IF1_DAT Data(5) Data(4) CAN_IF1_DAT Data(7) Data(6) CAN_IF2_CRE Busy Reserved Message Number CAN_IF2_CMA Reserved CAN_IF2_MAS Msk15-0 CAN_IF2_MAS MDir Res. Msk28-16 CAN_IF2_ARB ID15-0 CAN_IF2_ARB ID28-16 CAN_IF2_MCO...

  • Page 503: Table 6.7-4 Can Register Map For Each Bit Function

    NuMicro NUC442/NUC472 Series Technical Reference Manual Addr Register Name Offset CAN_IF2_DAT Data(3) Data(2) CAN_IF2_DAT Data(5) Data(4) CAN_IF2_DAT Data(7) Data(6) 100h CAN_TXREQ1 TxRqst16-1 104h CAN_TXREQ2 TxRqst32-17 120h CAN_NDAT1 NewDat16-1 124h CAN_NDAT2 NewDat32-17 140h CAN_IPND1 IntPnd16-1 144h CAN_IPND2 IntPnd32-17 160h CAN_MVLD1 MsgVal16-1 164h CAN_MVLD2 MsgVal32-17...
  • Page 504 NuMicro NUC442/NUC472 Series Technical Reference Manual CAN Control Register (CAN_CON) Register Offset Description Reset Value CAN_CON CANx_BA+0x00 Control Register 0x0000_0001 Reserved Reserved Reserved Test Reserved Init Bits Description [31:8] Reserved Reserved. Test Mode Enable Bit Test 0 = Normal Operation. 1 = Test Mode.
  • Page 505 NuMicro NUC442/NUC472 Series Technical Reference Manual 1 = Initialization is started. Note: The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or resetting the Init bit. If the device goes in the busoff state, it will set Init of its own accord, stopping all bus activities. Once Init has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operations.
  • Page 506 NuMicro NUC442/NUC472 Series Technical Reference Manual CAN Status Register (CAN_STATUS) Register Offset Description Reset Value CAN_STATUS CANx_BA+0x04 Status Register 0x0000_0000 Reserved Reserved Reserved BOFF EWarn EPass RxOK TxOK Bits Description [31:8] Reserved Reserved. Bus-Off Status (Read Only) BOff 0 = The CAN module is not in bus-off state. 1 = The CAN module is in bus-off state.

  • Page 507: Table 6.7-5 Error Code

    NuMicro NUC442/NUC472 Series Technical Reference Manual Error Code Meanings No Error Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. Form Error: A fixed format part of a received frame has the wrong format. AckError: The message this CAN Core transmitted was not acknowledged by another node.
  • Page 508 NuMicro NUC442/NUC472 Series Technical Reference Manual CAN Error Counter Register (CAN_ERR) Register Offset Description Reset Value CAN_ERR CANx_BA+0x08 Error Counter Register 0x0000_0000 Reserved Reserved REC[6:0] TEC[7:0] Bits Description [31:16] Reserved Reserved. Receive Error Passive 0 = The Receive Error Counter is below the error passive level. [15] 1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
  • Page 509 NuMicro NUC442/NUC472 Series Technical Reference Manual Bit Timing Register (CAN_BTIME) Register Offset Description Reset Value CAN_BTIME CANx_BA+0x0C Bit Timing Register 0x0000_2301 Reserved Reserved Reserved TSeg2 TSeg1 Bits Description [31:15] Reserved Reserved. Time Segment After Sample Point [14:12] TSeg2 0x0-0x7: Valid values for TSeg2 are [0 … 7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

  • Page 510: Table 6.7-6 Source Of Interrupts

    NuMicro NUC442/NUC472 Series Technical Reference Manual Interrupt Identify Register (CAN_IIDR) Register Offset Description Reset Value CAN_IIDR CANx_BA+0x10 Interrupt Identifier Register 0x0000_0000 Reserved Reserved IntId[15:8] IntId[7:0] Bits Description Interrupt Identifier (Indicates The Source Of The Interrupt) If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
  • Page 511 NuMicro NUC442/NUC472 Series Technical Reference Manual Test Register (CAN_TEST) Register Offset Description Reset Value CAN_TEST CANx_BA+0x14 Test Register 0x0000_00x0 Reserved Reserved Reserved Tx[1:0] LBack Silent Basic Bits Description [31:8] Reserved Reserved. Monitors The Actual Value Of CAN_RX Pin (Read Only) *(1) 0 = The CAN bus is dominant (CAN_RX = ‘0’).
  • Page 512 NuMicro NUC442/NUC472 Series Technical Reference Manual Baud Rate Prescaler Extension REGISTER (CAN_BRPE) Register Offset Description Reset Value CAN_BRPE CANx_BA+0x18 Baud Rate Prescaler Extension Register 0x0000_0000 Reserved Reserved Reserved Reserved BRPE Bits Description [31:4] Reserved Reserved. BRPE: Baud Rate Prescaler Extension 0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to [3:0] BRPE...

  • Page 513: Table 6.7-7 If1 And If2 Message Interface Register

    NuMicro NUC442/NUC472 Series Technical Reference Manual Message Interface Register Sets There are two sets of Interface Registers, which are used to control the CPU access to the Message RAM. The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception and transmission by buffering the data to be transferred.
  • Page 514 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Command Request Register (CAN_IFn_CREQ) Register Offset Description Reset Value CAN_IF1_CREQ CANx_BA+0x20 IF1 Command Request Register 0x0000_0001 CAN_IF2_CREQ CANx_BA+0x80 IF2 Command Request Register 0x0000_0001 Reserved Reserved Busy Message Number Bits Description Busy Flag 0 = Read/write action has finished. [15] Busy 1 = Writing to the IFn Command Request Register is in progress.
  • Page 515 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Command Mask Register (CAN_IFn_CMASK) The control bits of the IFn Command Mask Register specify the transfer direction and select which of the IFn Message Buffer Registers are source or target of the data transfer. Register Offset Description...
  • Page 516 NuMicro NUC442/NUC472 Series Technical Reference Manual 0 = Control Bits unchanged. 1 = Transfer Control Bits to Message Object. Read Operation: 0 = Control Bits unchanged. 1 = Transfer Control Bits to IFn Message Buffer Register. Clear Interrupt Pending Bit Write Operation: When writing to a Message Object, this bit is ignored.
  • Page 517 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Mask 1 Register (CAN_IFn_MASK1) Register Offset Description Reset Value CAN_IF1_MASK1 CANx_BA+0x28 IF1 Mask 1 Register 0x0000_FFFF CAN_IF2_MASK1 CANx_BA+0x88 IF2 Mask 1 Register 0x0000_FFFF Reserved Reserved Msk[15:8] Msk[7:0] Bits Description [31:16] Reserved Reserved. Identifier Mask 15-0 0 = The corresponding bit in the identifier of the message object cannot inhibit the match in [15:0] Msk[15:0]...
  • Page 518 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Mask 2 Register (CAN_IFn_MASK2) Register Offset Description Reset Value CAN_IF1_MASK2 CANx_BA+0x2C IF1 Mask 2 Register 0x0000_FFFF CAN_IF2_MASK2 CANx_BA+0x8C IF2 Mask 2 Register 0x0000_FFFF Reserved Reserved MXtd MDir Reserved Msk[28:24] Msk[23:16] Bits Description [31:16] Reserved Reserved.
  • Page 519 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Arbitration 1 Register (CAN_IFn_ARB1) Register Offset Description Reset Value CAN_IF1_ARB1 CANx_BA+0x30 IF1 Arbitration 1 Register 0x0000_0000 CAN_IF2_ARB1 CANx_BA+0x90 IF2 Arbitration 1 Register 0x0000_0000 Reserved Reserved ID[15:8] ID[7:0] Bits Description [31:16] Reserved Reserved. Message Identifier 15-0 [15:0] ID[15:0] ID28 - ID0, 29-bit Identifier (“Extended Frame”).
  • Page 520 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Arbitration 2 Register (CAN_IFn_ARB2) Register Offset Description Reset Value CAN_IF1_ARB2 CANx_BA+0x34 IF1 Arbitration 2 Register 0x0000_0000 CAN_IF2_ARB2 CANx_BA+0x94 IF2 Arbitration 2 Register 0x0000_0000 Reserved Reserved MsgVal ID[28:24] ID[23:16] Bits Description [31:16] Reserved Reserved. Message Valid 0 = The Message Object is ignored by the Message Handler.
  • Page 521 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Message Control Register (CAN_IFn_MCON) Register Offset Description Reset Value CAN_IF1_MCON CANx_BA+0x38 IF1 Message Control Register 0x0000_0000 CAN_IF2_MCON CANx_BA+0x98 IF2 Message Control Register 0x0000_0000 Reserved Reserved NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst Reserved DLC[3:0] Bits...
  • Page 522 NuMicro NUC442/NUC472 Series Technical Reference Manual 1 = IntPnd will be set after a successful reception of a frame. Remote Enable Bit RmtEn 0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. 1 = At the reception of a Remote Frame, TxRqst is set. Transmit Request TxRqst 0 = This Message Object is not waiting for transmission.
  • Page 523 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Data A1 Register (CAN_IFn_DAT_A1) Register Offset Description Reset Value CAN_IF1_DAT_A1 CANx_BA+0x3C IF1 Data A1 Register 0x0000_0000 CAN_IF2_DAT_A1 CANx_BA+0x9C IF2 Data A1 Register 0x0000_0000 Reserved Reserved Data1 Data0 Bits Description [31:16] Reserved Reserved. Data Byte 1 [15:8] Data1 2nd data byte of a CAN Data Frame...
  • Page 524 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Data A2 Register (CAN_IFn_DAT_A2) Register Offset Description Reset Value CAN_IF1_DAT_A2 CANx_BA+0x40 IF1 Data A2 Register 0x0000_0000 CAN_IF2_DAT_A2 CANx_BA+0xA0 IF2 Data A2 Register 0x0000_0000 Reserved Reserved Data3 Data2 Bits Description [31:16] Reserved Reserved. Data Byte 3 [15:8] Data3 4th data byte of CAN Data Frame...
  • Page 525 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Data B1 Register (CAN_IFn_DAT_B1) Register Offset Description Reset Value CAN_IF1_DAT_B1 CANx_BA+0x44 IF1 Data B1 Register 0x0000_0000 CAN_IF2_DAT_B1 CANx_BA+0xA4 IF2 Data B1 Register 0x0000_0000 Reserved Reserved Data5 Data4 Bits Description [31:16] Reserved Reserved. Data Byte 5 [15:8] Data5 6th data byte of CAN Data Frame...
  • Page 526 NuMicro NUC442/NUC472 Series Technical Reference Manual IFn Data B2 Register (CAN_IFn_DAT_B2) Register Offset Description Reset Value CAN_IF1_DAT_B2 CANx_BA+0x48 IF1 Data B2 Register 0x0000_0000 CAN_IF2_DAT_B2 CANx_BA+0xA8 IF2 Data B2 Register 0x0000_0000 Reserved Reserved Data7 Data6 Bits Description [31:16] Reserved Reserved. Data Byte 7 [15:8] Data7 8th data byte of CAN Data Frame.

  • Page 527: Table 6.7-8 Structure Of A Message Object In The Message Memory

    NuMicro NUC442/NUC472 Series Technical Reference Manual Message Object in the Message Memory There are 32 Message Objects in the Message RAM. To avoid conflicts between application software access to the Message RAM and CAN message reception and transmission, the CPU cannot directly access the Message Objects, these accesses are handled through the IFn Interface Registers.
  • Page 528 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmission Request Register 1 (CAN_TXREQ1) These registers hold the TxRqst bits of the 32 Message Objects. By reading the TxRqst bits, the software can check which Message Object in a Transmission Request is pending. The TxRqst bit of a specific Message Object can be set/reset by the application software through the IFn Message Interface Registers or by the Message Handler after reception of a Remote Frame or after a successful transmission.
  • Page 529 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmission Request Register 2 (CAN_TXREQ2) Register Offset Description Reset Value CAN_TXREQ2 CANx_BA+0x104 R Transmission Request Register 2 0x0000_0000 Reserved Reserved TxRqst32-25 TxRqst24-17 Bits Description [31:16] Reserved Reserved. Transmission Request Bits 32-17 (Of All Message Objects) 0 = This Message Object is not waiting for transmission.
  • Page 530 NuMicro NUC442/NUC472 Series Technical Reference Manual New Data Register 1 (CAN_NDAT1) These registers hold the NewDat bits of the 32 Message Objects. By reading out the NewDat bits, the software can check for which Message Object the data portion was updated. The NewDat bit of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers or by the Message Handler after reception of a Data Frame or after a successful transmission.
  • Page 531 NuMicro NUC442/NUC472 Series Technical Reference Manual New Data Register 2 (CAN_NDAT2) Register Offset Description Reset Value CAN_NDAT2 CANx_BA+0x124 R New Data Register 2 0x0000_0000 Reserved Reserved NewData 32-25 NewData 24-17 Bits Description [31:16] Reserved Reserved. New Data Bits 32-17 (Of All Message Objects) 0 = No new data has been written into the data portion of this Message Object by the [15:0] NewData 32-17...
  • Page 532 NuMicro NUC442/NUC472 Series Technical Reference Manual Interrupt Pending Register 1 (CAN_IPND1) These registers contain the IntPnd bits of the 32 Message Objects. By reading the IntPnd bits, the software can check for which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset by the application software through the IFn Message Interface Registers or by the Message Handler after reception or after a successful transmission of a frame.
  • Page 533 NuMicro NUC442/NUC472 Series Technical Reference Manual Interrupt Pending Register 2 (CAN_IPND2) Register Offset Description Reset Value CAN_IPND2 CANx_BA+0x144 R Interrupt Pending Register 2 0x0000_0000 Reserved Reserved IntPnd 32-25 IntPnd 24-17 Bits Description [31:16] Reserved Reserved. Interrupt Pending Bits 32-17(Of All Message Objects) [15:0] IntPnd 32-17 0 = This message object is not the source of an interrupt.
  • Page 534 NuMicro NUC442/NUC472 Series Technical Reference Manual Message Valid Register 1 (CAN_MVLD1) These registers hold the MsgVal bits of the 32 Message Objects. By reading the MsgVal bits, the application software can check which Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by the application software via the IFn Message Interface Registers.
  • Page 535 NuMicro NUC442/NUC472 Series Technical Reference Manual Message Valid Register 2 (CAN_MVLD2) Register Offset Description Reset Value CAN_MVLD2 CANx_BA+0x164 R Message Valid Register 2 0x0000_0000 Reserved Reserved MsgVal 32-25 MsgVal 24-17 Bits Description [31:16] Reserved Reserved. Message Valid Bits 32-17 (Of All Message Objects) (Read Only) 0 = This Message Object is ignored by the Message Handler.
  • Page 536 NuMicro NUC442/NUC472 Series Technical Reference Manual Wake-up Enable Control Register (CAN_WU_EN) Register Offset Description Reset Value CAN_WU_EN CANx_BA+0x168 R/W Wake-up Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WAKUP_EN Bits Description [31:1] Reserved Reserved. Wake-Up Enable Bit 0 = The wake-up function Disabled. WAKUP_EN 1 = The wake-up function Enabled.
  • Page 537 NuMicro NUC442/NUC472 Series Technical Reference Manual Wake-up Status Register (CAN_WU_STATUS) Register Offset Description Reset Value CAN_WU_STATUS CANx_BA+0x16C R/W Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WAKUP_STS Bits Description [31:1] Reserved Reserved. Wake-Up Status 0 = No wake-up event occurred. WAKUP_STS 1 = Wake-up event occurred.

  • Page 538: Crc Controller

    NuMicro NUC442/NUC472 Series Technical Reference Manual CRC Controller 6.8.1 Overview The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with programmable polynomial settings. 6.8.2 Features  Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32  CRC-CCITT: X  CRC-8: X + X + 1 ...

  • Page 539: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.8.3 Block Diagram Figure 6.8-1 CRC Generator Block Diagram 6.8.4 Basic Configuration The CRC peripheral clock is enabled in CRCCKEN (CLK_AHBCLK[7]). After CRC is setting, user can start to perform CRC calculate by control CRC’s registers. May 23, 2014 Page 539 of 1386 Rev.1.05...

  • Page 540: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.8.5 Functional Description CRC generator can perform CRC calculation with programmable polynomial settings. The operation polynomial includes CRC-CCITT, CRC-8, CRC-16 and CRC-32; User can choose the CRC operation polynomial mode by setting CRCMODE[1:0] (CRC_CTL[31:30] CRC Polynomial Mode).

  • Page 541: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.8.7 Register Description CRC Control Register (CRC_CTL) Register Offset Description Reset Value CRC_CTL CRC_BA+0x00 CRC Control Register 0x2000_0000 CRCMODE DATLEN CHKSFMT DATFMT CHKSREV DATREV Reserved Reserved Reserved CRCRST CRCEN Bits Description CRC Polynomial Mode Selection 00 = CRC-CCITT Polynomial mode.
  • Page 542 NuMicro NUC442/NUC472 Series Technical Reference Manual Write Data Order Reverse 0 = No bit order reversed for CRC write data in. DATREV [24] 1 = Bit order reversed for CRC write data in (per byte). Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB Reserved [23:2]...
  • Page 543 NuMicro NUC442/NUC472 Series Technical Reference Manual CRC Write Data Register (CRC_DAT) Register Offset Description Reset Value CRC_DAT CRC_BA+0x04 CRC Write Data Register 0x0000_0000 DATA [31:24] DATA [23:16] DATA [15:8] DATA [7:0] Bits Description CRC Write Data Bits Software can write data to this field to perform CRC operation, or uses PDMA function to get the data from memory [31:0] DATA...
  • Page 544 NuMicro NUC442/NUC472 Series Technical Reference Manual CRC Seed Register (CRC_SEED) Register Offset Description Reset Value CRC_SEED CRC_BA+0x08 CRC Seed Register 0xFFFF_FFFF SEED [31:24] SEED [23:16] SEED [15:8] SEED [7:0] Bits Description CRC Seed Bits SEED [31:0] This field indicates the CRC seed value. May 23, 2014 Page 544 of 1386 Rev.1.05...
  • Page 545 NuMicro NUC442/NUC472 Series Technical Reference Manual CRC Checksum Register (CRC_CHECKSUM) Register Offset Description Reset Value CRC_CHECKSUM CRC_BA+0x0C CRC Checksum Register 0x0000_0000 CHECKSUM [31:24] CHECKSUM [23:16] CHECKSUM [15:8] CHECKSUM [7:0] Bits Description CRC Checksum Bits CHECKSUM [31:0] This field indicates the CRC checksum. May 23, 2014 Page 545 of 1386 Rev.1.05...

  • Page 546: Cryptographic Accelerator

    NuMicro NUC442/NUC472 Series Technical Reference Manual Cryptographic Accelerator 6.9.1 Overview The Crypto (Cryptographic Accelerator) includes a secure pseudo random number generator (PRNG) core and supports AES, DES/TDES, and SHA algorithms. The PRNG core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation. The AES accelerator is an implementation fully compliant with the AES (Advance Encryption Standard) encryption and decryption algorithm.

  • Page 547: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.9.3 Block Diagram Figure 6.9-1 Cryptographic Accelerator Block Diagram May 23, 2014 Page 547 of 1386 Rev.1.05...

  • Page 548: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.9.4 Functional Description The cryptographic accelerator includes a secure pseudo random number generator (PRNG) core and supports AES, DES/TDES, SHA algorithms. The accelerator can be used in different data security applications, such as secure communications that need cryptographic protection and integrity. 1.

  • Page 549: Figure 6.9-2 Prng Function Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.9.4.1 PRNG (Pseudo Random Number Generator) The PRNG block diagram is depicted below. The core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation configured by KEYSZ. BUSY BUSY PRNG PRNG PRNG SEED...

  • Page 550: Figure 6.9-3 Electronic Codebook Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.9-3 Electronic Codebook Mode In ECB mode, any given plaintext block always gets encrypted to the same ciphertext block under a given key. If this property is undesirable in a particular application, the ECB mode should not be used. Cipher Block Chaining Mode: The Cipher Block Chaining (CBC) mode is a confidentiality mode whose encryption process features the combining chaining of the plaintext blocks with the previous ciphertext blocks.

  • Page 551: Figure 6.9-4 Cipher Block Chaining Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.9-4 Cipher Block Chaining Mode Cipher Feedback Mode (CFB): The Cipher Feedback (CFB) mode is a confidentiality mode that features the feedback of successive ciphertext segments into the input blocks of the forward cipher to generate output blocks that are exclusive-ORed with the plaintext to produce the ciphertext, and vice versa.

  • Page 552: Figure 6.9-5 Cipher Feedback Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.9-5 Cipher Feedback Mode Output Feedback Mode: The Output Feedback (OFB) mode is a confidentiality mode that features the iteration of the forward cipher on an IV to generate a sequence of output blocks that are exclusive-ORed with the plaintext to produce the ciphertext, and vice versa.

  • Page 553: Figure 6.9-6 Output Feedback Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.9-6 Output Feedback Mode Counter Mode (CTR): The Counter (CTR) mode is a confidentiality mode that features the application of the forward cipher to a set of input blocks, called counters, to produce a sequence of output blocks that are exclusive- ORed with the plaintext to produce the ciphertext, and vice versa.

  • Page 554: Figure 6.9-7 Counter Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.9-7 Counter Mode CBC Ciphertext-Stealing 1 Mode (CBC-CS1): The figure below illustrates the CBC-CS1-Encrypt algorithm for the case that P is a partial block. The cryptographic accelerator would append P with ‘0’ to form a complete block P May 23, 2014 Page 554 of 1386 Rev.1.05...

  • Page 555: Figure 6.9-8 Cbc-Cs1 Encryption

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.9-8 CBC-CS1 Encryption The figure below illustrates the CBC-CS1-Decrypt algorithm for the case that C is a partial block. Figure 6.9-9 CBC-CS1 Decryption CBC Ciphertext-Stealing 2 Mode (CBC-CS2): When P is a partial block, then CBC-CS2-Encrypt and CBC-CS1-Encrypt differ only in the ordering of and C May 23, 2014 Page 555 of 1386...
  • Page 556 NuMicro NUC442/NUC472 Series Technical Reference Manual CBC Ciphertext-Stealing 3 Mode (CBC-CS3): and C are unconditionally swapped, i.e., even when C is a complete block; therefore, CBC- CS3 is not strictly an extension of CBC mode. In the other case, i.e., when C is a nonempty partial block, CBC-CS3-Encrypt is equivalent to CBC-CS2-Encrypt.

  • Page 557: Table 6.9-1 Comparison Of Sha Functions

    NuMicro NUC442/NUC472 Series Technical Reference Manual is 0. Check the TDES engine is in idle state, i.e., BUSY(CRPT_TDES_STS[0]) Program TDES registers CRPT_TDESn_KEY1H, CRPT_TDESn_KEY1L, CRPT_TDESn_KEY2H, CRPT_TDESn_KEY2L, CRPT_TDESn_KEY3H, CRPT_TDESn_KEY3L. (where n is the selected channel number) Program initial vector to registers CRPT_TDESn_IVH and CRPT_TDESn_IVL. Program DMA source address to register CRPT_TDESn_SADR.
  • Page 558 NuMicro NUC442/NUC472 Series Technical Reference Manual SHA DMA mode programming flow: Write 1 to SHAIEN(CRPT_INTEN[24]) to enable SHA interrupt. Configure SHA control register CRPT_SHA_CTL for SHA engine input/output data swap, DMA mode, and SHA operation mode. Program DMA source address to register CRPT_SHA_SADDR.

  • Page 559: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.9.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value CRYPTO Base Address: CRYP_BA = 0x5008_0000 CRPT_INTEN CRYP_BA+0x000 Crypto Interrupt Enable Control Register 0x0000_0000 CRPT_INTSTS CRYP_BA+0x004 Crypto Interrupt Flag 0x0000_0000...
  • Page 560 NuMicro NUC442/NUC472 Series Technical Reference Manual CRPT_AES0_KEY4 CRYP_BA+0x120 AES Key Word 4 Register for Channel 0 0x0000_0000 CRPT_AES0_KEY5 CRYP_BA+0x124 AES Key Word 5 Register for Channel 0 0x0000_0000 CRPT_AES0_KEY6 CRYP_BA+0x128 AES Key Word 6 Register for Channel 0 0x0000_0000 CRPT_AES0_KEY7 CRYP_BA+0x12C AES Key Word 7 Register for Channel 0 0x0000_0000...
  • Page 561 NuMicro NUC442/NUC472 Series Technical Reference Manual CRPT_AES2_IV0 CRYP_BA+0x1A8 AES Initial Vector Word 0 Register for Channel 2 0x0000_0000 CRPT_AES2_IV1 CRYP_BA+0x1AC AES Initial Vector Word 1 Register for Channel 2 0x0000_0000 CRPT_AES2_IV2 CRYP_BA+0x1B0 AES Initial Vector Word 2 Register for Channel 2 0x0000_0000 CRPT_AES2_IV3 CRYP_BA+0x1B4...
  • Page 562 NuMicro NUC442/NUC472 Series Technical Reference Manual CRPT_TDES0_SADDR TDES/DES DMA Source Address Register for 0x0000_0000 CRYP_BA+0x228 Channel 0 CRPT_TDES0_DADDR TDES/DES DMA Destination Address Register for 0x0000_0000 CRYP_BA+0x22C Channel 0 CRPT_TDES0_CNT CRYP_BA+0x230 TDES/DES Byte Count Register for Channel 0 0x0000_0000 CRPT_TDES_DATIN CRYP_BA+0x234 TDES/DES Engine Input data Word Register 0x0000_0000 CRPT_TDES_DATOUT...
  • Page 563 NuMicro NUC442/NUC472 Series Technical Reference Manual CRPT_TDES3_KEY2L CRYP_BA+0x2D4 TDES Key 2 Low Word Register for Channel 3 0x0000_0000 CRPT_TDES3_KEY3H CRYP_BA+0x2D8 TDES Key 3 High Word Register for Channel 3 0x0000_0000 CRPT_TDES3_KEY3L CRYP_BA+0x2DC TDES Key 3 Low Word Register for Channel 3 0x0000_0000 CRPT_TDES3_IVH TDES/DES Initial Vector High Word Register for...

  • Page 564: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.9.6 Register Description 6.9.6.1 Crypto Register CRYPTO Interrupt Enable Control Register (CRPT_INTEN) Register Offset Description Reset Value CRPT_INTEN CRYP_BA+0x000 Crypto Interrupt Enable Control Register 0x0000_0000 Reserved SHAERRIEN SHAIEN Reserved PRNGIEN Reserved TDESERRIEN TDESIEN Reserved AESERRIEN AESIEN Bits...
  • Page 565 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Interrupt Enable Bit 0 = TDES/DES interrupt Disabled. 1 = TDES/DES interrupt Enabled. TDESIEN In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
  • Page 566 NuMicro NUC442/NUC472 Series Technical Reference Manual CRYPTO Interrupt Flag Register (CRPT_INTSTS) Register Offset Description Reset Value CRPT_INTSTS CRYP_BA+0x004 Crypto Interrupt Flag 0x0000_0000 Reserved SHAERRIF SHAIF Reserved PRNGIF Reserved TDESERRIF TDESIF Reserved AESERRIF AESIF Bits Description [31:26] Reserved Reserved. SHA Error Flag This register includes operating and setting error.
  • Page 567 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Finish Interrupt Flag This bit is cleared by writing 1, and it has no effect by writing 0. TDESIF 0 = No TDES/DES interrupt. 1 = TDES/DES encryption/decryption done interrupt. Reserved [7:2] Reserved. AES Error Flag This bit is cleared by writing 1, and it has no effect by writing 0.
  • Page 568 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.9.6.2 PRNG Register PRNG Control Register (CRPT_PRNG_CTL) Register Offset Description Reset Value CRPT_PRNG_ CRYP_BA+0x008 R/W PRNG Control Register 0x0000_0000 Reserved Reserved Reserved BUSY Reserved KEYSZ SEEDRLD START Bits Description [31:9] Reserved Reserved. PRNG Busy (Read Only) BUSY 0 = PRNG engine is idle.
  • Page 569 NuMicro NUC442/NUC472 Series Technical Reference Manual PRNG Seed Register (CRPT_PRNG_SEED) Register Offset Description Reset Value CRPT_PRNG_S CRYP_BA+0x00C W Seed for PRNG Undefined SEED SEED SEED SEED Bits Description Seed For PRNG (Write Only) [31:0] SEED The bits store the seed for PRNG engine. May 23, 2014 Page 569 of 1386 Rev.1.05...
  • Page 570 NuMicro NUC442/NUC472 Series Technical Reference Manual PRNG Key x Register (CRPT_PRNG_KEYx) Register Offset Description Reset Value CRPT_PRNG_ CRYP_BA+0x010 PRNG Generated Key0 Undefined KEY0 CRPT_PRNG_ CRYP_BA+0x014 PRNG Generated Key1 Undefined KEY1 CRPT_PRNG_ CRYP_BA+0x018 PRNG Generated Key2 Undefined KEY2 CRPT_PRNG_ CRYP_BA+0x01C PRNG Generated Key3 Undefined KEY3 CRPT_PRNG_...
  • Page 571 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.9.6.3 AES Register AES Control Register (CRPT_AES_CTL) Register Offset Description Reset Value CRPT_AES_CTL CRYP_BA+0x100 R/W AES Control Register 0x0000_0000 KEYPRT KEYUNPRT CHANNEL INSWAP OUTSWAP Reserved ENCRPT OPMODE DMAEN DMACSCAD DMALAST Reserved KEYSZ STOP START Bits Description Protect Key...
  • Page 572 NuMicro NUC442/NUC472 Series Technical Reference Manual AES Encryption/Decryption [16] ENCRPT 0 = AES engine executes decryption operation. 1 = AES engine executes encryption operation. AES Engine Operation Modes 0x00 (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). 0x02 = CFB (Cipher Feedback Mode). 0x03 = OFB (Output Feedback Mode).
  • Page 573 NuMicro NUC442/NUC472 Series Technical Reference Manual AES Engine Start 0 = No effect. START 1 = Start AES engine. BUSY flag will be set. Note: This bit is always 0 when it’s read back. May 23, 2014 Page 573 of 1386 Rev.1.05...
  • Page 574 NuMicro NUC442/NUC472 Series Technical Reference Manual AES Status Flag Register (CRPT_AES_STS) Register Offset Description Reset Value CRPT_AES_STS CRYP_BA+0x104 R AES Engine Flag 0x0001_0100 31 30 29 Reserved 23 22 21 Reserved BUSERR Reserved OUTBUFERR OUTBUFFULL OUTBUFEMPTY 15 14 13 Reserved CNTERR Reserved INBUFERR...
  • Page 575 NuMicro NUC442/NUC472 Series Technical Reference Manual AES Input Buffer Error Flag [10] INBUFERR 0 = No error. 1 = Error happens during feeding data to the AES engine. AES Input Buffer Full Flag 0 = AES input buffer is not full. Software can feed the data into the AES INBUFFULL engine.
  • Page 576 NuMicro NUC442/NUC472 Series Technical Reference Manual AES Data Input Port Register (CRPT_AES_DATIN) Register Offset Description Reset Value CRPT_AES_DATIN CRYP_BA+0x108 R/W AES Engine Data Input Port Register 0x0000_0000 DATIN DATIN DATIN DATIN Bits Description AES Engine Input Port [31:0] DATIN CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
  • Page 577 NuMicro NUC442/NUC472 Series Technical Reference Manual AES Data Output Port Register (CRPT_AES_DATOUT) Register Offset Description Reset Value CRPT_AES_DATO CRYP_BA+0x10C AES Engine Data Output Port Register 0x0000_0000 DATOUT DATOUT DATOUT DATOUT Bits Description AES Engine Output Port [31:0] DATOUT CPU gets results from the AES engine through this port by checking CRPT_AES_STS. Get data as OUTBUFEMPTY is 0.
  • Page 578 NuMicro NUC442/NUC472 Series Technical Reference Manual AES Key Word x Register (CRPT_AES0_KEYx, CRPT_AES1_KEYx, CRPT_AES2_KEYx, CRPT_AES3_KEYx) Register Offset Description Reset Value CRPT_AES0_K CRYP_BA+0x110 AES Key Word 0 Register for Channel 0 0x0000_0000 CRPT_AES0_K CRYP_BA+0x114 AES Key Word 1 Register for Channel 0 0x0000_0000 CRPT_AES0_K CRYP_BA+0x118...
  • Page 579 NuMicro NUC442/NUC472 Series Technical Reference Manual CRPT_AES2_K CRYP_BA+0x19C AES Key Word 5 Register for Channel 2 0x0000_0000 CRPT_AES2_K CRYP_BA+0x1A0 AES Key Word 6 Register for Channel 2 0x0000_0000 CRPT_AES2_K CRYP_BA+0x1A4 AES Key Word 7 Register for Channel 2 0x0000_0000 CRPT_AES3_K CRYP_BA+0x1C4 AES Key Word 0 Register for Channel 3 0x0000_0000...
  • Page 580 NuMicro NUC442/NUC472 Series Technical Reference Manual CRPT_AESn_KEYx The KEY keeps the security key for AES operation. n = 0, 1..3. x = 0, 1..7. The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit [31:0] registers are to store each security key.
  • Page 581 NuMicro NUC442/NUC472 Series Technical Reference Manual AES Initial Vector Word x Register (CRPT_AES0_IVx, CRPT_AES1_IVx, CRPT_AES2_IVx, CRPT_AES3_IVx) Register Offset Description Reset Value CRPT_AES0_ CRYP_BA+0x130 AES Initial Vector Word 0 Register for Channel 0 0x0000_0000 CRPT_AES0_ CRYP_BA+0x134 AES Initial Vector Word 1 Register for Channel 0 0x0000_0000 CRPT_AES0_ CRYP_BA+0x138...
  • Page 582 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description CRPT_AESn_IVx n = 0, 1..3. x = 0, 1..3. [31:0] Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
  • Page 583 NuMicro NUC442/NUC472 Series Technical Reference Manual Source Address Register (CRPT_AES0_SADDR, CRPT_AES1_SADDR, CRPT_AES2_SADDR, CRPT_AES3_SADDR) Register Offset Description Reset Value CRPT_AES0_S CRYP_BA+0x140 AES DMA Source Address Register for Channel 0 0x0000_0000 ADDR CRPT_AES1_S CRYP_BA+0x17C AES DMA Source Address Register for Channel 1 0x0000_0000 ADDR CRPT_AES2_S...
  • Page 584 NuMicro NUC442/NUC472 Series Technical Reference Manual Destination Address Register (CRPT_AES0_DADDR, CRPT_AES1_DADDR, CRPT_AES2_DADDR, CRPT_AES3_DADDR) Register Offset Description Reset Value CRPT_AES0_DA CRYP_BA+0x144 AES DMA Destination Address Register for Channel 0 0x0000_0000 CRPT_AES1_DA CRYP_BA+0x180 AES DMA Destination Address Register for Channel 1 0x0000_0000 CRPT_AES2_DA CRYP_BA+0x1BC AES DMA Destination Address Register for Channel 2 0x0000_0000...
  • Page 585 NuMicro NUC442/NUC472 Series Technical Reference Manual Byte Count Register (CRPT_AES0_CNT, CRPT_AES1_CNT, CRPT_AES2_CNT, CRPT_AES3_CNT) Register Offset Description Reset Value CRPT_AES0_ CRYP_BA+0x148 AES Byte Count Register for Channel 0 0x0000_0000 CRPT_AES1_ CRYP_BA+0x184 AES Byte Count Register for Channel 1 0x0000_0000 CRPT_AES2_ CRYP_BA+0x1C0 AES Byte Count Register for Channel 2 0x0000_0000 CRPT_AES3_...
  • Page 586 NuMicro NUC442/NUC472 Series Technical Reference Manual AES Feedback x Register (CRPT_AES_FDBCKx) Register Offset Description Reset Value CRPT_AES_FDBCK0 Engine Output Feedback Data after CRYP_BA+0x050 0x0000_0000 Cryptographic Operation CRPT_AES_FDBCK1 CRYP_BA+0x054 Engine Output Feedback Data after 0x0000_0000 Cryptographic Operation CRPT_AES_FDBCK2 CRYP_BA+0x058 Engine Output Feedback Data after...
  • Page 587 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.9.6.4 TDES/DES Register TDES/DES Control Register (CRPT_TDES_CTL) Register Offset Description Reset Value CRPT_TDES_ CRYP_BA+0x200 R/W TDES/DES Control Register 0x0000_0000 KEYPRT KEYUNPRT CHANNEL INSWAP OUTSWAP BLKSWAP Reserved ENCRPT Reserved OPMODE DMAEN DMACSCAD DMALAST Reserved 3KEYS TMODE STOP START...
  • Page 588 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Engine Block Double Word Endian Swap 0 = Keep the original order, e.g. {WORD_H, WORD_L}. BLKSWAP [21] 1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.
  • Page 589 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Engine Start 0 = No effect. START 1 = Start TDES/DES engine. The flag BUSY would be set. Note: The bit is always 0 when it’s read back. May 23, 2014 Page 589 of 1386 Rev.1.05...
  • Page 590 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Status Flag Register (CRPT_TDES_STS) Register Offset Description Reset Value CRPT_TDES_S CRYP_BA+0x204 TDES/DES Engine Flag 0x0001_0100 Reserved Reserved BUSERR Reserved OUTBUFERR OUTBUFFULL OUTBUFEMPTY Reserved INBUFERR INBUFFULL INBUFEMPTY Reserved BUSY Bits Description [31:21] Reserved Reserved. TDES/DES DMA Access Bus Error Flag [20] BUSERR...
  • Page 591 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES In Buffer Full Flag 0 = TDES/DES input buffer is not full. Software can feed the data into the INBUFFULL TDES/DES engine. 1 = TDES input buffer is full. Software cannot feed data to the TDES/DES engine.
  • Page 592 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Key 1, 3 High/Low Word Register (TDES_KEY1H/L, TDES_KEY2H/L, TDES_KEY3H/L) Register Offset Description Reset Value CRPT_TDES0_KE CRYP_BA+0x208 TDES/DES Key 1 High Word Register for Channel 0 0x0000_0000 CRPT_TDES0_KE CRYP_BA+0x20C TDES/DES Key 1 Low Word Register for Channel 0 0x0000_0000 CRPT_TDES0_KE CRYP_BA+0x210...
  • Page 593 NuMicro NUC442/NUC472 Series Technical Reference Manual CRPT_TDES3_KE CRYP_BA+0x2D4 TDES Key 2 Low Word Register for Channel 3 0x0000_0000 CRPT_TDES3_KE CRYP_BA+0x2D8 TDES Key 3 High Word Register for Channel 3 0x0000_0000 CRPT_TDES3_KE CRYP_BA+0x2DC TDES Key 3 Low Word Register for Channel 3 0x0000_0000 KEYH/KEYL KEYH/KEYL...
  • Page 594 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES High/Low Word Register (CRPT_TDES0_IVH/L, CRPT_TDES1_IVH/L, CRPT_TDES2_IVH/L, CRPT_TDES3_IVH/L) Register Offset Description Reset Value CRPT_TDES0_I CRYP_BA+0x220 TDES/DES Initial Vector High Word Register for 0x0000_0000 Channel 0 CRPT_TDES0_I CRYP_BA+0x224 TDES/DES Initial Vector Low Word Register for 0x0000_0000 Channel 0 CRPT_TDES1_I...
  • Page 595 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES DMA Source Address Register (CRPT_TDES0_SADDR, CRPT_TDES1_SADDR, CRPT_TDES2_SADDR, CRPT_TDES3_SADDR) Register Offset Description Reset Value CRPT_TDES0_S CRYP_BA+0x22 TDES/DES DMA Source Address Register for Channel 0 0x0000_0000 ADDR CRPT_TDES1_S CRYP_BA+0x26 TDES/DES DMA Source Address Register for Channel 1 0x0000_0000 ADDR CRPT_TDES2_S...
  • Page 596 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES DMA Destination Address Register (CRPT_TDES0_DADDR, CRPT_TDES1_DADDR, CRPT_TDES2_DADDR, CRPT_TDES3_DADDR) Register Offset Description Reset Value CRPT_TDES0_DA CRYP_BA+0x22C TDES/DES DMA Destination Address Register for 0x0000_0000 Channel 0 CRPT_TDES1_DA CRYP_BA+0x26C TDES/DES DMA Destination Address Register for 0x0000_0000 Channel 1 CRPT_TDES2_DA TDES/DES DMA Destination Address Register for...
  • Page 597 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Block Count Register (CRPT_TDES0_CNT, CRPT_TDES1_CNT, CRPT_TDES2_CNT, CRPT_TDES3_CNT) Register Offset Description Reset Value CRPT_TDES0_ CRYP_BA+0x230 TDES/DES Byte Count Register for Channel 0 0x0000_0000 CRPT_TDES1_ CRYP_BA+0x270 TDES/DES Byte Count Register for Channel 1 0x0000_0000 CRPT_TDES2_ CRYP_BA+0x2B0 TDES/DES Byte Count Register for Channel 2 0x0000_0000...
  • Page 598 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Data Input Port Register (CRPT_TDES_DATIN) Register Offset Description Reset Value CRPT_TDES_DAT CRYP_BA+0x234 TDES/DES Engine Input data Word Register 0x0000_0000 DATIN[31:24] DATIN[23:16] DATIN[15:8] DATIN[7:0] Bits Description TDES/DES Engine Input Port [31:0] DATIN CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS. Feed data as INBUFFULL is 0.
  • Page 599 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Data Output Port Register (CRPT_TDES_DATOUT) Register Offset Description Reset Value CRPT_TDES_DATO CRYP_BA+0x238 TDES/DES Engine Output data Word Register 0x0000_0000 DATOUT[31:24] DATOUT[23:16] DATOUT[15:8] DATOUT[7:0] Bits Description TDES/DES Engine Output Port [31:0] DATOUT CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS.
  • Page 600 NuMicro NUC442/NUC472 Series Technical Reference Manual TDES/DES Feedback x Register (CRPT_TDES_FEEDBACKx) Register Offset Description Reset Value CRPT_TDES_FDBCKH TDES/DES Engine Output Feedback High Word CRYP_BA+0x060 0x0000_0000 Data after Cryptographic Operation CRPT_TDES_FDBCKL CRYP_BA+0x064 TDES/DES Engine Output Feedback Low Word 0x0000_0000 Data after Cryptographic Operation FDBCK FDBCK FDBCK...
  • Page 601 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.9.6.5 SHA Register SHA Control Register (CRPT_SHA_CTL) Register Offset Description Reset Value CRPT_SHA CRYP_BA+0x300 SHA Control Register 0x0000_0000 _CTL Reserved INSWAP OUTSWAP Reserved Reserved OPMODE DMAEN Reserved DMALAST Reserved STOP START Bits Description [31:24] Reserved Reserved.
  • Page 602 NuMicro NUC442/NUC472 Series Technical Reference Manual SHA Last Block In DMA mode, this bit must be set as beginning the last DMA cascade DMALAST round. In Non-DMA mode, this bit must be set as feeding in last byte of data. [4:2] Reserved Reserved.
  • Page 603 NuMicro NUC442/NUC472 Series Technical Reference Manual SHA Flag Register (CRPT_SHA_STS) Register Offset Description Reset Value CRPT_SHA_ST CRYP_BA+0x304 SHA Status Flag 0x0000_0000 Reserved Reserved DATINREQ Reserved DMAERR Reserved DMABUSY BUSY Bits Description [31:16] Reserved Reserved. SHA Non-DMA Mode Data Input Request [16] DATINREQ 0 = No effect.
  • Page 604 NuMicro NUC442/NUC472 Series Technical Reference Manual SHA Outputs Digest Word Register (CRPT_SHA_DGSTx) Register Offset Description Reset Value CRPT_SHA_DGS CRYP_BA+0x308 SHA Digest Message 0 0x0000_0000 CRPT_SHA_DGS CRYP_BA+0x30C SHA Digest Message 1 0x0000_0000 CRPT_SHA_DGS CRYP_BA+0x310 SHA Digest Message 2 0x0000_0000 CRPT_SHA_DGS CRYP_BA+0x314 SHA Digest Message 3 0x0000_0000 CRPT_SHA_DGS...
  • Page 605 NuMicro NUC442/NUC472 Series Technical Reference Manual SHA Key Byte Count Register (CRPT_SHA_KEYCNT ) Register Offset Description Reset Value CRPT_SHA_KE CRYP_BA+0x348 SHA Key Byte Count Register 0x0000_0000 YCNT KEYCNT KEYCNT KEYCNT KEYCNT Bits Description SHA Key Byte Count The CRPT_SHA_KEYCNT keeps the byte count of key that SHA engine operates. The register is 32-bit and the maximum byte count is 4G bytes.
  • Page 606 NuMicro NUC442/NUC472 Series Technical Reference Manual SHA DMA Source Address Register (CRPT_SHA_SADDR) Register Offset Description Reset Value CRPT_SHA_S CRYP_BA+0x34C SHA DMA Source Address Register 0x0000_0000 ADDR SADDR[31:24] SADDR[23:16] SADDR[15:8] SADDR[7:0] Bits Description SHA DMA Source Address The SHA accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
  • Page 607 NuMicro NUC442/NUC472 Series Technical Reference Manual SHA Byte Count Register (CRPT_SHA_DMACNT) Register Offset Description Reset Value CRPT_SHA_ CRYP_BA+0x350 SHA Byte Count Register 0x0000_0000 DMACNT DMACNT DMACNT DMACNT DMACNT Bits Description SHA Operation Byte Count The CRPT_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode.
  • Page 608 NuMicro NUC442/NUC472 Series Technical Reference Manual SHA Data Input Port Register (CRPT_SHA_DATIN) Register Offset Description Reset Value CRPT_SHA_DAT CRYP_BA+0x354 SHA Engine Non-DMA Mode Data Input Port Register 0x0000_0000 DATIN DATIN DATIN DATIN Bits Description SHA Engine Input Port [31:0] DATIN CPU feeds data to SHA engine through this port by checking CRPT_SHA_STS.

  • Page 609: Pdma Controller (Pdma)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.10 PDMA Controller (PDMA) 6.10.1 Overview The direct memory access (PDMA) controller is used to provide high-speed data transfer. The PDMA controller can module transfers data from one address to another without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.

  • Page 610: Table 6.10-1 Memory Map Of Embedded Descriptor Table

    NuMicro NUC442/NUC472 Series Technical Reference Manual without CPU intervention. The PDMA controller supports a single request type or burst request type and the request source can be from software request or peripheral request. A single request means that user or peripheral is ready to transfer one item (every item needs one request), and the burst request means that user or peripheral is ready to transfer multiple items (multiple items only need one request).

  • Page 611: Figure 6.10-2 Embedded Description Table Data Structure

    NuMicro NUC442/NUC472 Series Technical Reference Manual DSCT15 DSCT14 4Byte DSCT15_NEXT 0x0C 4Byte DSCT15_ENDDA 0x08 4Byte DSCT15_ENDSA 0x04 4Byte DSCT15_CTL 0x00 Embedded Descriptor Table Data Structure DSCT1 DSCT0 Embedded Descriptor Table Figure 6.10-2 Embedded Description Table Data Structure PDMA Operation Mode The PDMA controller supports three operation modes including Stop mode, Basic mode, and Scatter-Gather mode.

  • Page 612: Figure 6.10-3 Embedded Description Table Data Structure

    NuMicro NUC442/NUC472 Series Technical Reference Manual interrupt to CPU if each PDMA interrupt bit is enabled (PDMA_INTEN) and DSCTx_CTL [7] bit is “0” (when finishing task and DSCTx_CTL [7] bit is “0”, each PDMA_TDSTS flag will be asserted and if this bit is “1” PDMA_TDSTS will not be active). LSB 16 bits DSCT15 SCATBA...

  • Page 613: Figure 6.10-4 Embedded Description Table Data Structure

    NuMicro NUC442/NUC472 Series Technical Reference Manual Priority Setting Arbitration Priority In Descending Channel Number Order (PDMA_FPIOSET) Fixed Priority (Enable) Highest Fixed Priority (Enable) Fixed Priority (Enable) Round-Robin Priority (Disable) Round-Robin Priority (Disable) Round-Robin Priority (Disable) Lowest Table 6.10-2 Channel Priority Table The following figure shows an example about single request type and burst request type.
  • Page 614 NuMicro NUC442/NUC472 Series Technical Reference Manual Channel time-out When the PDMA channel is enabled and the channel has been selected to the peripheral, the channel’s corresponding time-out counter will start count down, where counter is based on 10KHz clock. If time-out counter counts to zero, the PDMA controller will generate interrupt signal. By setting PDMA Time-out Period Counter Register to control time-out counter reload value (Channel 0 and Channel 1 by setting PDMA_TOC0_1, Channel 2 and Channel 3 by setting PDMA_TOC2_3 and so on).

  • Page 615: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.10.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PDMA Base Address: PDMA_BA = 0x4000_8000 PDMA_DSCT0_CT PDMA_BA + 0x000 R/W Descriptor Table Control Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT0_EN PDMA_BA + 0x004...
  • Page 616 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA_DSCT4_NE Scatter-Gather Descriptor Table Offset Address of PDMA PDMA_BA + 0x04C 0xXXXX_XXXX Channel 4 PDMA_DSCT5_CT PDMA_BA + 0x050 R/W Descriptor Table Control Register of PDMA Channel 5 0xXXXX_XXXX PDMA_DSCT5_EN PDMA_BA + 0x054 R/W End Source Address Register of PDMA Channel 5 0xXXXX_XXXX PDMA_DSCT5_EN PDMA_BA + 0x058...
  • Page 617 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA_DSCT10_E PDMA_BA + 0x0A8 R/W End Destination Address Register of PDMA Channel 10 0xXXXX_XXXX NDDA PDMA_DSCT10_N Scatter-Gather Descriptor Table Offset Address of PDMA PDMA_BA + 0x0AC 0xXXXX_XXXX Channel 10 PDMA_DSCT11_CT PDMA_BA + 0x0B0 R/W Descriptor Table Control Register of PDMA Channel 11 0xXXXX_XXXX PDMA_DSCT11_E PDMA_BA + 0x0B4...
  • Page 618 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Scatter-Gather Descriptor Table Address of PDMA PDMA_CURSCAT1 PDMA_BA + 0x104 0x0000_0000 Channel 1 Current Scatter-Gather Descriptor Table Address of PDMA PDMA_CURSCAT2 PDMA_BA + 0x108 0x0000_0000 Channel 2 Current Scatter-Gather Descriptor Table Address of PDMA PDMA_CURSCAT3 PDMA_BA + 0x10C 0x0000_0000 Channel 3...
  • Page 619 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Scatter-Gather Descriptor Table Base Address PDMA_SCATBA PDMA_BA + 0x43C 0x2000_0000 Register PDMA_TOC0_1 PDMA_BA + 0x440 R/W PDMA Time-out Period Counter Ch1 and Ch0 Register 0xFFFF_FFFF PDMA_TOC2_3 PDMA_BA + 0x444 R/W PDMA Time-out Period Counter Ch3 and Ch2 Register 0xFFFF_FFFF PDMA_TOC4_5 PDMA_BA + 0x448...

  • Page 620: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.10.6 Register Description PDMA Channel Control Register (PDMA_CHCTL) Register Offset R/W Description Reset Value PDMA_CHCTL PDMA_BA + 0x400 PDMA Channel Control Register 0x0000_0000 Reserved Reserved CHEN15 CHEN14 CHEN13 CHEN12 CHEN11 CHEN10 CHEN9 CHEN8 CHEN7 CHEN6 CHEN5 CHEN4...
  • Page 621 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Stop Transfer Register (PDMA_STOP) Register Offset R/W Description Reset Value PDMA_STOP PDMA_BA + 0x404 PDMA Stop Transfer Register 0x0000_0000 Reserved Reserved STOP15 STOP14 STOP13 STOP12 STOP11 STOP10 STOP9 STOP8 STOP7 STOP6 STOP5 STOP4 STOP3 STOP2 STOP1...
  • Page 622 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Software Request Register (PDMA_SWREQ) Register Offset R/W Description Reset Value PDMA_SWREQ PDMA_BA + 0x408 PDMA Software Request Register 0x0000_0000 Reserved Reserved SWREQ15 SWREQ14 SWREQ13 SWREQ12 SWREQ11 SWREQ10 SWREQ9 SWREQ8 SWREQ7 SWREQ6 SWREQ5 SWREQ4 SWREQ3 SWREQ2 SWREQ1...
  • Page 623 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Request Active Flag Register (PDMA_TRGSTS) Register Offset R/W Description Reset Value PDMA_TRGSTS PDMA_BA + 0x40C PDMA Request Active Flag Register 0x0000_0000 Reserved Reserved REQSTS15 REQSTS14 REQSTS13 REQSTS12 REQSTS11 REQSTS10 REQSTS9 REQSTS8 REQSTS7 REQSTS6 REQSTS5 REQSTS4 REQSTS3...
  • Page 624 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA High Priority Setting Register (PDMA_PRISET) Register Offset R/W Description Reset Value PDMA_PRISET PDMA_BA + 0x410 PDMA Fixed Priority Setting Register 0x0000_0000 Reserved Reserved FPRISET15 FPRISET14 FPRISET13 FPRISET12 FPRISET11 FPRISET10 FPRISET9 FPRISET8 FPRISET7 FPRISET6 FPRISET5 FPRISET4 FPRISET3...
  • Page 625 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Fix Priority Clear Register (PDMA_PRICLR) Register Offset R/W Description Reset Value PDMA_PRICLR PDMA_BA + 0x414 PDMA Fixed Priority Clear Register 0x0000_0000 Reserved Reserved FPRICLR15 FPRICLR14 FPRICLR13 FPRICLR12 FPRICLR11 FPRICLR10 FPRICLR9 FPRICLR8 FPRICLR7 FPRICLR6 FPRICLR5 FPRICLR4 FPRICLR3...
  • Page 626 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Interrupt Enable Register (PDMA_INTEN) Register Offset R/W Description Reset Value PDMA_INTEN PDMA_BA + 0x418 PDMA Interrupt Enable Register 0x0000_0000 Reserved Reserved INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1...
  • Page 627 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Interrupt Status Register (PDMA_INTSTS) Register Offset R/W Description Reset Value PDMA_INTSTS PDMA_BA + 0x41C PDMA Interrupt Status Register 0x0000_0000 Reserved REQTOF15 REQTOF 14 REQTOF 13 REQTOF12 REQTOF11 REQTOF10 REQTOF9 REQTOF8 REQTOF7 REQTOF6 REQTOF5 REQTOF4 REQTOF3 REQTOF2...
  • Page 628 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Target Abort Flag Register (PDMA_ABTSTS) Register Offset R/W Description Reset Value PDMA_ABTSTS PDMA_BA + 0x420 PDMA Target Abort Flag Register 0x0000_0000 Reserved Reserved ABTIF15 ABTIF14 ABTIF13 ABTIF12 ABTIF11 ABTIF10 ABTIF9 ABTIF8 ABTIF7 ABTIF6 ABTIF5 ABTIF4 ABTIF3...
  • Page 629 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Transfer Done Flag Register (PDMA_TDSTS) Register Offset R/W Description Reset Value PDMA_TDSTS PDMA_BA + 0x424 PDMA Transfer Done Flag Register 0x0000_0000 Reserved Reserved TDIF15 TDIF14 TDIF13 TDIF12 TDIF11 TDIF10 TDIF9 TDIF8 TDIF7 TDIF6 TDIF5 TDIF4 TDIF3...
  • Page 630 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Scatter-Gather Transfer Done Flag Register (PDMA_SCATSTS) Register Offset R/W Description Reset Value PDMA_SCATSTS PDMA_BA + 0x428 PDMA Scatter-Gather Transfer Done Flag Register 0x0000_0000 Reserved Reserved TEMPTYF15 TEMPTYF14 TEMPTYF13 TEMPTYF12 TEMPTYF11 TEMPTYF10 TEMPTYF9 TEMPTYF8 TEMPTYF7 TEMPTYF6 TEMPTYF5...
  • Page 631 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Transfer on Active Flag Register (PDMA_TACTSTS) Register Offset R/W Description Reset Value PDMA_TACTSTS PDMA_BA + 0x42C PDMA Transfer on Active Flag Register 0x0000_0000 Reserved Reserved TXACTF15 TXACTF14 TXACTF13 TXACTF12 TXACTF11 TXACTF10 TXACTF9 TXACTF8 TXACTF7 TXACTF6 TXACTF5...
  • Page 632 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Scatter-Gather Descriptor Table Base Address Register (PDMA_SCATBA) Register Offset R/W Description Reset Value PDMA Scatter-Gather Descriptor Table Base PDMA_SCATBA PDMA_BA + 0x43C 0x2000_0000 Address Register SCATBA [15:8] SCATBA [7:0] Reserved Reserved Bits Description PDMA Scatter-Gather Descriptor Table Base Address In Scatter-Gather mode, this is the base address for calculating the next link - list address.
  • Page 633 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Time-out Period Counter Register (PDMA_TOC0_1) Register Offset R/W Description Reset Value PDMA Time-out Period Counter Ch1 and Ch0 PDMA_TOC0_1 PDMA_BA + 0x440 0xFFFF_FFFF Register TOC1[15:8] TOC1[7:0] TOC0[15:8] TOC0[7:0] Bits Description Time-Out Period Counter For Channel 1 [31:16] TOC1 This controls the period of time-out function for channel 1.
  • Page 634 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Time-out Period Counter Register (PDMA_TOC2_3) Register Offset R/W Description Reset Value PDMA Time-out Period Counter Ch3 and Ch2 PDMA_TOC2_3 PDMA_BA + 0x444 0xFFFF_FFFF Register TOC3[15:8] TOC3[7:0] TOC2[15:8] TOC2[7:0] Bits Description Time-Out Period Counter For Channel 3 [31:16] TOC3 This controls the period of time-out function for channel 3.
  • Page 635 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Time-out Period Counter Register (PDMA_TOC4_5) Register Offset R/W Description Reset Value PDMA Time-out Period Counter Ch5 and Ch4 PDMA_TOC4_5 PDMA_BA + 0x448 0xFFFF_FFFF Register TOC5[15:8] TOC5[7:0] TOC4[15:8] TOC4[7:0] Bits Description Time-Out Period Counter For Channel 5 [31:16] TOC5 This controls the period of time-out function for channel 5.
  • Page 636 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Time-out Period Counter Register (PDMA_TOC6_7) Register Offset R/W Description Reset Value PDMA Time-out Period Counter Ch7 and Ch6 PDMA_TOC6_7 PDMA_BA + 0x44C 0xFFFF_FFFF Register TOC7[15:8] TOC7[7:0] TOC6[15:8] TOC6[7:0] Bits Description Time-Out Period Counter For Channel 7 [31:16] TOC7 This controls the period of time-out function for channel 7.
  • Page 637 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Time-out Period Counter Register (PDMA_TOC8_9) Register Offset R/W Description Reset Value PDMA Time-out Period Counter Ch9 and Ch8 PDMA_TOC8_9 PDMA_BA + 0x450 0xFFFF_FFFF Register TOC9[15:8] TOC9[7:0] TOC8[15:8] TOC8[7:0] Bits Description Time-Out Period Counter For Channel 9 [31:16] TOC9 This controls the period of time-out function for channel 9.
  • Page 638 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Time-out Period Counter Register (PDMA_TOC10_11) Register Offset R/W Description Reset Value PDMA Time-out Period Counter Ch11 and Ch10 PDMA_TOC10_11 PDMA_BA + 0x454 0xFFFF_FFFF Register TOC11[15:8] TOC11[7:0] TOC10[15:8] TOC10[7:0] Bits Description Time-Out Period Counter For Channel 11 [31:16] TOC11 This controls the period of time-out function for channel 11.
  • Page 639 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Time-out Period Counter Register (PDMA_TOC12_13) Register Offset R/W Description Reset Value PDMA Time-out Period Counter Ch13 and Ch12 PDMA_TOC12_13 PDMA_BA + 0x458 0xFFFF_FFFF Register TOC13[15:8] TOC13[7:0] TOC12[15:8] TOC12[7:0] Bits Description Time-Out Period Counter For Channel 13 [31:16] TOC13 This controls the period of time-out function for channel 13.
  • Page 640 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Time-out Period Counter Register (PDMA_TOC14_15) Register Offset R/W Description Reset Value PDMA Time-out Period Counter Ch15 and Ch14 PDMA_TOC14_15 PDMA_BA + 0x45C 0xFFFF_FFFF Register TOC15[15:8] TOC15[7:0] TOC14[15:8] TOC14[7:0] Bits Description Time-Out Period Counter For Channel 15 [31:16] TOC15 This control the period of time-out function for channel 15.
  • Page 641 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Source Module Select Register 0 (PDMA_REQSEL0_3) Register Offset R/W Description Reset Value PDMA_REQSEL0_ PDMA_BA + 0x480 R/W PDMA Source Module Select Register Ch0 ~ Ch3 0x1F1F_1F1F Reserved REQSRC3 Reserved REQSRC2 Reserved REQSRC1 Reserved REQSRC0 Bits Description...
  • Page 642 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description 00111 = Connect to UART3_TX. 01000 = Connect to UART4_TX. 01001 = Connect to UART5_TX. 01010 = Reserved. 01011 = Connect to I2S_TX. 01100 = Connect to I2S1_TX. 01101 = Connect to SPI0_RX. 01110 = Connect to SPI1_RX.
  • Page 643 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Source Module Select Register 1 (PDMA_REQSEL4_7) Register Offset R/W Description Reset Value PDMA_REQSEL4_ PDMA_BA + 0x484 R/W PDMA Source Module Select Register Ch4 ~ Ch7 0x1F1F_1F1F Reserved REQSRC7 Reserved REQSRC6 Reserved REQSRC5 Reserved REQSRC4 Bits Description...
  • Page 644 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Source Module Select Register 2 (PDMA_REQSEL8_11) Register Offset R/W Description Reset Value PDMA_REQSEL8_ PDMA_BA + 0x488 R/W PDMA Source Module Select Register Ch8 ~ Ch11 0x1F1F_1F1F Reserved REQSRC11 Reserved REQSRC10 Reserved REQSRC9 Reserved REQSRC8 Bits Description...
  • Page 645 NuMicro NUC442/NUC472 Series Technical Reference Manual PDMA Source Module Select Register 3 (PDMA_REQSEL12_15) Register Offset R/W Description Reset Value PDMA_REQSEL12 PDMA_BA + 0x48C R/W PDMA Source Module Select Register Ch12 ~ Ch15 0x1F1F_1F1F Reserved REQSRC15 Reserved REQSRC14 Reserved REQSRC13 Reserved REQSRC12 Bits Description...
  • Page 646 NuMicro NUC442/NUC472 Series Technical Reference Manual Descriptor Table Control Register (PDMA_DSCTn_CTL) (n = 0~15) Register Offset R/W Description Reset Value PDMA_DSCT0_CT Descriptor Table Control Register of PDMA Channel PDMA_BA + 0x000 0xXXXX_XXXX PDMA_DSCT1_CT Descriptor Table Control Register of PDMA Channel PDMA_BA + 0x010 0xXXXX_XXXX PDMA_DSCT2_CT...
  • Page 647 NuMicro NUC442/NUC472 Series Technical Reference Manual TBINTDIS BURSIZE Reserved TXTYPE OPMODE Bits Description [31:30] Reserved Reserved. Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is [29:16] TXCNT[13:0] (TXCNT + 1); The maximum transfer count is 16384, every transfer may be byte, half- word or word that is dependent on TXWIDTH field.
  • Page 648 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description Reserved Reserved. Request Type TXTYPE 0 = Burst request type. 1 = Single request type. PDMA Operation Mode Selection 00 = Stop Mode. Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to stop mode automatically.
  • Page 649 NuMicro NUC442/NUC472 Series Technical Reference Manual End Source Address Register (PDMA_DSCn_ENDSA) (n = 0~15) Register Offset R/W Description Reset Value PDMA_DSCT0_END PDMA_BA + 0x004 R/W End Source Address Register of PDMA Channel 0 0xXXXX_XXXX PDMA_DSCT1_END PDMA_BA + 0x014 R/W End Source Address Register of PDMA Channel 1 0xXXXX_XXXX PDMA_DSCT2_END PDMA_BA + 0x024...
  • Page 650 NuMicro NUC442/NUC472 Series Technical Reference Manual ENDSA Bits Description PDMA Transfer Ending Source Address Bits This field indicates a 32-bit ending source address of PDMA. [31:0] ENDSA Note: If the source start address is 0x2000_0000, the transfer count is 0x100 and the source address increment is word, this field must be filled 0x2000_0400.
  • Page 651 NuMicro NUC442/NUC472 Series Technical Reference Manual End Destination Address Register (PDMA_DSCTn_ENDDA) (n = 0~15) Register Offset Description Reset Value PDMA_DSCT0_E PDMA_BA + 0x008 End Destination Address Register of PDMA Channel 0 0xXXXX_XXXX NDDA PDMA_DSCT1_E PDMA_BA + 0x018 End Destination Address Register of PDMA Channel 1 0xXXXX_XXXX NDDA PDMA_DSCT2_E PDMA_BA + 0x028...
  • Page 652 NuMicro NUC442/NUC472 Series Technical Reference Manual ENDDA Bits Description PDMA Transfer Ending Destination Address Bits This field indicates a 32-bit ending destination address of PDMA. ENDDA [31:0] Note: If the destination start address is 0x2000_0000, the transfer count is 0x100 and the [31:0] destination address increment is word, this field must be filled 0x2000_0400.
  • Page 653 NuMicro NUC442/NUC472 Series Technical Reference Manual Scatter-Gather Descriptor Table Offset Register (PDMA_DSCTn_NEXT) (n = 0~15) Register Offset R/W Description Reset Value PDMA_DSCT0_N Scatter-Gather Descriptor Table Offset Address of PDMA_BA + 0x00C 0xXXXX_XXXX PDMA Channel 0 PDMA_DSCT1_N Scatter-Gather Descriptor Table Offset Address of PDMA_BA + 0x01C 0xXXXX_XXXX PDMA Channel 1...
  • Page 654 NuMicro NUC442/NUC472 Series Technical Reference Manual NEXT Reserved Bits Description [31:16] Reserved Reserved. PDMA Next Description Table Offset Address Bits This field indicates the offset of next descriptor table address in system memory. Note1: The next descriptor table address must be word boundary. NEXT [15:2] Note2: The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the...
  • Page 655 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Scatter-Gather Descriptor Table Address of PDMA Channel[n] (n = 0~15) Register Offset R/W Description Reset Value Current Scatter-Gather Descriptor Table Address of PDMA_CURSCAT0 PDMA_BA + 0x100 0x0000_0000 PDMA Channel 0 Current Scatter-Gather Descriptor Table Address of PDMA_CURSCAT1 PDMA_BA + 0x104 0x0000_0000 PDMA Channel 1...
  • Page 656 NuMicro NUC442/NUC472 Series Technical Reference Manual CURADDR Bits Description PDMA External Current Descriptor Address Bits This field indicates a 32-bit current external descriptor address of PDMA. [31:0] CURADDR [31:0] Note: This field is read only and only used for Scatter-Gather mode to indicate the current external descriptor address.

  • Page 657: External Bus Interface (Ebi)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.11 External Bus Interface (EBI) 6.11.1 Overview The NUC442/NUC472 series is equipped with an external bus interface (EBI) for external device use. To minimize the connections between external device and this chip, EBI supports address bus and data bus multiplex mode.

  • Page 658: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.11.3 Block Diagram H_CLK MCLK MCLK Divider MCLKDIV Idle Cycle Timing EBI_A[24:16] Controller EBI_A[15:0] TACC TAHD EBI State AD[15:0] EBI Signal TALE Machine Timing Controller nCS[3:0] Register Output Controller DW16 Controller EBI request Address CSEN Hit and Request...

  • Page 659: Figure 6.11-2 Connection Of 16-Bit Ebi Data Width With 16-Bit Device

    NuMicro NUC442/NUC472 Series Technical Reference Manual To map the whole EBI memory space, it requires 25-bit address for 16-bit device. For package that output less than 25-bit address, EBI will map device to mirror space. Ex: For package with 23-bit EBI address, EBI will mapped external device (for Bank0/nCS[0]) to 0x6000_0000 ~ 0x60FF_FFFF, 0x6100_0000 ~ 0x61FF_FFFF, 0x6200_0000 ~ 0x62FF_FFFF and 0x6300_0000 ~ 0x63FF_FFFF simultaneously.

  • Page 660: Figure 6.11-3 Connection Of 8-Bit Ebi Data Width With 8-Bit Device

    NuMicro NUC442/NUC472 Series Technical Reference Manual 32M x 8-bit External Bus Interface SRAM EBI_A[24:8] Addr[24:8] Address latch device AD[7:0] Addr[7:0] nCS[x] AD[7:0] AD[7:0] Data[7:0] Figure 6.11-3 Connection of 8-bit EBI Data Width with 8-bit Device 32M x 16-bit External Bus Interface SRAM EBI_A[24:16] Addr[24:16]...

  • Page 661: Table 6.11-1 Timing Control Parameter Settings

    NuMicro NUC442/NUC472 Series Technical Reference Manual for a wide frequency range of EBI device. If MCLK is set to HCLK/1, EBI signals are synchronized by positive edge of MCLK, else by negative edge of MCLK. Operation and Access Timing Control In the start of access, chip select (nCS[3:0]) asserts to low and wait one MCLK for address setup time (tASU) for address stable.

  • Page 662: Figure 6.11-5 Timing Control Waveform For 16-Bit Data Width

    NuMicro NUC442/NUC472 Series Technical Reference Manual tASU tALE tLHD tA2D tACC tAHD MCLK nCS[x] Address RData AD[15:0] output[15:0] input Address AD[15:0] WData output[15:0] output[15:0] Figure 6.11-5 Timing Control Waveform for 16-bit Data Width Figure 6.11-5 shows an example of setting 16-bit data width. In this example, AD bus is used for being address [15:0] and data [15:0].

  • Page 663: Figure 6.11-6 Timing Control Waveform For 8-Bit Data Width

    NuMicro NUC442/NUC472 Series Technical Reference Manual tASU tASU tALE tALE tLHD tA2D tLHD tA2D tACC tACC tAHD tAHD MCLK MCLK nCS[x] nCS[x] Address RData Address RData AD[7:0] AD[7:0] output[7:0] output[7:0] input input EBI_A[15:8] Address output[15:8] EBI_A[15:8] Address output[15:8] Address Address AD[7:0] WData output[7:0] AD[7:0]...

  • Page 664: Figure 6.11-7 Timing Control Waveform For Insert Idle Cycle

    NuMicro NUC442/NUC472 Series Technical Reference Manual Insert Idle Cycle When EBI accessing continuously, there may occur bus conflict if the device access time is much slow with system operating. EBI controller supply additional idle cycle to solve this problem. During idle cycle, all control signals of EBI are inactive. The following figure shows idle cycle: tASU tALE tLHD tA2D...

  • Page 665: Figure 6.11-8 Timing Control Waveform For Address & Data Separate Mode (16-Bit Data Width)

    NuMicro NUC442/NUC472 Series Technical Reference Manual tACC tAHD tASU / tA2D MCLK nCS[x] EBI_A[24:0] Address output[24:0] RData AD[15:0] input AD[15:0] WData output[15:0] Figure 6.11-8 Timing Control Waveform for Address & Data Separate Mode (16-bit Data Width) 6.11.4.4 EBI Crypto Function EBI supports the transparent crypto function to protect data storing in external device.

  • Page 666: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.11.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value EBI Base Address: EBI_BA = 0x4001_0000 EBI_CTL EBI_BA+0x00 External Bus Interface General Control Register 0x0000_0000 EBI_TCTL0 EBI_BA+0x04 External Bus Interface Bank0 Timing Control Register...

  • Page 667: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.11.6 Register Description External Bus Interface Control Register (EBI_CTL) Register Offset Description Reset Value EBI_CTL EBI_BA+0x00 External Bus Interface General Control Register 0x0000_0000 CSPOLINV CRYPTOEN Reversed Reversed MCLKDIV Reversed Bits Description Reverse Chip Select The original design Chip Select is active low nCS.
  • Page 668 NuMicro NUC442/NUC472 Series Technical Reference Manual External Bus Interface Timing Control Register0 (EBI_TCTL0) Register Offset Description Reset Value EBI_TCTL0 EBI_BA+0x04 External Bus Interface Bank0 Timing Control Register 0x0000_0000 Reserved SEPEN DW16 CSEN Reserved Reversed TAHD TACC TALE Bits Description [31] Reserved Reserved.
  • Page 669 NuMicro NUC442/NUC472 Series Technical Reference Manual Idle state cycle = (W2X*MCLK). 0 = reserved. [11] Reserved Reserved. EBI Bank0 Data Access Hold Time [10:8] TAHD TAHD define data access hold time (tAHD). tAHD = (TAHD +1) * MCLK. EBI Bank0 Data Access Time [7:3] TACC TACC define data access time (tACC).
  • Page 670 NuMicro NUC442/NUC472 Series Technical Reference Manual External Bus Interface Timing Control Register1 (EBI_TCTL1) Register Offset Description Reset Value EBI_TCTL1 EBI_BA+0x08 External Bus Interface Bank1 Timing Control Register 0x0000_0000 Reserved SEPEN DW16 CSEN Reserved Reversed TAHD TACC TALE Bits Description [31] Reserved Reserved.
  • Page 671 NuMicro NUC442/NUC472 Series Technical Reference Manual Idle state cycle = (W2X*MCLK). 0 =reserved. [11] Reserved Reserved. EBI Bank1 Data Access Hold Time [10:8] TAHD TAHD define data access hold time (tAHD). tAHD = (TAHD +1) * MCLK. EBI Bank1 Data Access Time [7:3] TACC TACC define data access time (tACC).
  • Page 672 NuMicro NUC442/NUC472 Series Technical Reference Manual External Bus Interface Timing Control Register2 (EBI_TCTL2) Register Offset Description Reset Value EBI_TCTL2 EBI_BA+0x0c External Bus Interface Bank2 Timing Control Register 0x0000_0000 Reserved SEPEN DW16 CSEN Reserved Reversed TAHD TACC TALE Bits Description [31] Reserved Reserved.
  • Page 673 NuMicro NUC442/NUC472 Series Technical Reference Manual Idle state cycle = (W2X*MCLK). 0 = reserved. [11] Reserved Reserved. EBI Bank2 Data Access Hold Time [10:8] TAHD TAHD define data access hold time (tAHD). tAHD = (TAHD +1) * MCLK. EBI Bank2 Data Access Time [7:3] TACC TACC define data access time (tACC).
  • Page 674 NuMicro NUC442/NUC472 Series Technical Reference Manual External Bus Interface Timing Control Register3 (EBI_TCTL3) Register Offset Description Reset Value EBI_TCTL3 EBI_BA+0x10 External Bus Interface Bank3 Timing Control Register 0x0000_0000 Reserved SEPEN DW16 CSEN Reserved Reversed TAHD TACC TALE Bits Description [31] Reserved Reserved.
  • Page 675 NuMicro NUC442/NUC472 Series Technical Reference Manual Idle state cycle = (W2X*MCLK). 0 : reserved. [11] Reserved Reserved. EBI Bank3 Data Access Hold Time [10:8] TAHD TAHD define data access hold time (tAHD). tAHD = (TAHD +1) * MCLK. EBI Bank3 Data Access Time [7:3] TACC TACC define data access time (tACC).
  • Page 676 NuMicro NUC442/NUC472 Series Technical Reference Manual External Bus Interface Crypto KEY Word0 (EBI_KEY0) Register Offset Description Reset Value EBI_KEY0 EBI_BA+0x14 External Bus Interface Crypto Key Word 0 0x0000_0000 KEY[31:24] KEY[23:16] KEY[15:8] KEY[7:0] Bits Description [31:0] Crypto Key Word 0 (key[31:0]). May 23, 2014 Page 676 of 1386 Rev.1.05...
  • Page 677 NuMicro NUC442/NUC472 Series Technical Reference Manual External Bus Interface Crypto KEY Word1 (EBI_KEY1) Register Offset Description Reset Value EBI_KEY1 EBI_BA+0x18 External Bus Interface Crypto Key Word 1 0x0000_0000 KEY[31:24] KEY[23:16] KEY[15:8] KEY[7:0] Bits Description [31:0] Crypto Key Word 1 (key[63:32]). May 23, 2014 Page 677 of 1386 Rev.1.05...
  • Page 678 NuMicro NUC442/NUC472 Series Technical Reference Manual External Bus Interface Crypto KEY Word2 (EBI_KEY2) Register Offset Description Reset Value EBI_KEY2 EBI_BA+0x1c External Bus Interface Crypto Key Word 2 0x0000_0000 KEY[31:24] KEY[23:16] KEY[15:8] KEY[7:0] Bits Description [31:0] Crypto Key Word 2 (key[95:64]). May 23, 2014 Page 678 of 1386 Rev.1.05...
  • Page 679 NuMicro NUC442/NUC472 Series Technical Reference Manual External Bus Interface Crypto KEY Word3 (EBI_KEY3) Register Offset Description Reset Value EBI_KEY3 EBI_BA+0x20 External Bus Interface Crypto Key Word 3 0x0000_0000 KEY[31:24] KEY[23:16] KEY[15:8] KEY[7:0] Bits Description [31:0] Crypto Key Word 3 (key[127:96]). May 23, 2014 Page 679 of 1386 Rev.1.05...

  • Page 680: Ethernet Mac Controller (Emac) (Nuc472 Only)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.12 Ethernet MAC Controller (EMAC) (NUC472 Only) 6.12.1 Overview This chip provides an Ethernet MAC Controller (EMAC) for Network application. The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM function for recognizing Ethernet MAC addresses, Transmit-FIFO, Receive-FIFO, TX/RX state machine controller, time stamping engine for IEEE 1588, Magic Packet parsing engine and status controller.

  • Page 681: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.12.3 Block Diagram Figure 6.12-1 Ethernet MAC Controller Block Diagram May 23, 2014 Page 681 of 1386 Rev.1.05...

  • Page 682: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.12.4 Functional Description 6.12.4.1 Arbiter In the EMAC, there are two different bus requests, RXREQ and TXREQ respectively. Arbiter does the arbitration between the RXREQ and TXREQ, and then decides which one can request the AHB bus.

  • Page 683: Figure 6.12-2 Ethernet Frame Format

    NuMicro NUC442/NUC472 Series Technical Reference Manual function will pause the transmission process after the current transmitting frame has been transmitted out. To transmit a control frame out, software must program the destination MAC address of control frame into the register pair {EMAC_CAM13M, EMAC_CAM13L}, source MAC address into the register pair {EMAC_CAM14M, EMAC_CAM14L}, and configure LENGTH, OPCODE and OPERAND of control frame into the register pair {EMAC_CAM15MSB, EMAC_CAM15LSB}, and then set the bit SDPZ (EMAC_CTL[16]).

  • Page 684: Figure 6.12-3 64-Bit Reference Timing Counter

    NuMicro NUC442/NUC472 Series Technical Reference Manual collision filtering. 6.12.4.7 Time Stamping Engine for IEEE 1588 The EMAC supports a time stamping engine for IEEE Std. 1588. In this time stamping engine, a 64-bit counter implemented to generate the reference timing, the registers EMAC_TSSEC and ETSLSR.

  • Page 685: Dma Descriptors Data Structure

    NuMicro NUC442/NUC472 Series Technical Reference Manual 48-bit MAC address defined by registers EMAC_CAM0M and EMAC_CAM0L. The WOLEN (EMAC_CTL[6]) controls if the Magic packet parsing engine enabled. If WOLEN (EMAC_CTL[6]) is high, EMAC will set bit WOLIF (EMAC_INTSTS[15]) high to indicate Magic packet received.
  • Page 686 NuMicro NUC442/NUC472 Series Technical Reference Manual RXDES 0: RXDMA Descriptor Word 0 The RXDMA descriptor word 0 contains a descriptor ownership indicator, receive frame status, and receive frame byte count. The detail description of RXDES 0 is shown below. Owner Reserved RTSAS RPIF...
  • Page 687 NuMicro NUC442/NUC472 Series Technical Reference Manual Frame Reception Complete The RXGDIF indicates the frame reception has completed and stored in the data buffer pointed by RX descriptor. RXGDIF [20] 0 = The frame reception does not complete yet. 1 = The frame reception completed. Long Packet Interrupt Flag The LPIF indicates the frame stored in the data buffer pointed by RX descriptor is a long frame (frame length is greater than 1518 bytes).
  • Page 688 NuMicro NUC442/NUC472 Series Technical Reference Manual RXDES 1: RXDMA Descriptor Word 1 The RXDMA descriptor word 1 contains the received frame buffer starting address or time stamp least significant 32-bit value. The detail description of RXDES 1 is shown below. RXBSA/TSSUBSEC RXBSA/TSSUBSEC RXBSA/TSSUBSEC...
  • Page 689 NuMicro NUC442/NUC472 Series Technical Reference Manual RXDES 2: RXDMA Descriptor Word 2 The RXDMA descriptor word 2 currently is reserved. Reserved Reserved Reserved Reserved Bits Field Description Reserved [31:0] Reserved. May 23, 2014 Page 689 of 1386 Rev.1.05...
  • Page 690 NuMicro NUC442/NUC472 Series Technical Reference Manual RXDES 3: RXDMA Descriptor Word 3 The RXDMA descriptor word 3 contains the next RXDMA descriptor starting address or time stamp most significant 32-bit value. The detail description of RXDES 3 is shown below. NRXDSA/TSSEC NRXDSA/TSSEC NRXDSA/TSSEC...

  • Page 691: Figure 6.12-5 Txdma Descriptor Data Structure

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.12.5.2 Descriptor Data Structure The TXDMA descriptor consists of four 32-bit words. The data structure of TXDMA descriptor shown in figure below. TXDES 0 Reserved TXDES 1 Transmit Frame Buffer Starting Address / Time Stamp Sub Second TXDES 2 Transmit Frame Status Transmit Frame Byte Count...
  • Page 692 NuMicro NUC442/NUC472 Series Technical Reference Manual TXDES 0: TXDMA Descriptor Word 0 The TXDMA descriptor word 0 contains a descriptor ownership indicator. In addition, it also contains control bits for transmit frame padding, CRC append, interrupt enable and time stamping control.
  • Page 693 NuMicro NUC442/NUC472 Series Technical Reference Manual CRC Append The CRCAPP control the CRC append during frame transmission. If CRCAPP is enabled, the 4-bytes CRC checksum will be appended to frame at the end of frame CRCAPP transmission. 0 = 4-bytes CRC appending Disabled. 1 = 4-bytes CRC appending Enabled.
  • Page 694 NuMicro NUC442/NUC472 Series Technical Reference Manual TXDES 1: TXDMA Descriptor Word 1 The TXDMA descriptor word 1 contains the transmit frame buffer starting address or time stamp least significant 32-bit value. The detail description of TXDES 1 is shown below. TXBSA/TSSUBSEC TXBSA/TSSUBSEC TXBSA/TSSUBSEC...
  • Page 695 NuMicro NUC442/NUC472 Series Technical Reference Manual TXDES 2: TXDMA Descriptor Word 2 The TXDMA descriptor word 2 contains transmit frame status, and transmit frame byte count. The detail description of TXDES 2 is shown below. COLCNT TTSAS TXPAUSED TXHALT LCIF TXABTIF NCSIF EXDEFIF...
  • Page 696 NuMicro NUC442/NUC472 Series Technical Reference Manual Late Collision The LCIF indicates the collision found in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has been transmitted out to the network, the collision still found. The late collision check will only be done while EMAC is operating [23] LCIF on half-duplex mode.
  • Page 697 NuMicro NUC442/NUC472 Series Technical Reference Manual TXDES 3: TXDMA Descriptor Word 3 The TXDMA descriptor word 3 contains the next TXDMA descriptor starting address or time stamp most significant 32-bit value. The detail description of TXDES 3 is shown below. NTXDSA/TSSEC NTXDSA/TSSEC NTXDSA/TSSEC...

  • Page 698: Register And Memory Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.12.6 Register and Memory Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value EMAC Base Address: EMAC_BA = 0x4000_B000 EMAC_CAMCTL EMAC_BA+0x000 R/W CAM Comparison Control Register 0x0000_0000 ECAM_CAMEN EMAC_BA+0x004...
  • Page 699 NuMicro NUC442/NUC472 Series Technical Reference Manual EMAC_CAM12M EMAC_BA+0x068 R/W CAM12 Most Significant Word Register 0x0000_0000 EMAC_CAM12L EMAC_BA+0x06C R/W CAM12 Least Significant Word Register 0x0000_0000 EMAC_CAM13M EMAC_BA+0x070 R/W CAM13 Most Significant Word Register 0x0000_0000 EMAC_CAM13L EMAC_BA+0x074 R/W CAM13 Least Significant Word Register 0x0000_0000 EMAC_CAM14M EMAC_BA+0x078 R/W CAM14 Most Significant Word Register...
  • Page 700 NuMicro NUC442/NUC472 Series Technical Reference Manual EMAC_TSSUBSE EMAC_BA+0x114 Time Stamp Counter Sub Second Register 0x0000_0000 EMAC_TSINC EMAC_BA+0x118 R/W Time Stamp Increment Register 0x0000_0000 EMAC_TSADDEN EMAC_BA+0x11C R/W Time Stamp Addend Register 0x0000_0000 EMAC_UPDSEC EMAC_BA+0x120 R/W Time Stamp Update Second Register 0x0000_0000 EMAC_UPDSUBS EMAC_BA+0x124 R/W Time Stamp Update Sub Second Register...

  • Page 701: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.12.7 Register Description CAM Command Register (EMAC_CAMCTL) The EMAC supports CAM function for destination MAC address recognition. The EMAC_CAMCTL control the CAM comparison function, and unicast, multicast, and broadcast packet reception. Register Offset Description Reset Value EMAC_CAMCTL EMAC_BA+0x000 R/W...
  • Page 702 NuMicro NUC442/NUC472 Series Technical Reference Manual Accept Multicast Packet The AMP controls the multicast packet reception. If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address. 0 = EMAC receives packet depends on the CAM comparison result. 1 = EMAC receives all multicast packets.

  • Page 703: Table 6.12-2 Different Camcmr Setting And Type Of Received Packet

    NuMicro NUC442/NUC472 Series Technical Reference Manual Table 6.12-2 Different CAMCMR Setting and Type of Received Packet May 23, 2014 Page 703 of 1386 Rev.1.05...
  • Page 704 NuMicro NUC442/NUC472 Series Technical Reference Manual CAM Enable Register (ECAM_CAMEN) The ECAM_CAMEN controls the validation of each CAM entry. Each CAM entry must be enabled first before it participates in the destination MAC address recognition. Register Offset Description Reset Value ECAM_CAMEN EMAC_BA+0x004 R/W CAM Enable Register...
  • Page 705 NuMicro NUC442/NUC472 Series Technical Reference Manual CAM Entry Register (EMAC_CAMxMSB, x = 0, 1, 2..14) The EMAC is equipped with 16 CAM entries. In these 16 CAM entries, 13 entries (entry 0~12) are to keep destination MAC address for packet recognition, and the other 3 entries (entry 13~15) are for PAUSE control frame transmission.
  • Page 706 NuMicro NUC442/NUC472 Series Technical Reference Manual MACADDR2 Bits Description MAC Address Byte 5 The CAMxM keeps the bit 47~16 of MAC address. The x can be the 0~14. The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC [31:24] MACADDR5 address.
  • Page 707 NuMicro NUC442/NUC472 Series Technical Reference Manual CAM Entry Register (EMAC_CAMxLSB; x = 0, 1, 2..14) Register Offset R/W Description Reset Value EMAC_CAM0L EMAC_BA+0x00C R/W CAM0 Least Significant Word Register 0x0000_0000 EMAC_CAM1L EMAC_BA+0x014 R/W CAM1 Least Significant Word Register 0x0000_0000 EMAC_CAM2L EMAC_BA+0x01C R/W CAM2 Least Significant Word Register 0x0000_0000 EMAC_CAM3L...
  • Page 708 NuMicro NUC442/NUC472 Series Technical Reference Manual EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. MACADDR0 MAC Address Byte 0 [23:16] [15:0] Rserved Reserved May 23, 2014 Page 708 of 1386 Rev.1.05...
  • Page 709 NuMicro NUC442/NUC472 Series Technical Reference Manual CAM Entry Register (EMAC_CAM15MSB) Register Offset R/W Description Reset Value EMAC_CAM15M EMAC_BA+0x080 R/W CAM15 Most Significant Word Register 0x0000_0000 LENGTH LENGTH OPCODE OPCODE Bits Description LENGTH Field Of PAUSE Control Frame [31:16] LENGTH In the PAUSE control frame, a LENGTH field defined and is 16‟h8808. OP Code Field Of PAUSE Control Frame [15:0] OPCODE...
  • Page 710 NuMicro NUC442/NUC472 Series Technical Reference Manual CAM Entry Register (EMAC_CAM15LSB) Register Offset R/W Description Reset Value EMAC_CAM15LS EMAC_BA+0x084 R/W CAM15 Least Significant Word Register 0x0000_0000 OPERAND Reserved Reserved Reserved Bits Description Pause Parameter In the PAUSE control frame, an OPERAND field defined and controls how much time the [31:24] OPERAND destination Ethernet MAC Controller paused.
  • Page 711 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmit Descriptor Link List Start Address Register (EMAC_TXDSA) The TX descriptor defined in EMAC is a link-list data structure. The EMAC_TXDSA keeps the starting address of this link-list. In other words, the EMAC_TXDSA keeps the starting address of the 1st TX descriptor.
  • Page 712 NuMicro NUC442/NUC472 Series Technical Reference Manual Receive Descriptor Link List Start Address Register (EMAC_RXDSA) The RX descriptor defined in EMAC is a link-list data structure. The EMAC_RXDSA keeps the starting address of this link-list. In other words, the EMAC_RXDSA keeps the starting address of the 1st RX descriptor.
  • Page 713 NuMicro NUC442/NUC472 Series Technical Reference Manual MAC Control Register (EMAC_CTL) The EMAC_CTL provides the control information for EMAC. Some command settings affect both frame transmission and reception, such as bit FUDUP (EMAC_CTL[18]), the full/half duplex mode selection, or bit OPMODE (EMAC_CTL[20]), the 100/10M bps mode selection. Some command settings control frame transmission and reception separately, likes bit TXON (EMAC_CTL[8]) and RXON (EMAC_CTL[0]).
  • Page 714 NuMicro NUC442/NUC472 Series Technical Reference Manual RMII RX Control The RMIIRXCTL control the receive data sample in RMII mode. It’s necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high. RMIIRXCTL [19] 0 = RMII RX control disabled. 1 = RMII RX control enabled.
  • Page 715 NuMicro NUC442/NUC472 Series Technical Reference Manual Wake On LAN Enable The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet is Magic Packet and wakeup system from Power-down mode. If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet WOLEN MAC controller would generate a wakeup event to wake system up from Power-down mode.
  • Page 716 NuMicro NUC442/NUC472 Series Technical Reference Manual MII Management Data Register (EMAC_MIIMDAT) The EMAC provides MII management function to access the control and status registers of the external PHY. The EMAC_MIIMDAT register is used to store the data that will be written into the registers of external PHY for write command or the data that is read from the registers of external PHY for read command.
  • Page 717 NuMicro NUC442/NUC472 Series Technical Reference Manual MII Management Control and Address Register (EMAC_MIIMCTL) The EMAC provides MII management function to access the control and status registers of the external PHY. The EMAC_MIIMCTL register is used to keep the MII management command information, like the register address, external PHY address, MDC clocking rate, read/write etc.

  • Page 718: Figure 6.12-6 Mii Management Frame Format

    NuMicro NUC442/NUC472 Series Technical Reference Manual [15:13] Reserved Reserved. PHY Address [12:8] PHYADDR The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command. [7:5] Reserved Reserved. PHY Register Address PHYREG [4:0] The PHYREG keeps the address to indicate which register of external PHY is the target of the MII management command.
  • Page 719 NuMicro NUC442/NUC472 Series Technical Reference Manual FIFO Threshold Control Register (EMAC_FIFOCTL) The EMAC_FIFOCTL defines the high and low threshold of internal FIFOs, including TXFIFO and RXFIFO. The threshold of internal FIFOs is related to EMAC request generation and when the frame transmission starts.
  • Page 720 NuMicro NUC442/NUC472 Series Technical Reference Manual [7:2] Reserved Reserved. RXFIFO Low Threshold The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO and system memory. The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold. The low threshold is the half of high threshold always.
  • Page 721 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmit Start Demand Register (EMAC_TXST) S/W issues a write command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission. Register Offset Description Reset Value EMAC_BA+0x0A EMAC_TXST Transmit Start Demand Register Undefined TXST TXST...
  • Page 722 NuMicro NUC442/NUC472 Series Technical Reference Manual Receive Start Demand Register (EMAC_RXST) S/W issues a write command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception. Register Offset Description Reset Value EMAC_BA+0x0A EMAC_RXST Receive Start Demand Register Undefined RXST RXST...
  • Page 723 NuMicro NUC442/NUC472 Series Technical Reference Manual Maximum Receive Frame Control Register (EMAC_MRFL) The EMAC_MRFL defines the maximum frame length for a received frame that can be stored in the system memory. It is recommend that only use this register while S/W wants to receive a frame which length is greater than 1518 bytes.
  • Page 724 NuMicro NUC442/NUC472 Series Technical Reference Manual MAC Interrupt Enable Register (EMAC_INTEN) The EMAC_INTEN controls the enable of EMAC interrupt status to generate interrupt. Two interrupts, RXIF for frame reception and TXIF for frame transmission, are generated from EMAC to CPU. Register Offset Description...
  • Page 725 NuMicro NUC442/NUC472 Series Technical Reference Manual Late Collision Interrupt Enable Bit The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation. If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If LCIEN or TXIEN [22] LCIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the LCIF...
  • Page 726 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmit Interrupt Enable Bit The TXIEN controls the TX interrupt generation. If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU. If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is [16] TXIEN...
  • Page 727 NuMicro NUC442/NUC472 Series Technical Reference Manual Maximum Frame Length Exceed Interrupt Enable The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation. If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If MFLEIEN or RXIEN MFLEIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MFLEIF (EMAC_INTSTS[8]) is set.
  • Page 728 NuMicro NUC442/NUC472 Series Technical Reference Manual Receive FIFO Overflow Interrupt Enable Bit The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation. If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RXOVIEN or RXIEN RXOVIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXOVIF (EMAC_INTSTS[2]) is set.
  • Page 729 NuMicro NUC442/NUC472 Series Technical Reference Manual MAC Interrupt Status Register (EMAC_INTSTS) The EMAC_INTSTS keeps much EMAC statuses, such as frame transmission, reception status and internal FIFO status. The statuses kept in EMAC_INTSTS will trigger the reception or transmission interrupt. The EMAC_INTSTS is a write clear register and write 1 to corresponding bit clears the status and also clears the interrupt.
  • Page 730 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmit Descriptor Unavailable Interrupt The TDUIF high indicates that there is no available TX descriptor for packet transmission and TXDMA will stay at Halt state. Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make TXDMA leave Halt state while new TX descriptor is available.
  • Page 731 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmit FIFO Underflow Interrupt The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission. While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically without S/W intervention. If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, the TXFIFOTH of FFTCR register, to higher level.
  • Page 732 NuMicro NUC442/NUC472 Series Technical Reference Manual Receive Descriptor Unavailable Interrupt The RDUIF high indicates that there is no available RX descriptor for packet reception and RXDMA will stay at Halt state. Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to make RXDMA leave Halt state while new RX descriptor is available.
  • Page 733 NuMicro NUC442/NUC472 Series Technical Reference Manual Long Packet Interrupt Flag The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped. If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
  • Page 734 NuMicro NUC442/NUC472 Series Technical Reference Manual MAC General Status Register (EMAC_GENSTS) The EMAC_GENSTS also keeps the statuses of EMAC. But the statuses in the EMAC_GENSTS will not trigger any interrupt. The EMAC_GENSTS is a write clear register and write 1 to corresponding bit clears the status.
  • Page 735 NuMicro NUC442/NUC472 Series Technical Reference Manual Deferred Transmission The DEF high indicates the packet transmission has deferred once. The DEF is only available while EMAC is operating on half-duplex mode. 0 = Packet transmission does not defer. 1 = Packet transmission has deferred once. Collision Count The COLCNT indicates that how many collisions occurred consecutively during a packet [7:4]...
  • Page 736 NuMicro NUC442/NUC472 Series Technical Reference Manual Missed Packet Count Register (EMAC_MPCNT) The EMAC_MPCNT keeps the number of packets that were dropped due to various types of receive errors. The EMAC_MPCNT is a read clear register. In addition, S/W also can write an initial value to EMAC_MPCNT and the missed packet counter will start counting from that initial value.
  • Page 737 NuMicro NUC442/NUC472 Series Technical Reference Manual MAC Receive Pause Count Register (EMAC_RPCNT) The EMAC supports the PAUSE control frame reception and recognition. If EMAC received a PAUSE control frame, the OPERAND field of the PAUSE control frame will be extracted and stored in the EMAC_RPCNT register.
  • Page 738 NuMicro NUC442/NUC472 Series Technical Reference Manual DMA Receive Frame Status Register (EMAC_FRSTS) The EMAC_FRSTS is used to keep the LENGTH field of each incoming Ethernet packet. Register Offset Description Reset Value EMAC_FRSTS EMAC_BA+0x0C8 R/W DMA Receive Frame Status Register 0x0000_0000 Reserved Reserved RXFLT...
  • Page 739 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Transmit Descriptor Start Address Register (EMAC_CTXDSA) Register Offset R/W Description Reset Value EMAC_CTXDSA EMAC_BA+0x0CC R Current Transmit Descriptor Start Address Register 0x0000_0000 CTXDSA CTXDSA CTXDSA CTXDSA Bits Description Current Transmit Descriptor Start Address [31:0] CTXDSA The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently.
  • Page 740 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Transmit Buffer Start Address Register (EMAC_CTXBSA) Register Offset R/W Description Reset Value EMAC_CTXBSA EMAC_BA+0x0D0 R Current Transmit Buffer Start Address Register 0x0000_0000 CTXBSA CTXBSA CTXBSA CTXBSA Bits Description Current Transmit Buffer Start Address [31:0] CTXBSA The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA...
  • Page 741 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Receive Descriptor Start Address Register (EMAC_CRXDSA) Register Offset R/W Description Reset Value EMAC_CRXDSA EMAC_BA+0x0D4 R Current Receive Descriptor Start Address Register 0x0000_0000 CRXDSA CRXDSA CRXDSA CRXDSA Bits Description Current Receive Descriptor Start Address [31:0] CRXDSA The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently.
  • Page 742 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Receive Buffer Start Address Register (EMAC_CRXBSA) Register Offset R/W Description Reset Value EMAC_CRXBSA EMAC_BA+0x0D8 Current Receive Buffer Start Address Register 0x0000_0000 CRXBSA CRXBSA CRXBSA CRXBSA Bits Description Current Receive Buffer Start Address [31:0] CRXBSA The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently.
  • Page 743 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Control Register (EMAC_TSCTL) Register Offset Description Reset Value EMAC_TSCTL EMAC_BA+0x100 R/W Time Stamp Control Register 0x0000_0000 Reserved Reserved Reserved Reserved TSALMEN Reserved TSUPDATE TSMODE TSIEN TSEN Bits Description Reserved [31:6] Reserved. Time Stamp Alarm Enable Bit Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
  • Page 744 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Counter Initialization Enable Bit Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stampe counter. TSIEN After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
  • Page 745 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Counter Second Register (EMAC_TSSEC) Register Offset Description Reset Value EMAC_TSSEC EMAC_BA+0x110 Time Stamp Counter Second Register 0x0000_0000 Bits Description Time Stamp Counter Second [31:0] This register reflects the bit [63:32] value of 64-bit reference timing counter. This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
  • Page 746 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Counter Sub Second Register (EMAC_TSSUBSEC) Register Offset Description Reset Value EMAC_TSSUBS EMAC_BA+0x114 R Time Stamp Counter Sub Second Register 0x0000_0000 SUBSEC SUBSEC SUBSEC SUBSEC Bits Description Time Stamp Counter Sub-Second This register reflects the bit [31:0] value of 64-bit reference timing counter. This 32-bit [31:0] SUBSEC value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is...
  • Page 747 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Increment Register (EMAC_TSINC) Register Offset Description Reset Value EMAC_TSINC EMAC_BA+0x118 Time Stamp Increment Register 0x0000_0000 Reserved Reserved Reserved CNTINC Bits Description Reserved [31:8] Reserved. Time Stamp Counter Increment Time stamp counter increment value. [7:0] CNTINC If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value...
  • Page 748 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Addend Register (EMAC_TSADDEND) Register Offset Description Reset Value EMAC_TSADD EMAC_BA+0x11C R/W Time Stamp Addend Register 0x0000_0000 ADDEND ADDEND ADDEND ADDEND Bits Description Time Stamp Counter Addend This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
  • Page 749 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Update Second Register (EMAC_UPDSEC) Register Offset Description Reset Value EMAC_UPDSEC EMAC_BA+0x120 R/W Time Stamp Update Second Register 0x0000_0000 Bits Description Time Stamp Counter Second Update When TSIEN (EMAC_TSCTL[1]) is high. EMAC loads this 32-bit value to EMAC_TSSEC [31:0] directly.
  • Page 750 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Update Sub Second Register (EMAC_UPDSUBSEC) Register Offset Description Reset Value EMAC_UPDSUB EMAC_BA+0x124 R/W Time Stamp Update Sub Second Register 0x0000_0000 SUBSEC SUBSEC SUBSEC SUBSEC Bits Description Time Stamp Counter Sub-Second Update When TSIEN (EMAC_TSCTL[1]) is high. EMAC loads this 32-bit value to [31:0] SUBSEC EMAC_TSSUBSEC directly.
  • Page 751 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Alarm Second Register (EMAC_ALMSEC) Register Offset Description Reset Value EMAC_ALMSEC EMAC_BA+0x128 Time Stamp Alarm Second Register 0x0000_0000 Bits Description Time Stamp Counter Second Alarm Time stamp counter second part alarm value. [31:0] This value is only useful when ALMEN (EMAC_TSCTL[5]) high.
  • Page 752 NuMicro NUC442/NUC472 Series Technical Reference Manual Time Stamp Alarm Sub Second Register (EMAC_ALMSUBSEC) Register Offset Description Reset Value EMAC_ALMSUB EMAC_BA+0x12C R/W Time Stamp Alarm Sub Second Register 0x0000_0000 SUBSEC SUBSEC SUBSEC SUBSEC Bits Description Time Stamp Counter Sub-Second Alarm Time stamp counter sub-second part alarm value. This value is only useful when ALMEN (EMAC_TSCTL[5]) high.

  • Page 753: Flash Memory Controller (Fmc)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.13 Flash Memory Controller (FMC) 6.13.1 Overview The NUC442/NUC472 is equipped with 256/512 Kbytes on-chip embedded flash for application program memory (APROM) and data flash that can be updated through ISP procedure. In- System-Programming (ISP) and In-Application-Programming (IAP) enables user to update chip ®...

  • Page 754: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.13.3 Block Diagram The flash memory controller consists of AHB slave interface, ISP control logic and flash macro interface timing control logic. The block diagram of flash memory controller is shown as follows. 6.13.4 Flash Memory Organization The flash memory consists of application program memory (APROM), Data Flash, ISP loader program memory (LDROM), user configuration and user hidden block.

  • Page 755: Figure 6.13-1 Flash Memory Organization

    NuMicro NUC442/NUC472 Series Technical Reference Manual 0 x 0030 _ 03 FF User Configuration 0 x 0030 _ 0000 0 x 0010 _ 3 FFF ISP Loader Program Memory 0 x 0010 _ 0000 Reserved for Further Used ( 512 KB ) 0 x 0007 _ FFFF ( 256 KB ) 0 x 0003 _ FFFF Data Flash DFBADR...

  • Page 756: Boot Selection

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.13.5 Boot Selection The NUC442/NUC472 provides In System Programming (ISP) feature for user to update application program memory (APROM) when chip is soldered on PCB. A dedicated 16 KB ISP loader program memory (LDROM) is used to store ISP firmware. User can select that CPU fetches code from APROM or LDROM by boot select (CBS) in Config0.

  • Page 757: In Application Programming

    NuMicro NUC442/NUC472 Series Technical Reference Manual 0x0010_3FFF ISP Loader Program Memory ISP Loader Program Memory (LDROM 16KB) (LDROM 16KB) Reserved 0x0010_0000 Reserved Reserved Reserved (512 KB) 0x0007_FFFF (512 KB) 0x0007_FFFF (256 KB) 0x0003_FFFF (256 KB) 0x0003_FFFF Data Flash Data Flash Data Flash DFBADR DFBADR...

  • Page 758: Data Flash

    NuMicro NUC442/NUC472 Series Technical Reference Manual 0x0010_3FFF 0x0010_3FFF LDROM LDROM (16K) (16K) 0x0010_0000 0x0010_0000 LDROM first page Reserved Reserved Default remap structure APROM APROM 0x0000_0000 0x0000_0000 LDROM first page CBS = 10b CBS = 00b Figure 6.13-3 Executable Range of Code with IAP Function Enabled When chip boots with the IAP function enabled, any other page within the executable range of code can be mirrored to the first page of executable code (0x0000_0000~0x0000_07FF) any time.

  • Page 759: Figure 6.13-4 Flash Memory Structure

    NuMicro NUC442/NUC472 Series Technical Reference Manual 0x0007_FFFF Data Flash 2*N K bytes DFBADR Programmable start address Reserved Note: N is the number of 0x0003_FFFF page Data Flash 2*N K bytes DFBADR Programmable start Application Program address (512-2*N) K bytes Application Program (256-2*N) K bytes 0x0000_0000 0x0000_0000...

  • Page 760: User Configuration

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.13.8 User Configuration Config0 (Address = 0x0030_0000) CWDTEN CWDTPDEN Reserved CFGXT1 CFOSC CBODEN CBOV1 CBOV0 CBORST Reserved RMII CFG32K Reserved LDWPEN CIOINI Reserved Reserved LOCK DFEN Bits Field Description Watchdog hardware Enable Bit CWDTEN 0 = Window Watchdog Timer Enabled when chip is powered on.
  • Page 761 NuMicro NUC442/NUC472 Series Technical Reference Manual Brown-out Voltage Selection 00 = 2.2V CBOV1-0 01 = 2.7V [22:21] 10 = 3.7V 11 = 4.5V Brown-out Reset Enable Bit [20] CBORST 0 = Brown-out reset Enabled after powered on. 1 = Brown-out reset Disabled after powered on. [19:16] Reserved Reserved.
  • Page 762 NuMicro NUC442/NUC472 Series Technical Reference Manual Config1 (Address = 0x0030_0004) Reserved Reserved DFBADR.19 DFBADR.18 DFBADR.17 DFBADR.16 DFBADR.15 DFBADR.14 DFBADR.13 DFBADR.12 DFBADR.11 DFBADR.10 DFBADR.9 DFBADR.8 DFBADR.7 DFBADR.6 DFBADR.5 DFBADR.4 DFBADR.3 DFBADR.2 DFBADR.1 DFBADR.0 Bits Field Description Reserved [31:20] Reserved. Data Flash Base Address (This register works only when DFEN set to 0) [19:0] DFBADR If DFEN is set to 0, the data flash base address is defined by user.
  • Page 763 NuMicro NUC442/NUC472 Series Technical Reference Manual Config2 (Address = 0x0030_0008) BWP31 BWP30 BWP29 BWP28 BWP27 BWP26 BWP25 BWP24 BWP23 BWP22 BWP21 BWP20 BWP19 BWP18 BWP17 BWP16 BWP15 BWP14 BWP13 BWP12 BWP11 BWP10 BWP9 BWP8 BWP7 BWP6 BWP5 BWP4 BWP3 BWP2 BWP1 BWP0 Bits...
  • Page 764 NuMicro NUC442/NUC472 Series Technical Reference Manual Config3 (Address = 0x0030_000C) CFGCHECKSUM[31:24] CFGCHECKSUM[23:16] CFGCHECKSUM[15:8] CFGCHECKSUM[7:0] Bits Field Description User Configuration CRC Checksum If Config0~Config2 are not 0xFFFF_FFFF, Config3 needs to program the correct CRC checksum value; otherwise, if the CRC checksum value is not correct, this chip will enter lock protect mode automatically.

  • Page 765: In System Program (Isp)

    Then LDROM firmware receives it and re-programs into APROM through ISP commands. The ISP firmware and PC application program for the NUC442/NUC472 series enables user to easily perform ISP through Nuvoton ISP tool. 6.13.10 ISP Procedure The NUC442/NUC472 supports booting from APROM or LDROM initially defined by user configuration bits (CBS).
  • Page 766 NuMicro NUC442/NUC472 Series Technical Reference Manual Power CBS[0] = 1 ? CBS[1] = 1 ? Enable ISPEN Write FMC_ISPADR/FMC_IS Fetch code from Fetch code from PCMD/FMC_ISPDAT? LDROM APROM Set FMC_ISPGO = 1 Update LDROM or write Execute ISP? Data Flash End of Flash Operation (Read FMC_ISPDAT) &...
  • Page 767 NuMicro NUC442/NUC472 Series Technical Reference Manual Enable ISPEN Enable ISPEN Select Vector Page CBS[1] = 1 ? Write FMC_ISPADR/ Write ISPCMD FMC_ISPCMD/ (Vector Page Re-Map) FMC_ISPDAT ? Page 0 is mapping to APROM Page 0 is mapping to LD-ROM Page 0 is mapping to LDROM Fetch code from APROM Fetch code from LD-ROM Fetch code from LDROM...

  • Page 768: Table 6.13-3 Isp Mode Command

    NuMicro NUC442/NUC472 Series Technical Reference Manual ISPCMD ISPADR ISPDAT ISP Mode CMD[3:0] A[19:0] D[31:0] Address in FLASH Page Erase 0010 0xFFFF_FFFF A[19:0] Address in Data in FLASH Program 0001 A[19:0] D[31:0] Address in Data out FLASH Read 0000 A[19:0] D[31:0] Address in CONFIG Page Erase 0010...

  • Page 769: Flash Control Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.13.11 Flash Control Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value FMC Base Address: FMC_BA = 0x4000_C000 FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0000_0000 FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000...

  • Page 770: Flash Control Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.13.12 Flash Control Register Description ISP Control Register (FMC_ISPCTL) Register Offset Description Reset Value FMC_ISPCTL FMC_BA+0x00 ISP Control Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF LDUEN CFGUEN APUEN Reserved ISPEN Bits Description [31:7] Reserved Reserved.
  • Page 771 NuMicro NUC442/NUC472 Series Technical Reference Manual Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened 0 = Boot from APROM.
  • Page 772 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Address (FMC_ISPADDR) Register Offset Description Reset Value FMC_ISPADDR FMC_BA+0x04 ISP Address Register 0x0000_0000 ISPADDR[31:24] ISPADDR[23:16] ISPADDR[15:8] ISPADDR[7:0] Bits Description ISP Address [31:0] ISPADDR The NUC442/NUC472 series is equipped with an embedded flash and supports word program only.
  • Page 773 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Data Register (FMC_ISPDAT) Register Offset Description Reset Value FMC_ISPDAT FMC_BA+0x08 ISP Data Register 0x0000_0000 ISPDAT[31:24] ISPDAT [23:16] ISPDAT [15:8] ISPDAT [7:0] Bits Description ISP Data [31:0] ISPDAT Write data to this register before ISP program operation. Read data from this register after ISP read operation.
  • Page 774 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Command (FMC_ISPCMD) Register Offset Description Reset Value FMC_ISPCMD FMC_BA+0x0C ISP Command Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:6] Reserved Reserved. ISP Command [5:0] Please check the table below for ISP commands. ISP command table: Operation Mode 32b Read...
  • Page 775 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Trigger Register (FMC_ISPTRG) Register Offset Description Reset Value FMC_ISPTRG FMC_BA+0x10 ISP Trigger Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPGO Bits Description [31:1] Reserved Reserved. ISP Start Trigger Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
  • Page 776 NuMicro NUC442/NUC472 Series Technical Reference Manual Data Flash Base Address Register (FMC_DFBA) Register Offset Description Reset Value FMC_DFBA FMC_BA+0x14 Data Flash Base Address 0xXXXX_XXXX DFBA[31:23] DFBA[23:16] DFBA[15:8] DFBA[7:0] Bits Description Data Flash Base Address This register indicates data flash start address. It is a read only register. [31:0] DFBA The data flash is shared with APROM and data flash size is defined by user configuration...
  • Page 777 NuMicro NUC442/NUC472 Series Technical Reference Manual Flash Access Time Control Register (FMC_FTCTL) Register Offset Description Reset Value FMC_FTCTL FMC_BA+0x18 Flash Access Time Control Register 0x0000_0000 Reserved Reserved Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. Frequency Optimization Mode (Write Protect) When chip operation frequency is lower, chip can work more efficiently by setting FOM bits FOM[2:0]...
  • Page 778 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Status Register (FMC_ISPSTS) Register Offset Description Reset Value FMC_ISPSTS FMC_BA+0x40 ISP Status Register 0x0000_0000 Reserved CFGCRCF Reserved Reserved VECMAP[11:7] VECMAP[6:0] Reserved Reserved ISPFF Reserved ISPBUSY Bits Description [31:27] Reserved Reserved. User-Configuration CRC Check Flag (Read Only) This bit is set by hardware when detecting CONFIG CRC checksum is error [26] CFGCRCF...
  • Page 779 NuMicro NUC442/NUC472 Series Technical Reference Manual Flash Block Write Protect Control Register (FMC_FBWP) Register Offset Description Reset Value FMC_FBWP FMC_BA+0x44 Flash Block Write Protect Control Register 0xXXXX_XXXX BWP31 BWP30 BWP29 BWP28 BWP27 BWP26 BWP25 BWP24 BWP23 BWP22 BWP21 BWP20 BWP19 BWP18 BWP17 BWP16...
  • Page 780 NuMicro NUC442/NUC472 Series Technical Reference Manual This register is also a protected bit which means programming this bit needs to write “59h”, “16h”, “88h” to address GCR_BA+0x100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100 May 23, 2014 Page 780 of 1386 Rev.1.05...
  • Page 781 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Multi-Word Program Data 0 Register (FMC_MPDAT0) Register Offset Description Reset Value FMC_MPDAT0 FMC_BA+0x80 ISP Multi-Word Program Data 0 Register 0x0000_0000 ISPDAT0 [31:24] ISPDAT0 [23:16] ISPDAT0 [15:8] ISPDAT0 [7:0] Bits Description ISP Data 0 [31:0] ISPDAT0 This register is the first 32-bit data for 32b/64b/multi-word program, and it is also the mirror...
  • Page 782 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Multi-Word Program Data 1 Register (FMC_MPDAT1) Register Offset Description Reset Value FMC_MPDAT1 FMC_BA+0x84 ISP Multi-Word Program Data 1 Register 0x0000_0000 ISPDAT1 [31:24] ISPDAT1 [23:16] ISPDAT1 [15:8] ISPDAT1 [7:0] Bits Description ISP Data 1 ISPDAT1 [31:0] This register is the second 32-bit data for 32b/64b/multi-word program.
  • Page 783 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Multi-Word Program Data 2 Register (FMC_MPDAT2) Register Offset Description Reset Value FMC_MPDAT2 FMC_BA+0x88 ISP Multi-Word Program Data 2 Register 0x0000_0000 ISPDAT2 [31:24] ISPDAT2 [23:16] ISPDAT2 [15:8] ISPDAT2 [7:0] Bits Description ISP Data 2 ISPDAT2 [31:0] This register is the third 32-bit data for 32b/64b/multi-word program.
  • Page 784 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Multi-Word Program Data 3 Register (FMC_MPDAT3) Register Offset Description Reset Value FMC_MPDAT3 FMC_BA+0x8C ISP Multi-Word Program Data 3 Register 0x0000_0000 ISPDAT3 [31:24] ISPDAT3 [23:16] ISPDAT3 [15:8] ISPDAT3 [7:0] Bits Description ISP Data 3 ISPDAT3 [31:0] This register is the fourth 32-bit data for 32b/64b/multi-word program.
  • Page 785 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Multi-Word Program Status Register (FMC_MPSTS) Register Offset Description Reset Value FMC_MPSTS FMC_BA+0xC0 ISP Multi-Word Program Status Register 0x0000_0000 Reserved Reserved Reserved Reserved ISPFF Reserved MPBUSY Bits Description [31:8] Reserved Reserved. ISP DATA 3 Flag (Read Only) This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 is programmed to flash complete.
  • Page 786 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Multi-Word Program Busy Flag (Read Only) MPBUSY 0 = ISP Multi-Word Program operation is aborted or finished. 1 = ISP Multi-Word Program operation is progressed. May 23, 2014 Page 786 of 1386 Rev.1.05...
  • Page 787 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Multi-Word Program Address Status (FMC_MPADDR) Register Offset Description Reset Value FMC_MPADDR FMC_BA+0xC4 ISP Multi-Word Program Address Status Register 0x0000_0000 MPADDR[31:24] MPADDR[23:16] MPADDR[15:8] MPADDR[7:0] Bits Description ISP Multi-Word Program Address Status [31:0] MPADDR MPADDR is the address of ISP Multi-Word Program operation when MPBUSY flag is 1. MPADDR will keep the final address when Multi-Word Program is aborted or finished.
  • Page 788 NuMicro NUC442/NUC472 Series Technical Reference Manual ISP Multi-Program Write FMC_ISPCTL Write FMC_ISPADDR Write FMC_MPDAT0 Write FMC_MPDAT1 Write FMC_MPDAT2 Write FMC_MPDAT3 Write FMC_ISPCMD Write FMC_ISPTRG Data Finish? Read FMC_MPSTS Read FMC_MPSTS Check {D1,D0} == 00? MPBUSY==0? Read FMC_MPADDR MPBUSY == 0? ISP Multi-Program Finish Write FMC_MPDAT0...

  • Page 789: General Purpose I/O (Gpio)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.14 General Purpose I/O (GPIO) 6.14.1 Overview The NUC442/NUC472 series has up to 114/144 General Purpose I/O pins shared with other function pins depending on the chip configuration. These 114/144 pins are arranged in 8/9 ports named GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI (NUC472 only).

  • Page 790: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.14.3 Functional Description 6.14.3.1 Input Mode Set Px_MODE (MODEn[1:0]) to 00b and the GPIOx port [n] pin is in Input mode and the I/O pin is in tri-state (high impedance) without output drive capability. The Px_PIN value reflects the status of the corresponding port pins.

  • Page 791: Figure 6.14-3 Quasi-Bidirectional I/O Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.14.3.4 Quasi-bidirectional Mode Set Px_MODE (MODEn[1:0]) to 11b the GPIOx port [n] pin is in Quasi-bidirectional mode and the I/O pin supports digital output and input function at the same time but the source current is only up to hundreds uA.

  • Page 792: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.14.4 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value GPIO Base Address: GPIO_BA = 0x4000_4000 PA_MODE GPIO_BA+0x000 R/W PA I/O Mode Control 0xFFFF_FFFF PA_DINOFF GPIO_BA+0x004 R/W PA Digital Input Path Disable Control 0x0000_0000...
  • Page 793 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value PC_DATMSK GPIO_BA+0x08C R/W PC Data Output Write Mask 0x0000_0000 PC_PIN GPIO_BA+0x090 R PC Pin Value 0x0000_XXXX PC_DBEN GPIO_BA+0x094 R/W PC De-Bounce Enable Control 0x0000_0000 PC_INTTYPE GPIO_BA+0x098 R/W PC Interrupt Trigger Type Register 0x0000_0000 PC_INTEN GPIO_BA+0x09C R/W...
  • Page 794 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value PE_SMTEN GPIO_BA+0x124 R/W PE Input Schmitt Trigger Enable 0x0000_0000 PE_SLEWCTL GPIO_BA+0x128 R/W PE High Slew Rate Control 0x0000_0000 PF_MODE GPIO_BA+0x140 R/W PF I/O Mode Control 0xFFFF_FFFF PF_DINOFF GPIO_BA+0x144 R/W PF Digital Input Path Disable Control 0x0000_0000 PF_DOUT...
  • Page 795 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value PH_DBEN GPIO_BA+0x1D4 R/W PH De-Bounce Enable Control 0x0000_0000 PH_INTTYPE GPIO_BA+0x1D8 R/W PH Interrupt Trigger Type Register 0x0000_0000 GPIO_BA+0x1D PH_INTEN PH Interrupt Enable 0x0000_0000 PH_INTSRC GPIO_BA+0x1E0 R/W PH Interrupt Source Flag 0x0000_XXXX PH_SMTEN GPIO_BA+0x1E4 R/W...
  • Page 796 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value PA11_PDIO GPIO_BA+0x82C R/W GPIO PA.n Pin Data Input/Output 0x0000_0001 PA12_PDIO GPIO_BA+0x830 R/W GPIO PA.n Pin Data Input/Output 0x0000_0001 PA13_PDIO GPIO_BA+0x834 R/W GPIO PA.n Pin Data Input/Output 0x0000_0001 PA14_PDIO GPIO_BA+0x838 R/W GPIO PA.n Pin Data Input/Output 0x0000_0001 PA15_PDIO...
  • Page 797 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value PC8_PDIO GPIO_BA+0x8A0 R/W GPIO PC.n Pin Data Input/Output 0x0000_0001 PC9_PDIO GPIO_BA+0x8A4 R/W GPIO PC.n Pin Data Input/Output 0x0000_0001 PC10_PDIO GPIO_BA+0x8A8 R/W GPIO PC.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x8A PC11_PDIO GPIO PC.n Pin Data Input/Output 0x0000_0001 PC12_PDIO...
  • Page 798 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value PE4_PDIO GPIO_BA+0x910 R/W GPIO PE.n Pin Data Input/Output 0x0000_0001 PE5_PDIO GPIO_BA+0x914 R/W GPIO PE.n Pin Data Input/Output 0x0000_0001 PE6_PDIO GPIO_BA+0x918 R/W GPIO PE.n Pin Data Input/Output 0x0000_0001 PE7_PDIO GPIO_BA+0x91C R/W GPIO PE.n Pin Data Input/Output 0x0000_0001 PE8_PDIO...
  • Page 799 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value PG1_PDIO GPIO_BA+0x984 R/W GPIO PG.n Pin Data Input/Output 0x0000_0001 PG2_PDIO GPIO_BA+0x988 R/W GPIO PG.n Pin Data Input/Output 0x0000_0001 PG3_PDIO GPIO_BA+0x98C R/W GPIO PG.n Pin Data Input/Output 0x0000_0001 PG4_PDIO GPIO_BA+0x990 R/W GPIO PG.n Pin Data Input/Output 0x0000_0001 PG5_PDIO...
  • Page 800 NuMicro NUC442/NUC472 Series Technical Reference Manual Register Offset Description Reset Value PH13_PDIO GPIO_BA+0x9F4 R/W GPIO PH.n Pin Data Input/Output 0x0000_0001 PH14_PDIO GPIO_BA+0x9F8 R/W GPIO PH.n Pin Data Input/Output 0x0000_0001 PH15_PDIO GPIO_BA+0x9FC R/W GPIO PH.n Pin Data Input/Output 0x0000_0001 PI0_PDIO GPIO_BA+0xA00 R/W GPIO PI.n Pin Data Input/Output 0x0000_0001 PI1_PDIO...

  • Page 801: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.14.5 Register Description GPIO Port n I/O Mode Control Register Offset Description Reset Value PA_MODE GPIO_BA+0x000 PA I/O Mode Control 0xFFFF_FFFF PB_MODE GPIO_BA+0x040 PB I/O Mode Control 0xFFFF_FFFF PC_MODE GPIO_BA+0x080 PC I/O Mode Control 0xFFFF_FFFF PD_MODE GPIO_BA+0x0C0 R/W...
  • Page 802 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n Digital Input Path Disable Register Offset Description Reset Value PA_DINOFF GPIO_BA+0x004 PA Digital Input Path Disable Control 0x0000_0000 PB_DINOFF GPIO_BA+0x044 PB Digital Input Path Disable Control 0x0000_0000 PC_DINOFF GPIO_BA+0x084 PC Digital Input Path Disable Control 0x0000_0000 PD_DINOFF GPIO_BA+0x0C4 R/W...
  • Page 803 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n Data Output Register Offset Description Reset Value GPIO_BA+0x00 PA_DOUT PA Data Output Value 0x0000_FFFF GPIO_BA+0x04 PB_DOUT PB Data Output Value 0x0000_FFFF GPIO_BA+0x08 PC_DOUT PC Data Output Value 0x0000_FFFF GPIO_BA+0x0C PD_DOUT PD Data Output Value 0x0000_FFFF GPIO_BA+0x10 PE_DOUT...
  • Page 804 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n Data Output Write Mask Register Offset Description Reset Value GPIO_BA+0x00 PA_DATMSK PA Data Output Write Mask 0x0000_0000 GPIO_BA+0x04 PB_DATMSK PB Data Output Write Mask 0x0000_0000 GPIO_BA+0x08 PC_DATMSK PC Data Output Write Mask 0x0000_0000 GPIO_BA+0x0C PD_DATMSK...
  • Page 805 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n Pin Value Register Offset Description Reset Value GPIO_BA+0x01 PA_PIN PA Pin Value 0x0000_XXXX GPIO_BA+0x05 PB_PIN PB Pin Value 0x0000_XXXX GPIO_BA+0x09 PC_PIN PC Pin Value 0x0000_XXXX GPIO_BA+0x0D PD_PIN PD Pin Value 0x0000_XXXX GPIO_BA+0x11 PE_PIN PE Pin Value...
  • Page 806 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n De-bounce Enable Register Offset Description Reset Value PA_DBEN GPIO_BA+0x014 R/W PA De-Bounce Enable Control 0x0000_0000 PB_DBEN GPIO_BA+0x054 R/W PB De-Bounce Enable Control 0x0000_0000 PC_DBEN GPIO_BA+0x094 R/W PC De-Bounce Enable Control 0x0000_0000 PD_DBEN GPIO_BA+0x0D4 R/W PD De-Bounce Enable Control...
  • Page 807 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n Interrupt Trigger Type Register Offset Description Reset Value GPIO_BA+0x01 PA_INTTYPE PA Interrupt Trigger Type Register 0x0000_0000 GPIO_BA+0x05 PB_INTTYPE PB Interrupt Trigger Type Register 0x0000_0000 GPIO_BA+0x09 PC_INTTYPE PC Interrupt Trigger Type Register 0x0000_0000 GPIO_BA+0x0D PD_INTTYPE...
  • Page 808 NuMicro NUC442/NUC472 Series Technical Reference Manual is level triggered, the de-bounce enable bit is ignored. May 23, 2014 Page 808 of 1386 Rev.1.05...
  • Page 809 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n Interrupt Enable Register Offset Description Reset Value GPIO_BA+0x01 PA_INTEN PA Interrupt Enable 0x0000_0000 GPIO_BA+0x05 PB_INTEN PB Interrupt Enable 0x0000_0000 GPIO_BA+0x09 PC_INTEN PC Interrupt Enable 0x0000_0000 GPIO_BA+0x0D PD_INTEN PD Interrupt Enable 0x0000_0000 GPIO_BA+0x11 PE_INTEN PE Interrupt Enable...
  • Page 810 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n Interrupt Source Flag Register Offset Description Reset Value GPIO_BA+0x02 PA_INTSRC PA Interrupt Source Flag 0x0000_XXXX GPIO_BA+0x06 PB_INTSRC PB Interrupt Source Flag 0x0000_XXXX GPIO_BA+0x0A PC_INTSRC PC Interrupt Source Flag 0x0000_XXXX GPIO_BA+0x0E PD_INTSRC PD Interrupt Source Flag 0x0000_XXXX GPIO_BA+0x12...
  • Page 811 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n Input Schmitt Trigger Enable Register Offset Description Reset Value GPIO_BA+0x02 PA_SMTEN PA Input Schmitt Trigger Enable 0x0000_0000 GPIO_BA+0x06 PB_SMTEN PB Input Schmitt Trigger Enable 0x0000_0000 GPIO_BA+0x0A PC_SMTEN PC Input Schmitt Trigger Enable 0x0000_0000 GPIO_BA+0x0E PD_SMTEN...
  • Page 812 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n High Slew Rate Control Register Offset Description Reset Value GPIO_BA+0x02 PA_SLEWCTL PA High Slew Rate Control 0x0000_0000 GPIO_BA+0x06 PB_SLEWCTL PB High Slew Rate Control 0x0000_0000 GPIO_BA+0x0A PC_SLEWCTL PC High Slew Rate Control 0x0000_0000 GPIO_BA+0x0E PD_SLEWCTL...
  • Page 813 NuMicro NUC442/NUC472 Series Technical Reference Manual Interrupt De-bounce Cycle Control (GPIO_DBCTL ) Register Offset Description Reset Value GPIO_DBCTL GPIO_BA+0x440 R/W Interrupt De-bounce Control 0x0000_0020 Reserved Reserved Reserved Reserved ICLKON DBCLKSRC DBCLKSEL Bits Description [31:6] Reserved Reserved. Interrupt Clock On Mode Setting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled.
  • Page 814 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO Port n Bit m I/O value Register Offset Description Reset Value GPIO_BA+0x80 PA0_PDIO GPIO PA.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x80 PA1_PDIO GPIO PA.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x80 PA2_PDIO GPIO PA.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x80 PA3_PDIO...
  • Page 815 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO_BA+0x85 PB6_PDIO GPIO PB.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x85 PB7_PDIO GPIO PB.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x86 PB8_PDIO GPIO PB.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x86 PB9_PDIO GPIO PB.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x86 PB10_PDIO GPIO PB.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x86...
  • Page 816 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO_BA+0x8B PC12_PDIO GPIO PC.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x8B PC13_PDIO GPIO PC.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x8B PC14_PDIO GPIO PC.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x8B PC15_PDIO GPIO PC.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x8C PD0_PDIO GPIO PD.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x8C...
  • Page 817 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO_BA+0x90 PE3_PDIO GPIO PE.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x91 PE4_PDIO GPIO PE.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x91 PE5_PDIO GPIO PE.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x91 PE6_PDIO GPIO PE.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x91 PE7_PDIO GPIO PE.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x92...
  • Page 818 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO_BA+0x96 PF10_PDIO GPIO PF.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x96 PF11_PDIO GPIO PF.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x97 PF12_PDIO GPIO PF.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x97 PF13_PDIO GPIO PF.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x97 PF14_PDIO GPIO PF.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x97...
  • Page 819 NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO_BA+0x9C PH1_PDIO GPIO PH.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x9C PH2_PDIO GPIO PH.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x9C PH3_PDIO GPIO PH.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x9D PH4_PDIO GPIO PH.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x9D PH5_PDIO GPIO PH.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0x9D...

  • Page 820: I 2 C Serial Interface Controller (Master/Slave)

    NuMicro NUC442/NUC472 Series Technical Reference Manual GPIO_BA+0xA2 PI8_PDIO GPIO PI.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0xA2 PI9_PDIO GPIO PI.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0xA2 PI10_PDIO GPIO PI.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0xA2 PI11_PDIO GPIO PI.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0xA3 PI12_PDIO GPIO PI.n Pin Data Input/Output 0x0000_0001 GPIO_BA+0xA3...

  • Page 821: Overview

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.15.1 Overview C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.

  • Page 822: Features

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.15.2 Features The I C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are:  Master/Slave mode  Bidirectional data transfer between masters and slaves ...

  • Page 823: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.15.3 Functional Description 6.15.3.1 C Protocol Normally, a standard communication consists of four parts: 1) START or Repeated START signal generation 2) Slave address and R/W bit transfer 3) Data transfer 4) STOP signal generation ADDRESS DATA DATA...

  • Page 824: Figure 6.15-4 Master Reads Data From Slave

    NuMicro NUC442/NUC472 Series Technical Reference Manual SLAVE ADDRESS DATA DATA data transfer ‘1’ : read (n bytes + acknowlegde) Figure 6.15-4 Master Reads Data from Slave 6.15.3.3 START or Repeated START signal and STOP signal When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal.

  • Page 825: Operation Modes

    NuMicro NUC442/NUC472 Series Technical Reference Manual Data line stable; Change of data data valid allowed Figure 6.15-6 Bit Transfer on I C Bus Clock pulse for acknowledgement from master data output by transmitter not acknowlegde data output by receiver acknowlegde START condition Figure 6.15-7 Acknowledge on I...

  • Page 826: Figure 6.15-8 Control I

    NuMicro NUC442/NUC472 Series Technical Reference Manual The bits, STA, STO and AA in I2C_CTL register are used to control the next state of the I hardware after SI flag of I2C_CTL [3] register is cleared. Upon completion of the new action, a new status code will be updated in I2C_STATUS register and the SI flag of I2C_CTL register will be set.

  • Page 827: Figure 6.15-9 Master Transmitter Mode Control Flow

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.15-9 Master Transmitter Mode Control Flow May 23, 2014 Page 827 of 1386 Rev.1.05...

  • Page 828: Figure 6.15-10 Master Receiver Mode Control Flow

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.15-10 Master Receiver Mode Control Flow If the I C is in Master mode and gets arbitration lost, the status code will be 0x38. In status 0x38, user may set (STA, STO, SI, AA) = (1, 0, 1, X) to send START to re-start Master operation when bus become free.

  • Page 829: Figure 6.15-11 Slave Mode Control Flow

    NuMicro NUC442/NUC472 Series Technical Reference Manual (Master want to write data to Slave) after arbitration lost, the status code is 0x68. If the detected address is SLA+R (Master want to read data from Slave) after arbitration lost, the status code is 0xB0.
  • Page 830 NuMicro NUC442/NUC472 Series Technical Reference Manual If I C is still transmitting data in addressed Slave mode but got a STOP or Repeat START, the status code will be 0xA0. User could follow the action for status code 0xC8 as shown in the above figure when getting 0xA0 status.

  • Page 831: Figure 6.15-12 Gc Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual Figure 6.15-12 GC Mode If I C is still receiving data in GC mode but got a STOP or Repeat START, the status code will be 0xA0. User could follow the action for status code 0x98 in above figure when getting 0xA0 status. Note: After slave gets status of 0x98 and 0xA0, slave can switch to not address mode and own SLA will not be recognized.

  • Page 832: Figure 6.15-13 Eeprom Random Read

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.15.4.4 Multi-Master In some applications, there are two or more masters on the same I C bus to access slaves, and the masters may transmit data simultaneously. The I C supports multi-master by including collision detection and arbitration to prevent data corruption.

  • Page 833: Protocol Registers

    NuMicro NUC442/NUC472 Series Technical Reference Manual The following figure shows how to use I C controller to implement the protocol of EEPROM random read. Figure 6.15-14 Protocol of EEPROM Random Read The I C controller sends START to bus to be a master. Then it sends a SLA+W (Slave address + Write bit) to EERPOM followed by two bytes data address to set the EEPROM address to read.

  • Page 834: Figure 6.15-15 I 2 C Data Shifting Direction

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.15.5.1 Address Registers (I2CADDR) The I C port is equipped with four slave address registers I2C_ADDRn (n=0~3). The contents of the register are irrelevant when I C is in Master mode. In the slave mode, the bit field I2C_ADDRn[7:1] must be loaded with the chip’s own slave address.
  • Page 835 NuMicro NUC442/NUC472 Series Technical Reference Manual I2CEN Set to enable I C serial function controller. When I2CEN=1 the I C serial function enables. The Multi-function pin function of SDA and SCL must be set to I C function. C START Control Bit. Setting STA to logic 1 to enter Master mode, the I C hardware sends a START or repeat START condition to bus when the bus is free.

  • Page 836: Figure 6.15-16 I 2 C Time-Out Count Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 0x48 Master Receive Address NACK 0x80 Slave Receive Data ACK 0x50 Master Receive Data ACK 0x88 Slave Receive Data NACK 0x58 Master Receive Data NACK 0x70 GC mode Address ACK 0x00 Bus error 0x78 GC mode Arbitration Lost 0x90 GC mode Data ACK...
  • Page 837 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.15.5.7 The I C wake-up control Register (I2C_WKCTL) When entering sleep mode, other I C master can wake up our chip by addressing our I C device, user must configure the related setting before entering sleep mode. WKUPEN enables I C wake-up function 6.15.5.8...

  • Page 838: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.15.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value I2C Base Address: I2Cx_BA = 0x4008_0000 + x * 0x1000 x=0,1..4 I2C_CTL I2Cx_BA+0x00 C Control Register 0x0000_0000 I2C_ADDR0 I2Cx_BA+0x04...

  • Page 839: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.15.7 Register Description C Control Register (I2C_CTL) Register Offset Description Reset Value I2C_CTL I2Cx_BA+0x00 C Control Register 0x0000_0000 Reserved Reserved Reserved INTEN I2CEN Reserved Bits Description [31:8] Reserved Reserved. C Interrupt Enable Bit INTEN 0 = I C interrupt Disabled.
  • Page 840 NuMicro NUC442/NUC472 Series Technical Reference Manual acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. [1:0] Reserved Reserved. May 23, 2014 Page 840 of 1386 Rev.1.05...
  • Page 841 NuMicro NUC442/NUC472 Series Technical Reference Manual C Data Register (I2C_DAT) Register Offset Description Reset Value I2C_DAT I2Cx_BA+0x08 C Data Register 0x0000_0000 Reserved Reserved Reserved Bits Description [31:8] Reserved Reserved. C Data Bits [7:0] Bit [7:0] is located with the 8-bit transferred data of I C serial port.
  • Page 842 NuMicro NUC442/NUC472 Series Technical Reference Manual C Status Register (I2C_STATUS ) Register Offset Description Reset Value I2C_STATUS I2Cx_BA+0x0C C Status Register 0x0000_00F8 Reserved Reserved Reserved STATUS[7:3] Bits Description [31:8] Reserved Reserved. C Status Bits The status register of I [7:0] STATUS The three least significant bits are always 0.
  • Page 843 NuMicro NUC442/NUC472 Series Technical Reference Manual C Clock Divided Register (I2C_CLKDIV) Register Offset Description Reset Value I2C_CLKDIV I2Cx_BA+0x10 C Clock Divided Register 0x0000_0000 Reserved Reserved Reserved DIVIDER Bits Description [31:8] Reserved Reserved. C Clock Divided Bits [7:0] DIVIDER The I C clock rate bits: Data Baud Rate of I C = (system clock) / (4x (DIVIDER+1)).
  • Page 844 NuMicro NUC442/NUC472 Series Technical Reference Manual C Time-out Counter Register (I2C_TOCTL) Register Offset Description Reset Value I2C_TOCTL I2Cx_BA+0x14 C Time-out Control Register 0x0000_0000 Reserved Reserved Reserved Reserved TOCEN TOCDIV4 TOIF Bits Description [31:3] Reserved Reserved. Time-Out Counter Enable Bit 0 = Disabled. TOCEN 1 = Enabled.
  • Page 845 NuMicro NUC442/NUC472 Series Technical Reference Manual C Slave Address Register (I2CADDRx) Register Offset Description Reset Value I2CADDR0 I2Cx_BA+0x04 C Slave Address Register0 0x0000_0000 I2C_ADDR1 I2Cx_BA+0x18 C Slave Address Register1 0x0000_0000 I2C_ADDR2 I2Cx_BA+0x1C C Slave Address Register2 0x0000_0000 I2C_ADDR3 I2Cx_BA+0x20 C Slave Address Register3 0x0000_0000 Reserved Reserved...
  • Page 846 NuMicro NUC442/NUC472 Series Technical Reference Manual C Slave Address Mask Register (I2CADMx) Register Offset Description Reset Value I2C_ADDRMSK0 I2Cx_BA+0x24 C Slave Address Mask Register0 0x0000_0000 I2C_ADDRMSK1 I2Cx_BA+0x28 C Slave Address Mask Register1 0x0000_0000 I2C_ADDRMSK2 I2Cx_BA+0x2C C Slave Address Mask Register2 0x0000_0000 I2C_ADDRMSK3 I2Cx_BA+0x30 C Slave Address Mask Register3...
  • Page 847 NuMicro NUC442/NUC472 Series Technical Reference Manual C Wake-up Control Register (I2C_WKCTL) Register Offset Description Reset Value I2C_WKCTL I2Cx_BA+0x3C C Wake-up Control Register 0x0000_0000 Reserved Reserved Reserved Reserved WKEN Bits Description [31:1] Reserved Reserved. C Wake-Up Enable Bit WKEN 0 = I C wake-up function Disabled.
  • Page 848 NuMicro NUC442/NUC472 Series Technical Reference Manual C Wake-up Status Register (I2C_WKSTS) Register Offset Description Reset Value I2C_WKSTS I2Cx_BA+0x40 C Wake-up Status Register 0x0000_0000 Reserved Reserved Reserved Reserved WKIF Bits Description [31:1] Reserved Reserved. C Wake-Up Flag 0 = No wake up occurred. WKIF 1 = Wake up from Power-down mode.

  • Page 849: I 2 S Controller (I 2 S)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.16 S Controller (I 6.16.1 Overview The I S controller consists of IIS protocol to interface with external audio CODEC. Two 8 word deep FIFO for read path and write path respectively and is capable of handling 8/16/24/32 bits word sizes.

  • Page 850: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.16.3 Block Diagram S_Clock_Select S_Clock_Enable HIRC I2S_CLK HCLK PLL FOUT HIRC: 22.1184 High Speed Internal RC oscillator HXT: External Crystal Clock Figure 6.16-1 I S Clock Control Diagram I2SMCLK I2S_CLK_GEN I2SLRCLK Transmit Contrl I2SDO Tx Shift Register &...

  • Page 851: Timing Diagram Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.16.4 Timing Diagram Description 6.16.4.1 S Operation I2SBCLK I2SLRCLK I2SDI / I2SDO word N-1 word N word N+1 right channel left channel right channel Figure 6.16-3 I S Bus Timing Diagram (PCM = 0, Format = 0) I2SBCLK I2SLRCLK I2SDI / I2SDO...

  • Page 852: Figure 6.16-6 Pcm B Audio Timing Diagram (Pcm = 1, Format = 1)

    NuMicro NUC442/NUC472 Series Technical Reference Manual I2SBCLK I2SLRCLK I2SDI/I2SDO word N word N+1 left channel right channel Figure 6.16-6 PCM B Audio Timing Diagram (PCM = 1, Format = 1) May 23, 2014 Page 852 of 1386 Rev.1.05...

  • Page 853: Figure 6.16-7 Fifo Contents For Various I

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.16.4.2 FIFO operation Mono 8-bit data mode Stereo 8-bit data mode LEFT+1 RIGHT+1 LEFT RIGHT Mono 16-bit data mode Stereo 16-bit data mode LEFT RIGHT Mono 24-bit data mode Stereo 24-bit data mode LEFT RIGHT Mono 32-bit data mode Stereo 32-bit data mode...

  • Page 854: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.16.5 Functional Description 6.16.5.1 Zero Crossing When playing the audio by I S function, the output data comes from the memory by PDMA or by CPU. However, it may result some pop noise if the playing gain level is changed by user at any time.

  • Page 855: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.16.6 Register Map R: Read only, W: Write only, R/W: Both read and write Register Offset Description Reset Value I2S Base Address I2S_BA = 0x4004_8000 I2S_CTL I2S_BA+0x00 S Control Register 0x0000_0000 I2S_CLKDIV I2S_BA+0x04 S Clock Divider Register 0x0000_0000 I2S_IEN I2S_BA+0x08...

  • Page 856: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.16.7 Register Description S Control Register (I2S_CTL) Register Offset Description Reset Value I2S_CTL I2S_BA+0x00 S Control Register 0x0000_0000 Reserved PCMEN RXLCH Reserved RXPDMAEN TXPDMAEN RXCLR TXCLR LZCEN RZCEN MCLKEN RXTH TXTH SLAVE FORMAT MONO WDWIDTH MUTE RXEN...
  • Page 857 NuMicro NUC442/NUC472 Series Technical Reference Manual Clear Receive FIFO 0 = No Effect. 1 = Clear RX FIFO. [19] RXCLR Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS[27:24]) returns 0 and receive FIFO becomes empty. Note2: This bit is cleared by hardware automatically, read it return zero.
  • Page 858 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmit FIFO Threshold Level 000 = 0 word data in transmit FIFO. 001 = 1 word data in transmit FIFO. 010 = 2 words data in transmit FIFO. 011 = 3 words data in transmit FIFO. [11:9] TXTH 100 = 4 words data in transmit FIFO.
  • Page 859 NuMicro NUC442/NUC472 Series Technical Reference Manual S Controller Enable Bit I2SEN 0 = Disabled. 1 = Enabled. May 23, 2014 Page 859 of 1386 Rev.1.05...
  • Page 860 NuMicro NUC442/NUC472 Series Technical Reference Manual S Clock Divider (I2S_CLKDIV) Register Offset Description Reset Value I2S_CLKDIV I2S_BA+0x04 S Clock Divider Register 0x0000_0000 Reserved Reserved BCLKDIV BCLKDIV Reserved MCLKDIV Bits Description [31:17] Reserved Reserved. Bit Clock Divider If I S operates in Master mode, bit clock is provided by the NuMicro NUC442/NUC472 series.
  • Page 861 NuMicro NUC442/NUC472 Series Technical Reference Manual S Interrupt Enable Register (I2S_IEN) Register Offset Description Reset Value I2S_IEN I2S_BA+0x08 S Interrupt Enable Register 0x0000_0000 Reserved Reserved Reserved LZCIEN RZCIEN TXTHIEN TXOVIEN TXUDIEN Reserved RXTHIEN RXOVIEN RXUDIEN Bits Description [31:13] Reserved Reserved. Left Channel Zero-Cross Interrupt Enable Bit 0 = Interrupt Disabled.
  • Page 862 NuMicro NUC442/NUC472 Series Technical Reference Manual Receive FIFO Threshold Level Interrupt Enable Bit 0 = Interrupt Disabled. RXTHIEN 1 = Interrupt Enabled. Note: When data word in receive FIFO is equal or higher than RXTH(I2S_CTL[14:12]) and the RXTHIF bit is set to 1. If RXTHIEN bit is enabled, interrupt occur. Receive FIFO Overflow Interrupt Enable Bit 0 = Interrupt Disabled.
  • Page 863 NuMicro NUC442/NUC472 Series Technical Reference Manual S Status Register (I2S_STATUS) Register Offset Description Reset Value I2S_STATUS I2S_BA+0x0C S Status Register 0x0014_1000 TXCNT RXCNT LZCIF RZCIF TXBUSY TXEMPTY TXFULL TXTHIF TXOVIF TXUDIF Reserved RXEMPTY RXFULL RXTHIF RXOVIF RXUDIF Reserved RIGHT TXIF RXIF I2SIF Bits...
  • Page 864 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmit Busy (Read Only) 0 = Transmit shift buffer is empty. TXBUSY [21] 1 = Transmit shift buffer is busy. Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer.
  • Page 865 NuMicro NUC442/NUC472 Series Technical Reference Manual Receive FIFO Overflow Flag 0 = No overflow occur. 1 = Overflow occur. RXOVIF Note1: When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. Note2: Write 1 to clear this bit to 0.
  • Page 866 NuMicro NUC442/NUC472 Series Technical Reference Manual S Transmit FIFO (I2S_TX) Register Offset Description Reset Value I2S_TX I2S_BA+0x10 S Transmit FIFO Register 0x0000_0000 Bits Description Transmit FIFO Bits S contains 8 words (8x32 bit) data buffer for data transmit. Write data to this register to [31:0] prepare data...
  • Page 867 NuMicro NUC442/NUC472 Series Technical Reference Manual S Receive FIFO (I2S_RX) Register Offset Description Reset Value I2S_RX I2S_BA+0x14 S Receive FIFO Register 0x0000_0000 Bits Description Receive FIFO Bits [31:0] S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO.

  • Page 868: Image Capture Interface (Icap)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.17 Image Capture Interface (ICAP) 6.17.1 Overview The Image Capture Interface is designed to capture image data from a sensor. After capturing or fetching image data, it will process the image data, and then FIFO outputs them into a frame buffer. 6.17.2 Block Diagram Motion Estimation...

  • Page 869: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.17.4 Functional Description 6.17.4.1 Image Capture Flow Chart Sensor in Next Packet Planar Receive data format and format order Planar scaling down INFMT(CAP_PAR[0]) Packet scaling down PLNDSVNL(CAP_PLNSL[31:24]) INDATORD(CAP_PAR[3:2]) PKTDSVNL(CAP_PKTDSL[31:24]) PLNDSVML(CAP_PLNSL[23:16]) PKTDSVML(CAP_PKTDSL[23:16]) PLNDSHNL(CAP_PLNSL[15:8]) PKTDSHNL(CAP_PKTDSL[15:8]) PLNDSHML(CAP_PLNSL[7:0]) PKTDSHML(CAP_PKTDSL[7:0]) Output data to memory format PLNDSVNLH(CAP_PLNSM[31:24])

  • Page 870: Figure 6.17-3 Image Start And Size Of The Window After Cropping Block

    NuMicro NUC442/NUC472 Series Technical Reference Manual CWADDRV(CAP_CWSP[26:16]) CWSADDRH(CAP_CWSP[11:0]) CWH(CAP_CWS[26:16]) Image CWW(CAP_CWSP[11:0]) Figure 6.17-3 Image Start and Size of the Window after Cropping Block 6.17.4.3 One Shutter Mode (Single Frame) In this mode, a single frame is captured. After the SHUTTER (CAP_CTL[16]) bit is set, the Image Capture interface automatically disables the capture interface after a frame is captured.

  • Page 871: Figure 6.17-5 Mdsm Is Set To 1 And Mdbs Is Set To 0

    NuMicro NUC442/NUC472 Series Technical Reference Manual MDYADDR(CAP_MDYADDR[31:0]) BASEADDR(CAP_PKTBA0[31:0]) MDTHR(CAP_MD[20:16]) MDADDR(CAP_MDADDR[31:0]) 1 bytes Figure 6.17-5 MDSM is set to 1 and MDBS is set to 0 May 23, 2014 Page 871 of 1386 Rev.1.05...

  • Page 872: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.17.5 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset Description Reset Value CAP Base Address: CAP_BA = 0x4003_0000 CAP_CTL CAP_BA+0x00 Image Capture Interface Control Register 0x0000_0040 CAP_PAR...

  • Page 873: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.17.6 Register Description Image Capture Interface Control Register (CAP_CTL) Register Offset Description Reset Value CAP_CTL CAP_BA+0x00 Image Capture Interface Control Register 0x0000_0040 Reserved VPRST Reserved UPDATE Reserved SHUTTER Reserved Reserved PKTEN PLNEN Reserved ADDRSW Reserved Reserved CAPEN...
  • Page 874 NuMicro NUC442/NUC472 Series Technical Reference Manual 0 = Packet buffer address switch Disabled. 1 = Packet buffer address switch Enabled. [2:1] Reserved Reserved. Image Capture Interface Enable CAPEN 0 = Image Capture Interface Disabled. 1 = Image Capture Interface Enabled. May 23, 2014 Page 874 of 1386 Rev.1.05...
  • Page 875 NuMicro NUC442/NUC472 Series Technical Reference Manual Image Capture Interface Parameter Register (CAP_PAR) Register Offset Description Reset Value CAP_PAR CAP_BA+0x04 Image Capture Interface Parameter Register 0x0000_0000 Reserved Reserved Reserved Reserved COLORCTL PCLKP PLNFMT RANGE OUTFMT INDATORD SENTYPE INFMT Bits Description [31:19] Reserved Reserved.
  • Page 876 NuMicro NUC442/NUC472 Series Technical Reference Manual Scale Input YUV CCIR601 Color Range To Full Range RANGE 0 = default. 1 = Scale to full range. Image Data Format Output To System Memory 00 = YCbCr422. [5:4] OUTFMT 01 = Only output Y. 10 = RGB555.
  • Page 877 NuMicro NUC442/NUC472 Series Technical Reference Manual Image Capture Interface Interrupt Register (CAP_INT) Register Offset Description Reset Value CAP_INT CAP_BA+0x08 Image Capture Interface Interrupt Register 0x0000_0000 Reserved Reserved MDIEN ADDRMIEN Reserved MEIEN VIEN Reserved Reserved MDINTF ADDRMINTF Reserved MEINTF VINTF Bits Description [31:21] Reserved...
  • Page 878 NuMicro NUC442/NUC472 Series Technical Reference Manual Video Frame End Interrupt VINTF If this bit shows 1, receiving a frame completed. Write 1 to clear it. May 23, 2014 Page 878 of 1386 Rev.1.05...
  • Page 879 NuMicro NUC442/NUC472 Series Technical Reference Manual YUV Component Posterizing Factor Register (CAP_POSTERIZE) Register Offset Description Reset Value CAP_POSTERIZE CAP_BA+0x0C YUV Component Posterizing Factor Register 0x0000_0000 Reserved YCOMP UCOMP VCOMP Bits Description [31:24] Reserved Reserved. Y Component Posterizing Factor YCOMP [23:16] Final_Y_Out = Original_Y[7:0] &...
  • Page 880 NuMicro NUC442/NUC472 Series Technical Reference Manual Motion Detection Register (CAP_MD) Register Offset Description Reset Value CAP_MD CAP_BA+0x10 Motion Detection Register 0x0000_0000 Reserved Reserved MDTHR Reserved MDDF MDSM MDBS Reserved MDEN Bits Description [31:21] Reserved Reserved. [20:16] MDTHR Motion Detection Differential Threshold Reserved [15:12] Reserved.
  • Page 881 NuMicro NUC442/NUC472 Series Technical Reference Manual Motion Detection Output Address Register (CAP_MDADDR) Register Offset Description Reset Value CAP_MDADDR CAP_BA+0x14 Motion Detection Output Address Register 0x0000_0000 MDADDR MDADDR MDADDR MDADDR Bits Description [31:0] MDADDR Motion Detection Output Address Register (Word Alignment) May 23, 2014 Page 881 of 1386 Rev.1.05...
  • Page 882 NuMicro NUC442/NUC472 Series Technical Reference Manual Motion Detection Temp Y Output Address Register (CAP_MDYADDR) Register Offset Description Reset Value CAP_MDYADDR CAP_BA+0x18 Motion Detection Temp Y Output Address Register 0x0000_0000 MDYADDR MDYADDR MDYADDR MDYADDR Bits Description [31:0] MDYADDR Motion Detection Temp Y Output Address Register (Word Alignment) May 23, 2014 Page 882 of 1386 Rev.1.05...
  • Page 883 NuMicro NUC442/NUC472 Series Technical Reference Manual Sepia Effect Control Register (CAP_SEPIA) Register Offset Description Reset Value CAP_SEPIA CAP_BA+0x1C Sepia Effect Control Register 0x0000_0000 Reserved Reserved UCOMP VCOMP Bits Description [31:16] Reserved Reserved. Define the constant U component while “Sepia” color effect is turned on. [15:8] UCOMP Define the constant V component while “Sepia”...
  • Page 884 NuMicro NUC442/NUC472 Series Technical Reference Manual Cropping Window Starting Address Register (CAP_CWSP) Register Offset Description Reset Value CAP_CWSP CAP_BA+0x20 Cropping Window Starting Address Register 0x0000_0000 Reserved CWSADDRV CWSADDRV Reserved CWSADDRH CWSADDRH Bits Description [31:27] Reserved Reserved. [26:16] CWSADDRV Cropping Window Vertical Starting Address Reserved [15:12] Reserved.
  • Page 885 NuMicro NUC442/NUC472 Series Technical Reference Manual Cropping Window Size Register (CAP_CWS) Register Offset Description Reset Value CAP_CWS CAP_BA+0x24 Cropping Window Size Register 0x0000_0000 Reserved Reserved Bits Description [31:27] Reserved Reserved. [26:16] Cropping Window Height Reserved [15:12] Reserved. [11:0] Cropping Window Width May 23, 2014 Page 885 of 1386 Rev.1.05...
  • Page 886 NuMicro NUC442/NUC472 Series Technical Reference Manual Packet Scaling Vertical/Horizontal Factor Register (LSB) (CAP_PKTSL) Register Offset Description Reset Value CAP_PKTSL CAP_BA+0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB) 0x0000_0000 PKTSVNL PKTSVML PKTSHNL PKTSHML Bits Description Packet Scaling Vertical Factor N (Lower 8-Bit) Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
  • Page 887 NuMicro NUC442/NUC472 Series Technical Reference Manual Planar Scaling Vertical/Horizontal Factor Register (LSB) (CAP_PLNSL) Register Offset Description Reset Value CAP_PLNSL CAP_BA+0x2C Planar Scaling Vertical/Horizontal Factor Register (LSB) 0x0000_0000 PLNSVNL PLNSVML PLNSHNL PLNSHML Bits Description Planar Scaling Vertical Factor N (Lower 8-Bit) Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
  • Page 888 NuMicro NUC442/NUC472 Series Technical Reference Manual Packet Scaling Vertical/Horizontal Factor Register (MSB) (CAP_PKTSM) Register Offset Description Reset Value CAP_PKTSM CAP_BA+0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB) 0x0000_0000 PKTSVNH PKTSVMH PKTSHNH PKTSHMH Bits Description Packet Scaling Vertical Factor N (Higher 8-Bit) Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
  • Page 889 NuMicro NUC442/NUC472 Series Technical Reference Manual Planar Scaling Vertical/Horizontal Factor Register (MSB) (CAP_PLNSM) Register Offset Description Reset Value CAP_PLNSM CAP_BA+0x4C Planar Scaling Vertical/Horizontal Factor Register (MSB) 0x0000_0000 PLNSVNH PLNSVMH PLNSHNH PLNSHMH Bits Description Planar Scaling Vertical Factor N (Higher 8-Bit) Specifies the higher 8-bit of numerator part (N) of the vertical scaling factor.
  • Page 890 NuMicro NUC442/NUC472 Series Technical Reference Manual Scaling Frame Rate Factor Register (CAP_FRCTL) Register Offset Description Reset Value CAP_FRCTL CAP_BA+0x30 Scaling Frame Rate Factor Register 0x0000_0000 Reserved Reserved Reserved Reserved Bits Description [31:14] Reserved Reserved. Scaling Frame Rate Factor N [13:8] Specify the denominator part (N) of the frame rate scaling factor.
  • Page 891 NuMicro NUC442/NUC472 Series Technical Reference Manual Output Frame Pixel Stride Width (CAP_STRIDE) Register Offset Description Reset Value CAP_STRIDE CAP_BA+0x34 Frame Output Pixel Stride Width Register 0x0000_0000 Reserved PLNSTRIDE PLNSTRIDE Reserved PKTSTRIDE PKTSTRIDE Bits Description [31:28] Reserved Reserved. Planar Frame Output Pixel Stride Width PLNSTRIDE [29:16] The output pixel stride size of planar pipe.
  • Page 892 NuMicro NUC442/NUC472 Series Technical Reference Manual FIFO Threshold Register (CAP_FIFOTH) Register Offset Description Reset Value CAP_FIFOTH CAP_BA+0x3C FIFO Threshold Register 0x070D_0507 Reserved PKTFTH Reserved PLNYFTH Reserved PLNUFTH Reserved PLNVFTH Bits Description [31] FIFO Overflow Flag [30:29] Reserved Reserved. PKTFTH Packet FIFO Threshold [28:24] [23:21] Reserved...
  • Page 893 NuMicro NUC442/NUC472 Series Technical Reference Manual Compare Memory Address Register (CAP_CMPADDR) Register Offset Description Reset Value CAP_CMPADDR CAP_BA+0x40 Compare Memory Base Address Register 0xFFFF_FFFC CMPADDR CMPADDR CMPADDR CMPADDR Bits Description Compare Memory Base Address [31:0] CMPADDR Word aligns address; ignore the bits [1:0]. May 23, 2014 Page 893 of 1386 Rev.1.05...
  • Page 894 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Packet System Memory Address Register (CAP_CURADDRP) Register Offset Description Reset Value CAP_CURADDRP CAP_BA+0x50 Current Packet System Memory Address Register 0x0000_0000 CURADDR CURADDR CURADDR CURADDR Bits Description [31:0] CURADDR Current Packet Output Memory Address May 23, 2014 Page 894 of 1386 Rev.1.05...
  • Page 895 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Planar Y System Memory Address Register (CAP_CURADDRY) Register Offset Description Reset Value CAP_CURADDRY CAP_BA+0x54 Current Planar Y System Memory Address Register 0x0000_0000 CURADDR CURADDR CURADDR CURADDR Bits Description [31:0] CURADDR Current Planar Y Output Memory Address May 23, 2014 Page 895 of 1386 Rev.1.05...
  • Page 896 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Planar U System Memory Address Register (CAP_CURADDRU) Register Offset Description Reset Value CAP_CURADDRU CAP_BA+0x58 Current Planar U System Memory Address Register 0x0000_0000 CURADDR CURADDR CURADDR CURADDR Bits Description [31:0] CURADDR Current Planar U Output Memory Address May 23, 2014 Page 896 of 1386 Rev.1.05...
  • Page 897 NuMicro NUC442/NUC472 Series Technical Reference Manual Current Planar V System Memory Address Register (CAP_CURVADDR) Register Offset Description Reset Value CAP_CURVADDR CAP_BA+0x5C Current Planar V System Memory Address Register 0x0000_0000 CURADDR CURADDR CURADDR CURADDR Bits Description [31:0] CURADDR Current Planar V Output Memory Address May 23, 2014 Page 897 of 1386 Rev.1.05...
  • Page 898 NuMicro NUC442/NUC472 Series Technical Reference Manual System Memory Packet Base Address 0 Register (CAP_PKTBA0) Register Offset Description Reset Value CAP_PKTBA0 CAP_BA+0x60 System Memory Packet Base Address 0 Register 0x0000_0000 BASEADDR BASEADDR BASEADDR BASEADDR Bits Description System Memory Packet Base Address 0 [31:0] BASEADDR Word aligns address;...
  • Page 899 NuMicro NUC442/NUC472 Series Technical Reference Manual System Memory Packet Base Address 1 Register (CAP_PKTBA1) Register Offset Description Reset Value CAP_PKTBA1 CAP_BA+0x64 System Memory Packet Base Address 1 Register 0x0000_0000 BASEADDR BASEADDR BASEADDR BASEADDR Bits Description System Memory Packet Base Address 1 [31:0] BASEADDR Word aligns address;...
  • Page 900 NuMicro NUC442/NUC472 Series Technical Reference Manual System Memory Planar Y Base Address Register (CAP_YBA) Register Offset Description Reset Value CAP_YBA CAP_BA+0x80 System Memory Planar Y Base Address Register 0x0000_0000 BASEADDR BASEADDR BASEADDR BASEADDR Bits Description System Memory Planar Y Base Address [31:0] BASEADDR Word aligns address;...
  • Page 901 NuMicro NUC442/NUC472 Series Technical Reference Manual System Memory Planar U Base Address Register (CAP_UBA) Register Offset Description Reset Value CAP_UBA CAP_BA+0x84 System Memory Planar U Base Address Register 0x0000_0000 BASEADDR BASEADDR BASEADDR BASEADDR Bits Description System Memory Planar U Base Address [31:0] BASEADDR Word aligns address;...
  • Page 902 NuMicro NUC442/NUC472 Series Technical Reference Manual System Memory Planar V Base Address Register (CAP_VBA) Register Offset Description Reset Value CAP_VBA CAP_BA+0x88 System Memory Planar V Base Address Register 0x0000_0000 BASEADDR BASEADDR BASEADDR BASEADDR Bits Description System Memory Planar V Base Address [31:0] BASEADDR Word aligns address;...

  • Page 903: Enhanced Input Capture Timer

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.18 Enhanced Input Capture Timer 6.18.1 Overview This device provides up to two units of Input Capture Timer/Counter which capture function can detect the digital edge changed signal at channel inputs. Each unit has three input capture channels. The timer/counter is equipped with up counting, reload and compare-match capabilities.

  • Page 904: Input Noise Filter

    NuMicro NUC442/NUC472 Series Technical Reference Manual CAPSEL0 NFDIS NFCLKSEL[1:0] Input Capture OPDO0 Control Unit CHAx CAP0 Noise CPO0 CAPEN0 Filter ECAP_HOLD0 CAPSEL1 ECAP_HOLD1 OPDO1 ECAP_HOLD2 ECAP_CNT CHBx CAP1 CPO1 Noise CAPEN1 Filter ECAP_CNTCMP CAPSEL2 ECAP_CTL0~1 ADCMPOx ECAP_STATUS CAP2 CHXx CPO2 Noise CAPEN2 Filter...
  • Page 905 NuMicro NUC442/NUC472 Series Technical Reference Manual 6.18.5.1 Capture Function Each time the capture input trigger is validated, the content of the free running 24 bits capture counter ECAP_CNT will be captured/transferred into the capture hold registers, ECAP_HOLD0~2, depending on which channel trigger. This action also causes the CAPF flag bits in ECAP_STATUS to be set, which will also generate an interrupt (if enabled by CAPIENx (ECAP_CTL0[16]).

  • Page 906: Figure 6.18-4 Input Capture Timer/Counter Functions Block

    NuMicro NUC442/NUC472 Series Technical Reference Manual Input Capture Unit0 IC0 Block Input Capture Input Capture ECAP_HLD0 IC1 Block Unit0 IC2 Block EDGESEL0[1:0] CAPF0 CAP1 CAP2 [00] CAP0 [01] [1x] CAPF0 CAPF1 CAPF2 Clear CAPCLR CMPCLR ECAP_CNT CMPF SRCSEL CAPF0 CAPF1 CAPF2 CAP2 24-bit up counter...

  • Page 907: Input Capture Timer/Counter Interrupt Architecture

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.18.5.3 Reload Mode Input Capture Timer/Counter can be also be configured for reload mode. The reload function is enabled by setting the RLDEN (ECAP_CTL0[27]) to 1. In this mode, ECAP_CNTCMP serves as a reload register. When ECAP_CNT overflows, a reload is generated that causes the contents of the ECAP_CNTCMP register to be reloaded into the ECAP_CNT register, if RLDEN is set.

  • Page 908: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.18.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value ECAP Base Address: ECAPn_BA = 0x400B_4000+ n *0x1000 n=0,1 ECAP_CNT ECAPn_BA+0x00 Input Capture Counter (24-bit up counter) 0x0000_0000 ECAP_HOLD0 ECAPn_BA+0x04...

  • Page 909: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.18.8 Register Description Input Capture Counter (ECAP_CNT) Register Offset Description Reset Value ECAP_CNT ECAPn_BA+0x00 Input Capture Counter (24-bit up counter) 0x0000_0000 Reserved VAL[23:16] VAL[15:8] VAL[7:0] Bits Description Reserved [31:24] Reserved. Input Capture Timer/Counter [23:0] The input Capture Timer/Counter is a 24-bit up-counting counter.
  • Page 910 NuMicro NUC442/NUC472 Series Technical Reference Manual Input Capture Counter Hold Register (ECAP_HOLD0~2) Register Offset Description Reset Value ECAP_HOLD0 ECAPn_BA+0x04 Input Capture Counter Hold Register 0 0x0000_0000 ECAP_HOLD1 ECAPn_BA+0x08 Input Capture Counter Hold Register 1 0x0000_0000 ECAP_HOLD2 ECAPn_BA+0x0C Input Capture Counter Hold Register 2 0x0000_0000 Reserved VAL[23:16]...
  • Page 911 NuMicro NUC442/NUC472 Series Technical Reference Manual Input Capture Counter Compare Register (ECAP_CNTCMP) Register Offset Description Reset Value ECAP_CNTCMP ECAPn_BA+0x10 Input Capture Counter Compare Register 0x0000_0000 Reserved VAL[23:16] VAL[15:8] VAL[7:0] Bits Description [31:24] Reserved Reserved. Input Capture Counter Compare Register If the compare function is enabled (CMPEN(ECAP_CTL0[28]) = 1), the compare register is loaded with the value that the compare function compares the capture counter (ECAP_CNT) [23:0] with.
  • Page 912 NuMicro NUC442/NUC472 Series Technical Reference Manual Input Capture Timer/Counter Control Register (ECAP_CTL0) Register Offset Description Reset Value ECAP_CTL0 ECAPn_BA+0x14 Input Capture Control Register 0 0x0000_0000 Reserved CAPEN CMPEN RLDEN CPTCLR CMPCLR CNTEN Reserved CMPIEN OVIEN Reserved CAPIEN2 CAPIEN1 CAPIEN0 Reserved CAPSEL2 CAPSEL1 CAPSEL0...
  • Page 913 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description Input Capture Counter Start Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK). [24] CNTEN 0 = ECAP_CNT stop counting. 1 = ECAP_CNT starts up-counting. [23:22] Reserved Reserved.
  • Page 914 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description Port Pin IC2 Input To Input Capture Unit Enable Bit CAPEN2 0 = IC2 input to Input Capture Unit Disabled. 1 = IC2 input to Input Capture Unit Enabled. Port Pin IC1 Input To Input Capture Unit Enable Bit CAPEN1 0 = IC1 input to Input Capture Unit Disabled.
  • Page 915 NuMicro NUC442/NUC472 Series Technical Reference Manual Input Capture Timer/Counter Control Register (ECAP_CTL1) Register Offset Description Reset Value ECAP_CTL1 ECAPn_BA+0x18 R/W Input Capture Control Register 1 0x0000_0000 Reserved Reserved SRCSEL Reserved CLKSEL Reserved RLDSEL Reserved EDGESEL2 EDGESEL1 EDGESEL0 Bits Description [31:18] Reserved Reserved.
  • Page 916 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description ECAP_CNT Reload Trigger Source Selection If the reload function is enabled RLDEN (ECAP_CTL0[27]) = 1, when a reload trigger event comes, the ECAP_CNT is reloaded with ECAP_CNTCMP. RLDSEL[2:0] determines the ECAP_CNT reload trigger source 000 = CAPF0.
  • Page 917 NuMicro NUC442/NUC472 Series Technical Reference Manual Input Capture Timer/Counter Status Register (ECAP_STATUS) Register Offset Description Reset Value ECAP_STATUS ECAPn_BA+0x1C Input Capture Status Register 0x0000_0000 Reserved Reserved Reserved Reserved CMPF Reserved CAPF2 CAPF1 CAPF0 Bits Description [31:6] Reserved Reserved. Input Capture Counter Overflow Flag Flag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
  • Page 918 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description Input Capture Channel 0 Captured Flag When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high. CAPF0 0 = No valid edge change is detected at CAP0 input. 1 = A valid edge change is detected at CAP0 input.

  • Page 919: Op Amplifier

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.19 OP Amplifier 6.19.1 Overview This device integrated two operational amplifiers. It can be enabled through OPENx (OPA_CTL[1:0]) bits. User can measure the outputs of the OP amplifier as the OP amplifier output to the integrated EADC channel EADC0_11 and EADC1_8, where digital results can be taken.

  • Page 920: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.19.3 Block Diagram OPSMTEN0 Schmitt trigger input OPDO0 Non-inverting buffer Enable OP0 OPEN0 To EADC Amplifier AINA[B] PF[9]/OPP0 PF[11]/OPO0 PF[10]/OPN0 To integrated OP Amplifier 0 comparator positive input end To integrated comparator positive input end Enable OP1 OPEN1 Amplifier...

  • Page 921: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.19.5 Register Map R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written Register Offset Description Reset Value OPS Base Address: OPA_BA = 0x4004_6000 OPA_CTL OPA_BA+0x00 OP Amplifier Control Register 0x0000_0000 OPA_STATU...

  • Page 922: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.19.6 Register Description OPA Control Register (OPA_CTL) Register Offset Description Reset Value OPA_CTL OPA_BA+0x00 OP Amplifier Control Register 0x0000_0000 Reserved Reserved Reserved OPAIE1 OPAIE0 Reserved Reserved OPSMTEN1 OPSMTEN0 Reserved Reserved OPEN1 OPEN0 Bits Description Reserved [31:10] Reserved.
  • Page 923 NuMicro NUC442/NUC472 Series Technical Reference Manual Bits Description OP Amplifier 1 Enable Bit 0 = Disabled. OPEN1 1 = Enabled. Note: OP Amplifier 1 output needs wait stable 20μs after OPEN1 is first set. OP Amplifier 0 Enable Bit 0 = Disabled. OPEN0 1 = Enabled.
  • Page 924 NuMicro NUC442/NUC472 Series Technical Reference Manual OPA Status Register (OPA_STATUS) Register Offset Description Reset Value OPA_STATUS OPA_BA+0x04 OP Amplifier Status Register 0x0000_0000 Reserved Reserved Reserved Reserved OPDF1 OPDF0 Reserved OPDO1 OPDO0 Bits Description [31:6] Reserved Reserved. OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag OPDF1 OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state.

  • Page 925: Ps/2 Device Controller (Ps2D)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.20 PS/2 Device Controller (PS2D) 6.20.1 Overview The PS/2 device controller provides basic timing control for PS/2 communication. All communication between the device and the host is managed through the CLK and DATA pins. Unlike PS/2 keyboard or mouse device controller, the received/transmit code needs to be translated as meaningful code by firmware.

  • Page 926: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.20.3 Block Diagram The PS/2 device controller consists of APB interface and timing control logic for DATA and CLK lines. Control & TX shift logic Off Chip Main state 16x8 Status machine TX FIFO 4.7k Register parity &...

  • Page 927: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.20.4 Functional Description 6.20.4.1 Communication The PS/2 device implements a bidirectional synchronous serial protocol. The bus is "Idle" when both lines are high (open-collector). This is the only state where the device is allowed start to transmit DATA.

  • Page 928: Figure 6.20-2 Data Format Of Device-To-Host

    NuMicro NUC442/NUC472 Series Technical Reference Manual The device writes a bit on the DATA line when CLK is high, and it is read by the host when CLK is low, which is illustrated in the following figure. DATA Figure 6.20-2 Data Format of Device-to-Host Host-to-Device: The PS/2 device always generates the CLK signal.

  • Page 929: Figure 6.20-4 Ps/2 Bit Data Format

    NuMicro NUC442/NUC472 Series Technical Reference Manual Detailed Host to Device Communication Communication Request Data Packet Inhibited to Send DATA DATA Figure 6.20-4 PS/2 Bit Data Format 6.20.4.2 PS/2 Bus Timing Specification PS2 Device Data Output 10th 11th DATA START PARITY STOP BIT0 PS2 Device Data Input...

  • Page 930: Figure 6.20-6 Ps/2 Data Format

    NuMicro NUC442/NUC472 Series Technical Reference Manual Symbol Timing Parameter DATA transition to the falling edge of CLK 25us Rising edge of CLK to DATA transition T4-5us Duration of CLK inactive 30us 50us Duration of CLK active 30us 50us Time to auxiliary device inhibit after 11 clock to ensure auxiliary device does not start >0 50us...

  • Page 931: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.20.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset Description Reset Value PS2 Base Address: PS2_BA=0x400E_0000 PS2_CTL PS2_BA+0x00 PS/2 Control Register 0x0000_0000 PS2_TXDAT0 PS2_BA+0x04 PS/2 Transmit DATA Register 0 0x0000_0000 PS2_TXDAT1 PS2_BA+0x08 PS/2 Transmit DATA Register 1...

  • Page 932: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.20.6 Register Description PS/2 Control Register (PS2_CTL) Register Offset Description Reset Value PS2_CTL PS2_BA+0x00 PS/2 Control Register 0x0000_0000 Reserved Reserved Reserved FPS2DAT FPS2CLK OVERRIDE CLRFIFO TXFDEPTH RXIEN TXIEN PS2EN Bits Description [31:12] Reserved Reserved. Force DATSTAT Line It forces DATSTAT high or low regardless of the internal state of the device controller if OVERRIDE is set to high.
  • Page 933 NuMicro NUC442/NUC472 Series Technical Reference Manual Transmit Data FIFO Depth There is 16-byte buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depending on the application. 0 = 1 byte. [6:3] TXFDEPTH 1 = 2 bytes. …...
  • Page 934 NuMicro NUC442/NUC472 Series Technical Reference Manual PS/2 TX DATA Register 0-3 (PS2_TXDAT0-3) Register Offset Description Reset Value PS2_TXDAT0 PS2_BA+0x04 PS/2 Transmit DATA Register 0 0x0000_0000 PS2_TXDAT1 PS2_BA+0x08 PS/2 Transmit DATA Register 1 0x0000_0000 PS2_TXDAT2 PS2_BA+0x0C PS/2 Transmit DATA Register 2 0x0000_0000 PS2_TXDAT3 PS2_BA+0x10...
  • Page 935 NuMicro NUC442/NUC472 Series Technical Reference Manual PS/2 Receiver DATA Register (PS2_RXDAT ) Register Offset Description Reset Value PS2_RXDAT PS2_BA+0x14 PS/2 Receive DATA Register 0x0000_0000 Reserved Reserved Reserved DAT[7:0] Bits Description [31:8] Reserved Reserved. Received Data For host to device communication, after acknowledge bit is sent, the received data is [7:0] copied from receive shift register to PS2_RXDAT register.
  • Page 936 NuMicro NUC442/NUC472 Series Technical Reference Manual PS/2 Status Register (PS2_STATUS) Register Offset Description Reset Value PS2_STATUS PS2_BA+0x18 PS/2 Status Register 0x0000_0083 Reserved Reserved Reserved BYTEIDX TXEMPTY RXOV TXBUSY RXBUSY RXPARITY FRAMEERR DATSTAT CLKSTAT Bits Description [31:12] Reserved Reserved. Byte Index It indicates which data byte in transmit data shift register.
  • Page 937 NuMicro NUC442/NUC472 Series Technical Reference Manual Note: Write 1 to clear this bit. Transmit Busy This bit indicates that the PS/2 device is currently sending data. TXBUSY 0 = Idle. 1 = Currently sending data. Note: This bit is read only. Receive Busy This bit indicates that the PS/2 device is currently receiving data.
  • Page 938 NuMicro NUC442/NUC472 Series Technical Reference Manual PS/2 Interrupt Identification Register (PS2_INTSTS) Register Offset Description Reset Value PS2_INTSTS PS2_BA+0x1C PS/2 Interrupt Status Register 0x0000_0000 Reserved Reserved Reserved Reserved TXIF RXIF Bits Description [31:3] Reserved Reserved. Transmit Interrupt This bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXIEN(PS2_CTL[1]) bit to 1.

  • Page 939: Pwm Generator And Capture Timer (Pwm)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.21 PWM Generator and Capture Timer (PWM) 6.21.1 Overview The NUC442/NUC472 has two PWM generators － PWM0 and PWM1. PWM0 supports 6 channels PWM output or 6 channels input capture, and these two functions share the same pins (PWM0_CH0/ PWM0_CH1/PWM0_CH2/PWM0_CH3/PWM0_CH4/PWM0_CH5).

  • Page 940: Block Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.21.3 Block Diagram The following six figures illustrate the architecture of PWM in pair (e.g. PWM-Timer 0/1 are in one pair, PWM-Timer 2/3 are in one pair and PWM-Timer 4/5 are in another one). PWM0CH01SEL (CLK_CLKSEL2[2:0]) PWM0CH01CKEN...

  • Page 941: Figure 6.21-2 Pwm Generator 0 Architecture Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual DZCNT01(PWM_DZCTL[7:0]) Dead Zone Generator 0 PWM_PERIOD0 CLKDIV0(PWM_CLKDIV[2:0]) PWM_CMPDAT0 POEN0(PWM_POEN[0]) PWM_CTL PWM_CNT0 PWMx_CH0 PWM- Timer0 Logic PWMx_CH01_CLK Clock (from clock Divider 1/16 PINV0 controller) (PWM_CTL[8]) CMPINV0 PIEN0 PIF0 (PWM_CTL[0]) DIEN0 DIF0 8-bit DTEN01 Prescaler (PWM_DTCTL[28]) PWM_PERIOD1 PWM_CMPDAT1 PWM_CNT1...

  • Page 942: Figure 6.21-3 Pwm Generator 2 Clock Source Control

    NuMicro NUC442/NUC472 Series Technical Reference Manual PWM0CH23SEL (CLK_CLKSEL2[6:4]) 4~24 MHz PWM0CH23CLEN(CLK_APBCLK1[17]) 32.768 kHz PWM1_CH23_CLK HCLK 22.1184 MHz HCLK 10 kHz PWMSYNCMODE (SYS_VREFCTL[9]) PWM1CH23SEL (CLK_CLKSEL2[18:16]) 4~24 MHz PWM1_CH23_EN(APBCLK1[20]) 32.768 kHz PWM1_CH23_CLK HCLK 22.1184 MHz HCLK 10 kHz PWMSYNCMODE (SYS_VREFCTL[9]) Figure 6.21-3 PWM Generator 2 Clock Source Control May 23, 2014 Page 942 of 1386 Rev.1.05...

  • Page 943: Figure 6.21-4 Pwm Generator 2 Architecture Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual DZCNT23(PWM_DZCTL[15:8]) Dead Zone Generator 2 PWM_PERIOD2 CLKDIV2(PWM_CLKDIV[10:8]) PWM_CMPDAT2 PWM_CTL POEN2(PWM_POEN[2]) PWM_ CNT2 PWMx_CH2 PWM- Timer2 Logic PWMx_CH23_CLK Clock Divider (from clock 1/16 PINV2 controller) (PWM_CTL[10]) CMPINV2 PIEN2 PIF2 (PWM_CTL[2]) DIEN2 DIF2 8-bit DTEN23 Prescaler (PWM_DTCTL[29]) PWM_PERIOD3 PWM_...

  • Page 944: Figure 6.21-5 Pwm Generator 4 Clock Source Control

    NuMicro NUC442/NUC472 Series Technical Reference Manual PWM0CH45SEL (CLK_CLKSEL2[10:8]) 4~24 MHz PWM0CH45CKEN(CLK_APBCLK1[18]) 32.768 kHz PWM0_CH45_CLK HCLK 22.1184 MHz HCLK 10 kHz PWMSYNCMODE (SYS_VREFCTL[9]) PWM1CH45SEL (CLK_CLKSEL2[22:20]) 4~24 MHz PWM1CH45CKEN(CLK_APBCLK1[21]) 32.768 kHz PWM1_CH45_CLK HCLK 22.1184 MHz HCLK 10 kHz PWMSYNCMODE (SYS_VREFCTL[9]) Figure 6.21-5 PWM Generator 4 Clock Source Control May 23, 2014 Page 944 of 1386 Rev.1.05...

  • Page 945: Functional Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual DTCNT45(PWM_DTCTL[23:16]) Dead Zone Generator 4 PWM_PERIOD4 CLKDIV4(PWM_CLKDIV[18:16]) PWM_CMPDAT4 PWM_CTL POEN4(PWM_POEN[4]) PWM_CNT4 PWMx_CH4 PWM- Timer4 Logic PWMx_CH45_CLK Clock Divider (from clock 1/16 PINV4 controller) (PWM_CTL[12]) CMPINV4 PIEN4 (PWM_CTL[4]) PIF4 DIEN4 DIF4 8-bit DTEN45 Prescaler (PWM_DTCTL[30]) PWM_PERIOD5 PWM_CMPDAT5 PWM_...

  • Page 946: Figure 6.21-7 Pwm Waveform Of Edge-Aligned Type

    NuMicro NUC442/NUC472 Series Technical Reference Manual  PWM_CMPDATn = 0: PWM low width = (PWM_PERIODn) unit; PWM high width = 1 unit Note: [1] Unit = one PWM clock cycle. Initialize Update Update start PWM_PERIODn PWM_CMPDATn PWM counter 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 PWM_PERIODn...

  • Page 947: Figure 6.21-8 Center-Aligned Mode Output Waveform

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.21.4.3 Center-aligned PWM (Up/down-counter) In Center-aligned type, the 16 bits PWM counter is an up/down counter and start counting-up from 0 to the value of (PWM_PERIODn+1) and then start counting down to zero to finish a PWM period.

  • Page 948: Figure 6.21-9 Pwm Center Aligned Interrupt Generate Timing Waveform

    NuMicro NUC442/NUC472 Series Technical Reference Manual PERIOD (0x7FF) CMP (0x3FF) PIFn (PINTTYPEn=0) clear clear clear PIFn (PINTTYPEn=1) clear clear PWM generator output Period Period Figure 6.21-9 PWM Center Aligned Interrupt Generate Timing Waveform 6.21.4.4 PWM Counter Operation mode The PWM counter supports two operation modes: One-shot mode and Auto-reload mode. PWM counter will operate in One-shot mode if CNTMODE (PWM_CTL[16+n]) bit is set to 0, and operate in Auto-reload mode if CNTMODE (PWM_CTL[16+n]) bit is set to 1.

  • Page 949: Figure 6.21-10 Pwm Double Buffering Timing Waveform

    NuMicro NUC442/NUC472 Series Technical Reference Manual Write Write Write Write PWM_PERIODn=0 PWM_PERIODn=150 PWM_PERIODn=199 PWM_PERIODn=99 PWM_CMPDATn=X PWM_CMPDATn=50 PWM_CMPDATn=49 PWM_CMPDATn=0 Start Stop Waveform write a nonzero number to prescaler & setup clock dividor Figure 6.21-10 PWM Double Buffering Timing Waveform 6.21.4.6 PWM Output Control Unit The PWM output control unit include Dead-Zone Generator, output mode control, mask control, brake control, polarity control.
  • Page 950 NuMicro NUC442/NUC472 Series Technical Reference Manual PWMx_CH2 and PWMx_CH4 synchronous with PWMx_CH0 generator, may simplify updating duty control in DC and BLDC motor applications. Independent mode Independent mode is enabled when OUTMODE (PWM_CTL[6]) = 0. By default, the PWM is operating in independent mode, with six PWM channels outputs: PWMx_CH0, PWMx_CH1, PWMx_CH2, PWMx_CH3, PWMx_CH4 and PWMx_CH5.

  • Page 951: Figure 6.21-12 Illustration Of Mask Control Waveform

    NuMicro NUC442/NUC472 Series Technical Reference Manual PWM_MSKEN register contains six bits, MSKENn(PWM_MSKEN[5:0]). If the MASKENn is set to active-high, the PWM channel n output will be overridden. The PWM_MSK register contains six bits, MSKDATn(PWM_MSK[5:0]). The bit value of the MSKDATn determines the state value of the PWM channel n output when the channel is overridden.

  • Page 952: Figure 6.21-13 Pwm Brake Function

    NuMicro NUC442/NUC472 Series Technical Reference Manual BK0NFSEL (PWM_BRKCTL[7:6]), BRK0INV BK0NFDIS(PWM_BRKCTL[1]) (PWM_BRKCTL[2]) HCLK/1,/2,/4,/16 NED* PWM_BKPx0 Noise Filter PWM0~5 outputs BRKP0EN(PWM_BRKCTL[0]) follow PWMnB CPO0 NED* CPO0BKEN(PWM_BRKCTL[16]) BRKIF0 (see note) (PWM_INTSTS[6]) CPO1 NED* CPO1BKEN(PWM_BRKCTL[17]) CPO2 Brake Detect NED* CPO2BKEN(PWM_BRKCTL[18]) Interrupt * NED: Negative Edge Detection BRKP1EN(PWM_BRKCTL[8]) BK1NFSEL BRKIEN(PWM_INTEN[6])

  • Page 953: Figure 6.21-14 Pwm Output Multiplex For Group Mode And Synchronous Mode

    NuMicro NUC442/NUC472 Series Technical Reference Manual PWM_MUX0 PCMPO0 PCMPO0 SYNCEN GRPEN PWM_MUX1 PCMPO0 PCMPO1 SYNCEN GRPEN PWM_MUX2 PCMPO2 PCMPO0 SYNCEN GRPEN PWM_MUX3 PCMPO2 PCMPO1 SYNCEN GRPEN PWM_MUX4 PCMPO4 PCMPO0 SYNCEN GRPEN PWM_MUX5 PCMPO4 PCMPO1 SYNCEN GRPEN Figure 6.21-14 PWM Output Multiplex for Group Mode and Synchronous Mode May 23, 2014 Page 953 of 1386 Rev.1.05...

  • Page 954: Figure 6.21-15 Pwm Multiplex For Mask Control, Brake Control And Polarity Control

    NuMicro NUC442/NUC472 Series Technical Reference Manual Mask Control Brake Control Polarity Control DTENnm PWM_MUXn MSKDAT[n] BKOD[n] BRKIF0 Dead-time OUTMODE MSKEN[n] PINV[n] Control BRKIF1 PWM_MUXm MSKDAT[m] BKODm BRKIF0 OUTMODE MSKEN[m] PINVm BRKIF1 Note: n = 0,2,4 and m = 1,3,5 Figure 6.21-15 PWM Multiplex for Mask Control, Brake Control and Polarity Control 6.21.4.7 Capture Operation The channel of capture input and PWM output share one pin and PWM counter.

  • Page 955: Figure 6.21-16 Capture Operation Timing

    NuMicro NUC442/NUC472 Series Technical Reference Manual PWM counter Reload Reload No reload due to (If PERIODx = 8) Capture Input no PWM interrupt CAPINEN[n] FCAPDATn RCAPDATn FLIEN[n] RLIEN[n] Set by H/W Clear by S/W CFLIF[n] Set by H/W Clear by S/W CRLIF[n] PWM interrupt Note: n=0~5...

  • Page 956: Figure 6.21-17 Pwm Interrupt Architecture Diagram

    NuMicro NUC442/NUC472 Series Technical Reference Manual BRKIF0 BRKIF1 BRKIEN BRAKE_INT PIF[n] PIEN[n] DIF[n] DIEN[n] PWMn_INT CRLIF[n] RLIEN[n] CFLIF[n] FLIEN[n] n: PWM channel from 0~5 Figure 6.21-17 PWM Interrupt Architecture Diagram 6.21.4.9 PWM Start Procedure The following procedure is recommended for starting a PWM drive. Set clock source divider select register (PWM_CSDR) Set prescaler (PWM_CLKPSC) Set PWM counter auto-reload/one-shot operation mode, PWM comparator output...
  • Page 957 NuMicro NUC442/NUC472 Series Technical Reference Manual Set PWM counter register (PWM_PERIODn) for setting PWM period. After setup PWM_PERIODn, PWM wave will be generated. 6.21.4.11 PWM Stop Procedure Method 1: Set PWM counter register (PWM_PERIODn) as 0, and monitor PWM_CNTn (current value of 16- down-counter).

  • Page 958: Register Map

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.21.5 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value PWM Base Address: PWMx_BA = 0x4005_8000 + 0x1000 * x x=0,1 PWM_CLKPSC PWMx_BA+0x00 R/W PWM Clock Prescale Register 0x0000_0000 PWM_CLKDIV PWMx_BA+0x04 R/W PWM Clock Divide Register...
  • Page 959 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM_CNT5 PWMx_BA+0x54 PWM Data Register 5 0x0000_0000 PWM_MSKEN PWMx_BA+0x58 R/W PWM Mask Control Register 0x0000_0000 PWM_MSK PWMx_BA+0x5C R/W PWM Mask Data Register 0x0000_0000 PWM_DTCTL PWMx_BA+0x60 R/W PWM Dead-zone Control Register 0x0000_0000 PWM_TRGADC PWMx_BA+0x64 R/W PWM Trigger Control Register 0x0000_0000 PWM_TRGADC PWMx_BA+0x68...
  • Page 960 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM_SBS0 PWMx_BA+0xE0 PWM0 Synchronous Busy Status Register 0x0000_0000 PWM_SBS1 PWMx_BA+0xE4 PWM1 Synchronous Busy Status Register 0x0000_0000 PWM_SBS2 PWMx_BA+0xE8 PWM2 Synchronous Busy Status Register 0x0000_0000 PWM_SBS3 PWMx_BA+0xEC PWM3 Synchronous Busy Status Register 0x0000_0000 PWM_SBS4 PWMx_BA+0xF0 PWM4 Synchronous Busy Status Register 0x0000_0000 PWM_SBS5...

  • Page 961: Register Description

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.21.6 Register Description PWM Clock Prescale Register (PWM_CLKPSC) Register Offset Description Reset Value PWM_CLKPS PWMx_BA+0x00 PWM Clock Prescale Register 0x0000_0000 Reserved CLKPSC45 CLKPSC23 CLKPSC01 Bits Description [31:24] Reserved Reserved. PWM Counter Base-Clock Prescale For PWM Pair Of Channel 4 And Channel 5 The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
  • Page 962 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Clock Divide Register (PWM_CLKDIV) Register Offset Description Reset Value PWM_CLKDIV PWMx_BA+0x04 PWM Clock Divide Register 0x0000_0000 Reserved Reserved CLKDIV5 Reserved CLKDIV4 Reserved CLKDIV3 Reserved CLKDIV2 Reserved CLKDIV1 Reserved CLKDIV0 Bits Description Reserved [31:23] Reserved.
  • Page 963 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Counter Base-Clock Divide For PWMx_CH0 [2:0] CLKDIV0 (Table is the same as CLKDIV5) May 23, 2014 Page 963 of 1386 Rev.1.05...
  • Page 964 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Control Register (PWM_CTL) Register Offset Description Reset Value PWM_CTL PWMx_BA+0x08 PWM Control Register 0x0000_0000 DBGTRIOFF Reserved CNTTYPE Reserved CNTMODE SYNCEN Reserved PINV GROUPEN OUTMODE CMPINV Bits Description ICE Debug Mode Acknowledge Disable Bit (Write Protect) 0 = ICE debug mode acknowledgement effects PWM output.
  • Page 965 NuMicro NUC442/NUC472 Series Technical Reference Manual 0 = PWM output polar inverse Disabled. 1 = PWM output polar inverse Enabled. Note: Each bit controls the corresponding PWM channel. Group Mode Enable Bit 0 = The signals timing of each PWM channel are independent. GROUPEN 1 = Unify the signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 in the same phase which is controlled by PWM_CH0 and unify the signals timing of PWM_CH1, PWM_CH3...
  • Page 966 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Counter Enable Control Register (PWM_CNTEN) Register Offset Description Reset Value PWM_CNTEN PWMx_BA+0x0C PWM Counter Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CNTEN Bits Description [31:6] Reserved Reserved. PWM Counter Enable Bit 0 = PWM Counter Stop Running. [5:0] CNTEN 1 = PWM Counter Start Running.
  • Page 967 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Period Register 5-0 (PWM_PERIOD5-0) Register Offset Description Reset Value PWM_PERIO PWMx_BA+0x10 PWM Period Register 0 0x0000_0000 PWM_PERIO PWMx_BA+0x14 PWM Period Register 1 0x0000_0000 PWM_PERIO PWMx_BA+0x18 PWM Period Register 2 0x0000_0000 PWM_PERIO PWMx_BA+0x1C PWM Period Register 3 0x0000_0000 PWM_PERIO PWMx_BA+0x20...
  • Page 968 NuMicro NUC442/NUC472 Series Technical Reference Manual  CMP = 0: PWM low width = 2 x PERIOD + 1 unit; PWM high width = 1 unit. (Unit = one PWM clock cycle). Note1: Any write to PERIOD will take effect in next PWM cycle. Note2: When PWM operating at center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE.
  • Page 969 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Comparator Register 5-0 (PWM_CMPDAT5-0) Register Offset Description Reset Value PWM_CMPDA PWMx_BA+0x28 PWM Comparator Register 0 0x0000_0000 PWM_CMPDA PWMx_BA+0x2C PWM Comparator Register 1 0x0000_0000 PWM_CMPDA PWMx_BA+0x30 PWM Comparator Register 2 0x0000_0000 PWM_CMPDA PWMx_BA+0x34 PWM Comparator Register 3 0x0000_0000 PWM_CMPDA PWMx_BA+0x38...
  • Page 970 NuMicro NUC442/NUC472 Series Technical Reference Manual (Unit = one PWM clock cycle). Note: Any write to CMP will take effect in next PWM cycle. May 23, 2014 Page 970 of 1386 Rev.1.05...
  • Page 971 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Data Register 5-0 (PWM_CNT5-0) Register Offset Description Reset Value PWM_CNT0 PWMx_BA+0x40 PWM Data Register 0 0x0000_0000 PWM_CNT1 PWMx_BA+0x44 PWM Data Register 1 0x0000_0000 PWM_CNT2 PWMx_BA+0x48 PWM Data Register 2 0x0000_0000 PWM_CNT3 PWMx_BA+0x4C PWM Data Register 3 0x0000_0000 PWM_CNT4 PWMx_BA+0x50...
  • Page 972 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Mask Control Register (PWM_MSKEN) Register Offset Description Reset Value PWM_MSKEN PWMx_BA+0x58 PWM Mask Control Register 0x0000_0000 Reserved Reserved Reserved Reserved MSKEN Bits Description [31:6] Reserved Reserved. PWM Mask Enable Bits The PWM output signal will be masked when this bit is enabled. The corresponding PWMn channel will be output with MSKDAT data.
  • Page 973 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Mask Data Register (PWM_MSK) Register Offset Description Reset Value PWM_MSK PWMx_BA+0x5C PWM Mask Data Register 0x0000_0000 Reserved Reserved Reserved Reserved MSKDAT Bits Description [31:6] Reserved Reserved. PWM Mask Data Bit: This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
  • Page 974 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Dead-zone Control Register (PWM_DTCTL) Register Offset Description Reset Value PWM_DTCTL PWMx_BA+0x60 PWM Dead-zone Control Register 0x0000_0000 Reserved DTEN45 DTEN23 DTEN01 Reserved DTDIV DTCNT45 DTCNT23 DTCNT01 Bits Description [31] Reserved Reserved. Dead-Zone Enable Control for PWM Pair Of Channel 4 and Channel 5 Dead-zone insertion is only active when this pair of complementary PWM is enabled.
  • Page 975 NuMicro NUC442/NUC472 Series Technical Reference Manual The unit time of Dead-zone length is received from corresponding PWM_CLKDIV. Dead-Zone Interval For PWM Pair Of Channel 2 And Channel 3 [15:8] DTCNT23 These 8-bit determine the Dead-zone length. The unit time of Dead-zone length is received from corresponding PWM_CLKDIV. Dead-Zone Interval For PWM Pair Of Channel 0 And Channel 1 [7:0] DTCNT01...
  • Page 976 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Trigger Control Register (PWM_TRGADCTL) Register Offset Description Reset Value PWM_TRGAD PWMx_BA+0x64 PWM Trigger Control Register 0x0000_0000 Reserved RTRGEN Reserved FTRGEN Reserved CTRGEN Reserved PTRGEN Bits Description [31:30] Reserved Reserved. PWM Rising Edge Point Trigger Enable Bits 0 = PWM rising edge point trigger ADC function Disabled.
  • Page 977 NuMicro NUC442/NUC472 Series Technical Reference Manual 0 = PWM period point trigger ADC function Disabled. 1 = PWM period point trigger ADC function Enabled. PWM can trigger ADC to start conversion when PWM counter down count to zero if this bit is set to1. Note: Each bit controls the corresponding PWM channel.
  • Page 978 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Trigger Indicator Register (PWM_TRGADCSTS) Register Offset Description Reset Value PWM_TRGAD PWMx_BA+0x68 PWM Trigger ADC Status Register 0x0000_0000 CSTS Reserved RTRGF Reserved FTRGF Reserved CTRGF Reserved PTRGF Bits Description [31:30] Reserved Reserved. PWM Rising Edge Point Trigger Indicator This bit is set to 1 by hardware when PWM output pin rising edge is detected if corresponding RETRGEN bit is 1.
  • Page 979 NuMicro NUC442/NUC472 Series Technical Reference Manual Note2: Each bit controls the corresponding PWM channel. May 23, 2014 Page 979 of 1386 Rev.1.05...
  • Page 980 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Brake Control Register (PWM_BRKCTL) Register Offset Description Reset Value PWM_BRKCT PWMx_BA+0x6C PWM Brake Control Register 0x0000_0000 Reserved BKOD Reserved LVDBKEN CPO2BKEN CPO1BKEN CPO0BKEN BRK1NFSEL BK1SEL Reserved BRK1INV BRK1NFDIS BRKP1EN BRK0NFSEL Reserved Reserved BRK0INV BRK0NFDIS BRKP0EN Bits...
  • Page 981 NuMicro NUC442/NUC472 Series Technical Reference Manual 00 = From external pin BKP1. 01 = From analog comparator 0 output (CPO0). 10 = From analog comparator 1 output (CPO1). 11 = Reserved. [11] Reserved Reserved. Inverse BKP1 State [10] BRK1INV 0 = The state of pin BKPx1 is passed to the negative edge detector. 1 = The inversed state of pin BKPx1 is passed to the negative edge detector.
  • Page 982 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Interrupt Control Register (PWM_INTCTL) Register Offset Description Reset Value PWM_INTCTL PWMx_BA+0x70 PWM Interrupt Control Register 0x0000_0000 Reserved Reserved Reserved DINTTYPE Reserved PINTTYPE Bits Description [31:14] Reserved Reserved. PWM Duty Interrupt Type Selection 0 = DIF[n] will be set if PWM counter matches PWM_CMPDATn register during down counting.
  • Page 983 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Interrupt Enable Control Register (PWM_INTEN) Register Offset Description Reset Value PWM_INTEN PWMx_BA+0x74 PWM Interrupt Enable Control Register 0x0000_0000 Reserved FLIEN Reserved RLIEN Reserved DIEN Reserved BRKIEN PIEN Bits Description [31:30] Reserved Reserved. Falling Latch Interrupt Enable Bit 0 = Falling latch interrupt Disabled.
  • Page 984 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Interrupt Flag Register (PWM_INTSTS) Register Offset Description Reset Value PWM_INTSTS PWMx_BA+0x78 PWM Interrupt Flag Register 0x0000_0000 Reserved CFLIF BRKSTS1 BRKSTS0 CRLIF Reserved BRKLK0 BRKIF1 BRKIF0 Bits Description [31:30] Reserved Reserved. Capture Falling Latch Interrupt Flag 0 = No capture falling latch condition happened.
  • Page 985 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Brake1 Flag 0 = PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one. BRKIF1 1 = When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high. Note: This bit must be cleared by writing 1 to it.
  • Page 986 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Output Enable Control Register (PWM_POEN) Register Offset Description Reset Value PWM_POEN PWMx_BA+0x7C PWM Output Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved POEN Bits Description [31:6] Reserved Reserved. PWM Pin Output Enable Bit 0 = PWM pin at tri-state.
  • Page 987 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Capture Control Register (PWM_CAPCTL) Register Offset Description Reset Value PWM_CAPCT PWMx_BA+0x80 PWM Capture Control Register 0x0000_0000 Reserved FCRLDEN Reserved RCRLDEN Reserved CAPINV Reserved CAPEN Bits Description [31:30] Reserved Reserved. Falling Latch Reload Enable Bits [29:24] FCRLDEN 0 = Falling latch reload counter Disabled.
  • Page 988 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Capture Input Enable Control Register (PWM_CAPINEN) Register Offset Description Reset Value PWM_CAPIN PWMx_BA+0x84 PWM Capture Input Enable Control Register 0x0000_0000 Reserved Reserved Reserved Reserved CAPINEN Bits Description [31:6] Reserved Reserved. Capture Input Enable Bits 0 = PWM Channel capture input path Disabled.
  • Page 989 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Capture Status Register (PWM_CAPSTS) Register Offset Description Reset Value PWM_CAPST PWMx_BA+0x88 PWM Capture Status Register 0x0000_0000 Reserved Reserved Reserved FLIFOV Reserved CRIFOV Bits Description [31:14] Reserved Reserved. Falling Latch Interrupt Flag Overrun Status [13:8] FLIFOV This flag indicates if falling latch happened when the corresponding CFLIF is 1...
  • Page 990 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Capture Rising Latch Register5-0 (PWM_RCAPDAT5-0) Register Offset Description Reset Value PWM_RCAPD PWMx_BA+0x90 PWM Capture Rising Latch Register 0 0x0000_0000 PWM_RCAPD PWMx_BA+0x98 PWM Capture Rising Latch Register 1 0x0000_0000 PWM_RCAPD PWMx_BA+0xA0 PWM Capture Rising Latch Register 2 0x0000_0000 PWM_RCAPD PWMx_BA+0xA8...
  • Page 991 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Capture Falling Latch Register5-0 (PWM_FCAPDAT5-0) Register Offset Description Reset Value PWM_FCAPD PWMx_BA+0x94 PWM Capture Falling Latch Register 0 0x0000_0000 PWM_FCAPD PWMx_BA+0x9C PWM Capture Falling Latch Register 1 0x0000_0000 PWM_FCAPD PWMx_BA+0xA4 PWM Capture Falling Latch Register 2 0x0000_0000 PWM_FCAPD PWMx_BA+0xAC...
  • Page 992 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM0 Synchronous Busy Status Register (PWM_SBS0) Register Offset Description Reset Value PWM_SBS0 PWMx_BA+0xE0 PWM0 Synchronous Busy Status Register 0x0000_0000 Reserved Reserved Reserved Reserved SYNCBUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 counter operation mode CNTMOD (PWM_CTL[16]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
  • Page 993 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM1 Synchronous Busy Status Register (PWM_SBS1) Register Offset Description Reset Value PWM_SBS1 PWMx_BA+0xE4 PWM1 Synchronous Busy Status Register 0x0000_0000 Reserved Reserved Reserved Reserved SYNCBUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When software writes PWM_PERIOD1/PWM_CMPDAT1/PWM_CLKPSC or switch PWM1 counter operation mode CNTMOD (PWM_CTL [17]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
  • Page 994 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM2 Synchronous Busy Status Register (PWM_SBS2) Register Offset Description Reset Value PWM_SBS2 PWMx_BA+0xE8 PWM2 Synchronous Busy Status Register 0x0000_0000 Reserved Reserved Reserved Reserved SYNCBUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When software writes PWM_PERIOD2/PWM_CMPDAT2/PWM_CLKPSC or switch PWM2 counter operation mode CNTMOD (PWM_CTL [18]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
  • Page 995 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM3 Synchronous Busy Status Register (PWM_SBS3) Register Offset Description Reset Value PWM_SBS3 PWMx_BA+0xEC PWM3 Synchronous Busy Status Register 0x0000_0000 Reserved Reserved Reserved Reserved SYNCBUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When software writes PWM_PERIOD3/PWM_CMPDAT3/PWM_CLKPSC or switch PWM3 counter operation mode CNTMOD (PWM_CTL [19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
  • Page 996 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM4 Synchronous Busy Status Register (PWM_SBS4) Register Offset Description Reset Value PWM_SBS4 PWMx_BA+0xF0 PWM4 Synchronous Busy Status Register 0x0000_0000 Reserved Reserved Reserved Reserved SYNCBUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When software writes PWM_PERIOD4/PWM_CMPDAT4/PWM_CLKPSC or switch PWM4 counter operation mode CNTMOD (PWM_CTL [20]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
  • Page 997 NuMicro NUC442/NUC472 Series Technical Reference Manual PWM5 Synchronous Busy Status Register (PWM_SBS5) Register Offset Description Reset Value PWM_SBS5 PWMx_BA+0xF4 PWM5 Synchronous Busy Status Register 0x0000_0000 Reserved Reserved Reserved Reserved SYNCBUSY Bits Description [31:1] Reserved Reserved. PWM Synchronous Busy When software writes PWM_PERIOD5/PWM_CMPDAT5/PWM_CLKPSC or switch PWM5 counter operation mode CNTMOD (PWM_CTL [21]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.

  • Page 998: Enhanced Pwm Generator (Epwm)

    NuMicro NUC442/NUC472 Series Technical Reference Manual 6.22 Enhanced PWM Generator (EPWM) 6.22.1 Overview This device is built in two PWM units with the same architecture which function is specially designed for driving motor control applications. Using the PWM, input capture module and QEI controller with proper control flow by software can easily drive the 3-phase Brushless DC motor, 3-phase AC induction motor and DC motor.

  • Page 999: Pwm Operation

    NuMicro NUC442/NUC472 Series Technical Reference Manual PWM Generator EPWM_CH0 PWM_CH0 & PWM_CH1 PWM_CH0 Set complementary & Freq/Duty EPWM_CH1 timebase Dead-time insertion control EPWM_CH2 PWM_CH2 & PWM_CH3 Polarity Mask PWM_CH2 Set complementary & & & Freq/Duty EPWM_CH3 Dead-time insertion 3-state Brake Control Control EPWM_CH4...

  • Page 1000: Figure 6.22-3 Pwm Time-Base Generator

    NuMicro NUC442/NUC472 Series Technical Reference Manual 16-bit LOAD PWMP Register 4-bit compared CNTEN Counter EPWMx_CLK Counter match 16-bits PWM PWMP/ underflow up/down counter Fpwm Prescaler PWM Period control block (1/1, 1/2, 1/4, 1/16) Writing 1 Interrupt (EPWM_STATUS[2]) to PIF CLKDIV (EPWM_CTLx[3:2]) Edge/Center CNTTYPE...

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