Nuvoton NuMicro NUC029 Series Manuals

Manuals and User Guides for Nuvoton NuMicro NUC029 Series. We have 1 Nuvoton NuMicro NUC029 Series manual available for free PDF download: Technical Reference Manual

Nuvoton NuMicro NUC029 Series Technical Reference Manual (497 pages)

32-bit Arm Cortex-M0 Microcontroller

Brand: Nuvoton | Category: Microcontrollers | Size: 5 MB

Table of Contents
2
List of Tables
11
General Description
12
Features
13
Abbreviations
16
Table 4.1-1 List of Abbreviations
17
Parts Information List and Pin Configuration
18
Numicro NUC029 Series Selection Code
18
Numicro
18
Figure 4.1-1 Numicro
18
NUC029 Series Selection Guide
19
Pin Configuration
20
Numicro NUC029LEE/NUC029SEE Pin Diagram
20
Figure 4.3-1 Numicro
20
Figure 4.3-2 Numicro
21
Pin Description
22
Numicro
22
NUC029LEE/NUC029SEE Pin Description
22
Block Diagram
27
Numicro NUC029LEE/NUC029SEE Block Diagram
27
Figure 5.1-1 Numicro
27
Functional Description
28
ARM Cortex -M0 Core
28
Figure 6.1-1 Functional Controller Diagram
28
System Manager
30
Overview
30
System Reset
30
System Power Distribution
31
Figure 6.2-1 Numicro
31
System Memory Map
32
Register Lock
33
Table 6.2-1 Address Space Assignments for On-Chip Controllers
33
Auto Trim
34
Register Map
36
Register Description
37
System Timer (Systick)
74
Nested Vectored Interrupt Controller (NVIC)
79
Table 6.2-2 Exception Model
80
Table 6.2-3 System Interrupt Map
81
Table 6.2-4 Vector Table Format
81
System Control
105
Clock Controller
113
Overview
113
Figure 6.3-1 Clock Generator Block Diagram
114
Figure 6.3-2 Clock Generator Global View Diagram
115
System Clock and Systick Clock
116
Figure 6.3-3 System Clock Block Diagram
116
Figure 6.3-4 Systick Clock Control Block Diagram
116
Power-Down Mode Clock
117
Frequency Divider Output
117
Figure 6.3-5 Clock Source of Frequency Divider
117
Figure 6.3-6 Frequency Divider Block Diagram
118
Register Map
119
Register Description
120
Table 6.3-1 Chip Idle/Power-Down Mode Control Table
123
Flash Memory Controller (FMC)
142
Overview
142
Features
142
Block Diagram
143
Figure 6.4-1 Flash Memory Control Block Diagram
143
Functional Description
144
Table 6.4-1 Memory Address Map
144
Figure 6.4-2 Flash Memory Organization
145
Figure 6.4-3 Program Executing Range for Booting from APROM and LDROM
149
Figure 6.4-4 Executable Range of Code with IAP Function Enabled
150
Figure 6.4-5 Example Flow of Boot Selection by BS Bit
151
Figure 6.4-6 ISP Flow Example
152
Table 6.4-2 ISP Command List
153
Register Map
154
Register Description
155
External Bus Interface (EBI)
164
Overview
164
Features
164
Block Diagram
165
Functional Description
165
Figure 6.5-1 EBI Block Diagram
165
Figure 6.5-2 Connection of 16-Bit EBI Data Width with 16-Bit Device
166
Figure 6.5-3 Connection of 8-Bit EBI Data Width with 8-Bit Device
166
Figure 6.5-4 Timing Control Waveform for 16-Bit Data Width
168
Figure 6.5-5 Timing Control Waveform for 8-Bit Data Width
169
Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle
170
Register Map
171
Register Description
172
General Purpose I/O (GPIO)
176
Overview
176
Features
176
Basic Configuration
177
Functional Description
177
Figure 6.6-1 Push-Pull Output
177
Figure 6.6-2 Open-Drain Output
178
Figure 6.6-3 Quasi-Bidirectional I/O Mode
178
Register Map
180
Register Description
183
PDMA Controller (PDMA)
195
Overview
195
Features
195
Block Diagram
196
Figure 6.7-1 DMA Controller Block Diagram
196
Basic Configuration
197
Functional Description
197
Figure 6.7-2 CRC Generator Block Diagram
197
Register Map
200
Register Description
202
Timer Controller (TIMER)
233
Overview
233
Features
233
Block Diagram
234
Figure 6.8-1 Timer Controller Block Diagram
234
Figure 6.8-2 Clock Source of Timer Controller
235
Basic Configuration
236
Functional Description
236
Figure 6.8-3 Continuous Counting Mode
237
Register Map
239
Register Description
241
PWM Generator and Capture Timer (PWM)
250
Overview
250
Features
251
Block Diagram
252
Figure 6.9-1 PWM Generator 0 Clock Source Control
252
Figure 6.9-2 PWM Generator 0 Architecture Diagram
252
Figure 6.9-3 PWM Generator 2 Clock Source Control
253
Figure 6.9-4 PWM Generator 2 Architecture Diagram
253
Figure 6.9-5 PWM Generator 4 Clock Source Control
254
Figure 6.9-6 PWM Generator 4 Architecture Diagram
254
Basic Configuration
255
Functional Description
255
Figure 6.9-7 Legend of Internal Comparator Output of PWM-Timer
255
Figure 6.9-8 PWM-Timer Operation Timing
256
Figure 6.9-9 PWM Edge-Aligned Interrupt Generate Timing Waveform
256
Figure 6.9-10 Center-Aligned Type Output Waveform
257
Figure 6.9-11 PWM Center-Aligned Interrupt Generate Timing Waveform
258
Figure 6.9-12 PWM Double Buffering Illustration
259
Figure 6.9-13 PWM Controller Output Duty Ratio
259
Figure 6.9-14 Paired-PWM Output with Dead-Zone Generation Operation
260
Figure 6.9-15 PWM Trigger ADC to Conversion in Center-Aligned Type Timing Waveform
260
Figure 6.9-16 Capture Operation Timing
261
Figure 6.9-17 PWM Group a PWM-Timer Interrupt Architecture Diagram
262
Figure 6.9-18 PWM Group B PWM-Timer Interrupt Architecture Diagram
262
Register Map
265
Register Description
267
Watchdog Timer (WDT)
295
Overview
295
Features
295
Block Diagram
296
Figure 6.10-1 Watchdog Timer Clock Control
296
Figure 6.10-2 Watchdog Timer Block Diagram
296
Basic Configuration
297
Functional Description
297
Figure 6.10-3 Watchdog Timer Time-Out Interval and Reset Period Timing
298
Table 6.10-1 Watchdog Timer Time-Out Interval Period Selection
298
Register Map
299
Register Description
300
Window Watchdog Timer (WWDT)
303
Overview
303
Features
303
Block Diagram
303
Figure 6.11-1 Window Watchdog Timer Clock Control
303
Basic Configuration
304
Functional Description
304
Figure 6.11-2 Window Watchdog Timer Block Diagram
304
Table 6.11-1 Window Watchdog Timer Prescale Value Selection
304
Figure 6.11-3 Window Watchdog Timer Reset and Reload Behavior
305
Table 6.11-2 WINCMP Setting Limitation
306
Register Map
307
Register Description
308
Real Time Clock (RTC)
313
Overview
313
Features
313
Block Diagram
314
Basic Configuration
314
Functional Description
314
Figure 6.12-1 RTC Block Diagram
314
Register Map
318
Register Description
320
UART Interface Controller (UART)
336
Overview
336
Features
336
Block Diagram
337
Figure 6.13-1 UART Clock Control Diagram
337
Basic Configuration
338
Figure 6.13-2 UART Block Diagram
338
Functional Description
339
Table 6.13-1 UART Interface Controller Pin
339
Table 6.13-2 UART Baud Rate Equation
339
Table 6.13-3 UART Controller Baud Rate Parameter Setting Table
340
Figure 6.13-3 Transmit Delay Time Operation
341
Table 6.13-4 UART Controller Baud Rate Register (UA_BAUD) Setting Table
341
Table 6.13-5 UART Controller Interrupt Source and Flag List
343
Table 6.13-6 Controller Interrupt Source and Flag in DMA Mode List
343
Table 6.13-7 UART Line Control of Word and Stop Length Setting
344
Table 6.13-8 UART Line Control of Parity Bit Setting
344
Figure 6.13-4 Auto Flow Control Block Diagram
345
Figure 6.13-5 UART CTS Auto Flow Control Enabled
345
Figure 6.13-6 UART RTS Auto Flow Control Enabled
346
Figure 6.13-7 UART RTS Flow with Software Control
346
Figure 6.13-8 Irda Control Block Diagram
347
Figure 6.13-9 Irda TX/RX Timing Diagram
348
Figure 6.13-10 Structure of LIN Frame
348
Figure 6.13-11 Structure of LIN Byte
349
Table 6.13-9 LIN Header Selection in Master Mode
349
Figure 6.13-12 Break Detection in LIN Mode
351
Figure 6.13-13 LIN Frame ID and Parity Format
352
Figure 6.13-14 LIN Sync Field Measurement
354
Figure 6.13-15 UA_BAUD Update Sequence in Automatic Resynchronization Mode When
355
Figure 6.13-16 UA_BAUD Update Sequence in Automatic Resynchronization Mode When LINS_DUM_EN (UA_LIN_CTL[3])= 0
355
Figure 6.13-17 RS-485 RTS Driving Level in Auto Direction Mode
358
Figure 6.13-18 RS-485 RTS Driving Level with Software Control
358
Figure 6.13-19 Structure of RS-485 Frame
359
Register Map
360
Register Description
362
I 2 C Serial Interface Controller
389
Overview
389
Features
389
Basic Configuration
390
Block Diagram
390
Functional Description
390
Figure 6.14-1 I 2 C Controller Block Diagram
390
Figure 6.14-2 I 2 C Bus Timing
391
Figure 6.14-3 I 2 C Protocol
391
Figure 6.14-4 START and STOP Conditions
392
Figure 6.14-5 Bit Transfer on the I 2 C Bus
393
Figure 6.14-6 Acknowledge on the I 2 C Bus
393
Figure 6.14-7 Master Transmits Data to Slave
393
Figure 6.14-8 Master Reads Data from Slave
394
Figure 6.14-9 Control I C Bus According to Current I C Status
394
Figure 6.14-10 Master Transmitter Mode Control Flow
395
Figure 6.14-11 Master Receiver Mode Control Flow
396
Figure 6.14-12 Save Mode Control Flow
397
Figure 6.14-13 GC Mode
398
Figure 6.14-14 Arbitration Lost
399
Figure 6.14-15 I 2 C Data Shifting Direction
400
Figure 6.14-16 I 2 C Time-Out Count Block Diagram
402
Table 6.14-1 I 2 C Status Code Description
402
Example for Random Read on EEPROM
403
Figure 6.14-17 EEPROM Random Read
403
Figure 6.14-18 Protocol of EEPROM Random Read
404
Register Map
405
Register Description
406
Serial Peripheral Interface (SPI)
416
Overview
416
Features
416
Block Diagram
417
Basic Configuration
417
Functional Description
417
Figure 6.15-1 SPI Block Diagram
417
Figure 6.15-2 SPI Master Mode Application Block Diagram
418
Figure 6.15-3 SPI Slave Mode Application Block Diagram
418
Figure 6.15-4 32-Bit in One Transaction
419
Figure 6.15-5 Variable Bus Clock Frequency
421
Figure 6.15-6 Byte Reorder Function
421
Figure 6.15-7 Timing Waveform for Byte Suspend
422
Figure 6.15-8 Bit Sequence of Dual Output Mode
423
Figure 6.15-9 Bit Sequence of Dual Input Mode
423
Figure 6.15-10 FIFO Mode Block Diagram
424
Timing Diagram
425
Figure 6.15-11 SPI Timing in Master Mode
426
Figure 6.15-12 SPI Timing in Master Mode (Alternate Phase of SPI Bus Clock)
426
Figure 6.15-13 SPI Timing in Slave Mode
427
Figure 6.15-14 SPI Timing in Slave Mode (Alternate Phase of SPI Bus Clock)
427
Programming Examples
428
Register Map
430
Register Description
431
USB Device Controller (USBD)
447
Overview
447
Features
447
Block Diagram
448
Basic Configuration
448
Functional Description
448
Figure 6.16-1 USB Device Block Diagram
448
Figure 6.16-2 Wake-Up Interrupt Operation Flow
450
Figure 6.16-3 Endpoint SRAM Structure
451
Figure 6.16-4 Setup Transaction Followed by Data in Transaction
452
Figure 6.16-5 Data out Transfer
452
Register Map
453
Register Description
455
Analog-To-Digital Converter (ADC)
472
Overview
472
Features
472
Block Diagram
473
Basic Configuration
473
Figure 6.17-1 ADC Controller Block Diagram
473
Functional Description
474
Figure 6.17-2 ADC Clock Control
474
Figure 6.17-3 Single Mode Conversion Timing Diagram
475
Figure 6.17-4 Single-Cycle Scan on Enabled Channels Timing Diagram
476
Figure 6.17-5 Continuous Scan on Enabled Channels Timing Diagram
477
Figure 6.17-6 VBG for Measuring AV DD Application Block Diagram
478
Figure 6.17-7 A/D Conversion Result Monitor Logics Diagram
479
Figure 6.17-8 A/D Controller Interrupt
480
Register Map
481
Register Description
482
Figure 6.17-9 ADC Single-End Input Conversion Voltage and Conversion Result Mapping
483
Figure 6.17-10 ADC Differential Input Conversion Voltage and Conversion Result Mapping
484
Electrical Characteristics
494
Package Dimensions
495
64-Pin LQFP (7X7X1.4 MM Footprint 2.0 MM)
495
48-Pin LQFP (7X7X1.4 MM Footprint 2.0 MM)
496
Revision History
497

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Nuvoton NuMicro NUC029 Series Manuals

Nuvoton NuMicro NUC029 Series Technical Reference Manual (497 pages)

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