Wiznet WizFi210 User Manual page 19

I2C_CLK/GPIO9 (*)
21
22 PWM0/GPIO10
GPIO19/CLK_44M
23
Hz (*)
GPIO20/CLK_22M
24
Hz (*)
GPIO21/CLK_11M
25
Hz (*)
I2C_DATA/GPIO8
26
(*)
SSPI_MISO (*)
27
SSPI_CLK (*)
28
SSPI_CS (*)
29
SSPI_MOSI (*)
30
GND
31
VIN_3V3
32
EN_1V8
33
VDDIO(**)
34
35 EXT_RESETN
UART1_CTS/GPIO
36
26 (*)
UART1_RTS/GPIO2
37
7
WizFi 210/220 User Manual
IO Pull-down
O Pull-down
I Pull-down
I Pull-down
I Pull-down
IO Pull-down
O Pull-up
I Pull-up
I Pull-up
I Pull-down
P NA
P NA
I NA
P NA
IO Pull-up
I Pull-down
O Pull-down
(WIZnet Co., Ltd.)
Inter-Integrated Circuit Clock / General
Purpose Input Output
Pulse Width Modulator / General Purpose
Input Out-put
Internal Clock Circuitry Test Point / General
Purpose Input Output
Internal Clock Circuitry Test Point / General
Purpose Input Output
Internal Clock Circuitry Test Point / General
Purpose Input Output
Inter-Integrated Circuit Data / General
Purpose Input Output
SPI Slave Transmit Data Output to the
HOST
SPI Slave Clock Input from the HOST
SPI Slave Chip Select Input from the HOST
SPI Slave Receive Data Input from the
HOST
Ground
Single Supply Port
Internal 1.8V regulator enable port-Active
High
All I/O voltage domain (can be tied to
VIN_3V3 or tied to HOST I/O supply)
Module Hardware Reset Input and Power
Supply Reset Monitor Indictor
Universal Asynchronous Receiver
Transmitter 1 Clear to Send Input / General
Purpose Input Output
Universal Asynchronous Receiver
Transmitter 1 Request to Send Output /
General Purpose Input Out-put /
Firmware Program Mode
It support download mode at high during
boot
13