Nuvoton Mini51 Series Manuals

Manuals and User Guides for Nuvoton Mini51 Series. We have 1 Nuvoton Mini51 Series manual available for free PDF download: Technical Reference Manual

Nuvoton Mini51 Series Technical Reference Manual (342 pages)

Brand: Nuvoton | Category: Microcontrollers | Size: 5 MB

Table of Contents
2
General Description
10
Features
11
Parts Information List and Pin Configuration
14
Numicro Mini51 Series Product Selection Guide
14
Figure 3.1-1 Numicro Mini51 Series Product Selection Guide
14
Pin Configuration
15
LQFP 48-Pin
15
Figure 3.2-1 Numicro Mini51 Series LQFP 48-Pin Assignment
15
QFN 33-Pin
16
Figure 3.2-2 Numicro Mini51 Series QFN 33-Pin Assignment
16
Pin Description
17
Table 3.3-1 Numicro Mini51 Series Pin Description
20
Block Diagram
21
Numicro Mini51™ Block Diagram
21
Figure 4.1-1 Numicro Mini51 Series Block Diagram
21
Functional Description
22
Memory Organization
22
Overview
22
System Memory Map
23
Table 5.1-1 Address Space Assignments for On-Chip Modules
23
Nested Vectored Interrupt Controller (NVIC)
24
Overview
24
Features
24
Exception Model and System Interrupt Map
24
Table 5.2-1 Exception Model
25
Vector Table
26
Table 5.2-2 System Interrupt Map
26
Table 5.2-3 Vector Table Format
26
NVIC Operation
27
NVIC Control Registers
28
Interrupt Source Control Registers
41
System Manager
47
Overview
47
System Reset
47
System Power Distribution
47
Figure 5.3-1 Numicro Mini51 Series Power Distribution Diagram
48
Memory Mapping Table
49
Table 5.3-1 Memory Mapping Table
49
System Manager Control Registers
50
Clock Controller
75
Overview
75
Clock Generator
75
Figure 5.4-1 Clock Generator Block Diagram
75
System Clock and Systick Clock
76
Figure 5.4-2 System Clock Block Diagram
76
Figure 5.4-3 Systick Clock Control Block Diagram
76
AHB Clock Source Selection
77
Figure 5.4-4 AHB Clock Source for HCLK
77
Peripheral Clock Source Selection
78
Figure 5.4-5 Peripherals Clock Source Selection for PCLK
78
Table 5.4-1 Peripherals Engine Clock Source Selection Table
79
Power-Down Mode Clock
80
Frequency Divider Output
81
Figure 5.4-6 Clock Source of Frequency Divider
81
Figure 5.4-7 Block Diagram of Frequency Divider
81
Clock Control Register Map
82
Clock Control Register
83
Table 5.4-2 Power-Down Mode Control Table
85
Comparator Controller (CMPC)
98
Overview
98
Features
98
Block Diagram
99
Figure 5.5-1 Analog Comparator Block Diagram
99
Functional Description
100
Figure 5.5-2 Comparator Controller Interrupt Sources
100
Comparator Reference Voltage (CRV)
101
Figure 5.5-3 Comparator Reference Voltage Block Diagram
101
Register Map
102
Register Description
103
Analog-To-Digital Converter (ADC) Controller
107
Overview
107
Features
107
Block Diagram
108
ADC Operation Procedure
108
Figure 5.6-1 ADC Controller Block Diagram
108
Figure 5.6-2 ADC Clock Control
109
Figure 5.6-3 A/D Conversion Result Monitor Logics Diagram
110
Figure 5.6-4 A/D Controller Interrupt
110
ADC Register Map
111
ADC Register
112
Flash Memory Controller (FMC)
121
Overview
121
Features
121
Block Diagram
121
Figure 5.7-1 Flash Memory Control Block Diagram
122
Functional Description
123
Table 5.7-1 Memory Address Map
123
Figure 5.7-2 Flash Memory Organization
124
Table 5.7-2 Boot Selection Table
125
Table 5.7-3 Data Flash Table
125
Figure 5.7-3 Flash Memory Structure
126
Table 5.7-4 Data Flash Configuration Example
129
Figure 5.7-4 ISP Procedure
130
Figure 5.7-5 ISP Operation Flow
131
Table 5.7-5 ISP Command Table
132
Flash Control Register Map
133
Flash Control Register
134
General Purpose I/O
142
Overview
142
Features
142
Functional Description
142
Figure 5.8-1 Push-Pull Output
143
Figure 5.8-2 Open-Drain Output
143
Figure 5.8-3 Quasi-Bidirectional I/O Mode
144
Port 0-5 Control Register Map
145
Port 0-5 Control Register
149
I 2 C Serial Interface Controller (Master/Slave)
167
Overview
167
Features
167
Figure 5.9-1 Bus Timing
167
C Protocol
168
Figure 5.9-2 I 2 C Protocol
168
Figure 5.9-3 Master Transmits Data to Slave
168
Figure 5.9-4 Master Reads Data from Slave
169
Figure 5.9-5 START and STOP Condition
169
Figure 5.9-6 Bit Transfer on the I C Bus
170
I 2 C Protocol Registers
171
Figure 5.9-7 Acknowledge on the I C Bus
171
Figure 5.9-8 I 2 C Data Shifting Direction
172
Figure 5.9-9 I 2 C Time-Out Count Block Diagram
173
Register Mapping
174
Register Description
175
Operation Modes
184
Master Transmitter Mode
184
Master Receiver Mode
184
Slave Receiver Mode
184
Slave Transmitter Mode
184
Data Transfer Flow in Five Operation Modes
184
Figure 5.9-10 Legend for the Following Five Figures
185
Figure 5.9-11 Master Transmitter Mode
186
Figure 5.9-12 Master Receiver Mode
187
Figure 5.9-13 Slave Transmitter Mode
188
Figure 5.9-14 Slave Receiver Mode
189
Figure 5.9-15 GC Mode
190
Enhanced PWM Generator
191
Overview
191
Features
191
Figure 5.10-1 Application Circuit Diagram
192
PWM Block Diagram
193
Figure 5.10-2 PWM Block Diagram
193
Figure 5.10-3 PWM Generator 0 Architecture Diagram
193
Figure 5.10-4 PWM Generator 2 Architecture Diagram
194
Figure 5.10-5 PWM Generator 4 Architecture Diagram
194
PWM Function
195
Figure 5.10-6 Edge-Aligned PWM
196
Figure 5.10-7 PWM Edge-Aligned Waveform Output
196
Figure 5.10-8 Edge-Aligned Flow Diagram
197
Figure 5.10-9 Legend of Internal Comparator Output of PWM-Timer
198
Figure 5.10-10 PWM Timer Operation Timing
198
Figure 5.10-11 Center-Aligned Mode
199
Figure 5.10-12 PWM Center-Aligned Waveform Output
200
Figure 5.10-13 Center-Aligned Flow Diagram (INT_TYPE = 0)
201
Figure 5.10-14 PWM Double Buffering Illustration
202
Figure 5.10-15 PWM Controller Output Duty Ratio
202
PWM Operation Modes
203
Figure 5.10-16 Dead-Zone Insertion
203
Polarity Control
204
Figure 5.10-17 Initial State and Polarity Control with Rising Edge Dead-Zone Insertion
205
PWM for Motor Control Interrupt Architecture
206
PWM Brake Function
206
Figure 5.10-18 Motor Control PWM Architecture
206
PWM Controller Register Map
207
PWM Controller Register
208
Serial Peripheral Interface (SPI) Controller
228
Overview
228
Features
228
SPI Block Diagram
228
Figure 5.11-1 SPI Block Diagram
228
Functional Description
229
Figure 5.11-3 SPI Slave Mode Application Block Diagram
229
Figure 5.11-4 Two Transfer (Burst Mode) in One Transaction
231
Figure 5.11-5 Word Suspend Mode
231
Figure 5.11-6 Byte Reorder
232
Figure 5.11-7 Byte Suspend Mode
232
Figure 5.11-8 Variable Serial Clock Frequency
233
Table 5.11-1 Byte Order and Byte Clock Idle Internal Conditions
233
Figure 5.11-9 SPI Timing in Master Mode
234
Figure 5.11-10 SPI Timing in Master Mode (Alternate Phase of SPICLK)
235
Figure 5.11-11 SPI Timing in Slave Mode
235
Figure 5.11-12 SPI Timing in Slave Mode (Alternate Phase of SPICLK)
236
SPI Serial Interface Control Register Map
239
Register Description
240
Timer Controller
251
Overview
251
Features
251
Block Diagram
252
Figure 5.12-1 Timer Controller Block Diagram
252
Figure 5.12-2 Clock Source of Timer Controller
252
Functional Description
253
Figure 5.12-3 Continuous Counting Mode
254
Table 5.12-1 Input Capture Mode Operation
255
Register Map
257
Register Description
258
UART Interface Controller
267
Overview
267
Table 5.13-1 UART Baud Rate Setting Table
267
Table 5.13-2 UART Baud Rate Setting Table
267
Features
269
Block Diagram
270
Figure 5.13-1 UART Clock Control Diagram
270
Figure 5.13-2 UART Block Diagram
271
Functional Description
273
Figure 5.13-3 Auto Flow Control Block Diagram
273
Figure 5.13-4 Irda Block Diagram
274
Figure 5.13-5 Irda TX/RX Timing Diagram
275
Figure 5.13-6 Structure of RS-485 Frame
277
Registers Map
278
Register Description
279
Table 5.13-3 UART Interrupt Sources and Flags Table in Software Mode
294
Table 5.13-4 UART Baud Rate Setting Table
297
Watchdog Timer
302
Overview
302
Table 5.14-1 Watchdog Time-Out Interval Selection
302
Features
303
Block Diagram
303
Figure 5.14-1 Timing of Interrupt and Reset Signal
303
Figure 5.14-2 Watchdog Timer Clock Control
303
Figure 5.14-3 Watchdog Timer Block Diagram
304
Watchdog Timer Control Registers Map
305
Register Description
306
Arm ® Cortex™-M0 Core
309
Overview
309
Figure 6.1-1 Functional Block Diagram
309
Features
310
System Timer (Systick)
311
System Timer Control Register Map
312
System Timer Control Register
313
System Control Registers
316
System Control Register Memory Map
316
System Control Register
317
Application Circuit
324
Electrical Characteristics
325
Absolute Maximum Ratings
325
DC Electrical Characteristics
326
AC Electrical Characteristics
331
External Input Clock
331
External 4 ~ 24 Mhz XTAL Oscillator
331
Typical Crystal Application Circuit
331
External 32.768 Khz XTAL Oscillator
332
Internal 22.1184 Mhz RC Oscillator
332
Figure 8.3-1 Typical Crystal Application Circuit
332
Internal 10 Khz RC Oscillator
333
Analog Characteristics
334
Brown-Out Reset (BOD)
334
Low Voltage Reset (LVR)
334
Analog Comparator
334
Analog Comparator Reference Voltage (CRV)
335
10-Bit ADC
335
Flash Memory Characteristics
337
Package Dimension
338
48-Pin LQFP
338
33-Pin QFN (4Mm X 4Mm)
339
33-Pin QFN (5Mm X 5Mm)
340
Revision History
341

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Nuvoton Mini51 Series Technical Reference Manual (342 pages)

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