200 Frequency Compensation Tests - Keithley 2002 Repair Manual

Troubleshooting

2.11.22 /200 frequency compensation tests

Test 408.1 — Circuit setup for test 408.2
Type
Fault message
Description
Drawing reference
Bit patterns
Test 408.2 — Signal stored for test 408.3
Type
Fault message
Description
Drawing reference
2-86
Circuit Exercise
None
In this series of tests, DAC A of U433 is used to exercise the frequency compensation capacitors
C459 and C461 of NET1, R488 (/100). In this phase, DAC A is programmed with 1s (no com-
pensation), and the pin 2 output is tied to C461. BUFF is applied to NET1 (R488) through R493.
The divided voltage pin 4 is tied to AC buffer Q418 and U423 through U428 and Q422. The sig-
nal AMP IN is tied through U425, U426, to Q510. This phase sets up the conditions for the next
phase; there is no measurement in this phase.
Analog Board; 2002-100
—U811—
00001101
—U224—
00010111
—U400— —U432—
01111101 11111111
*Bits associated with register IC terminals as follows:
Q Q Q Q
87654321 87654321
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4.
Circuit Exercise
None
The SELFTEST control line turns ON Q425 and forces the voltage on NET1 (R488) to ground.
The response of R488 pin 4 is stored in C439. This test uses the same path as test 408.1 except
as follows: when the SELFTEST control line forces the divider voltage to zero, it also generates
a one-shot pulse 5ms after SELFTEST goes low. This pulse turns Q414 on and stores the voltage
on C439. The 5ms delay that turns on Q414 comes from U402 and U425. Note that no measure-
ment is made during this test phase.
Analog Board; 2002-100
Bit pattern*
—U810—
00000011
—U206—
01110000
—U203—
10001110
—U411—
00111011
Q Q Q Q
87654321 87654321
Register
—U809— AD_STB
11100111
—U207— MUX_STB
11001111
—U221— R1_STB
11101001
—U406— R2_STB
01101110