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7-5. MN1292 VIDEO
SIGNAL GON:r ... ROl lc."
The systems using both the CRT (720x3S0) and th e LCD (640x200)
without difficulty.
This LSI is packed in a
100~pin
flat package
and uses CMOS
technorogy.
1. FEATURES
1-1. Both LCD and CRT Mode
Display Format
Colors
1-2. LCD Mode
Character Mode (80
Monochrome
x2S)
LCD Panel
Panel Image
Character Font
Attribute Types
Intensity Types
640x200 (l-Panel,
Normal, Reverse
8x8 dots
2-Panel)
1-3. CRT Mode
Display Monitor
Character Font
Mode
1, Mode 2
Half-Tone, Alternate
720x3S0
9x14 dots
Note:
The MN1288 is a LCD/CRT controller.
2. PIN DESCRIPTIONS
2-1, Pin Assignment
vss
XO
HSYNC
VSYNC
RAO
RAl
RA2
RAJ
1s/2S
CRT/LCD
cca
CC7
CC,
CC5
CC,
CC3
CC2
CCl
CCO
ROMADR
RD7
RD'
RD5
RD'
VDD
2
3
,
5
,
7
a
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MN1292
(TOP VIEW)
Figure 2-1. Pin assignment
Font
~
om
nH
~
Ie t:::le
75 fo---VDD
74 r--ADRDEC
731-91
72 _cPMES
71_~
70 _
"""""
69 fo---iOW
68
r--JOR
67 i---U
66 -AS
6S - A 2
64 -A1
63
-AO
62 1--00
61
i=~l
60
02
59
i=f 3
58
I--~'
57
05
56 1--06
55
1--07
54
~:r.""
53
DIA
~~
r-
RAMA
r-..<o~~
I-vss
~II~~
7 -12
-
P C-7200
2-2. Pin Descriptions
~-N
...
~A-Nam
...
--J/.O
~Ae{Ijo
I
VSS
System ground
2
XO
a
Output osc
3
HSYNC
I
Input HSYNC signal
4
VSYNC
I
Input VSYNC signal
5-8
RAO-RA3
I
Input raster addresses to control underline
9
1S/2S
I
Input signal to select the LCD format
IS/2S is HIGH: I-Panel format
I S/2s is lOW : 2 - Panel format
10
CRT /LCD
I
Input signal to select the CRT and thelCD
CRT
1L'Ci5
is HIGH: CRT mode
CRT /LCD
is
LOW
: LCD mode
11-19
CC8-CCO
0 *2
Output address to the C. G. ROM
20
ROMADR
a *1
Output address to the C. G. ROM
CRT mode: ROMADR is HIGH
LCD mode: ROMADR is LOW
21-24
RD7-RDO
I
Input data from the C. G. ROM
27 -30
25
VDD
+5V Power supply
26
VSS
System ground
31-36 MD7-MDO I/O *2 Bi
directional data with the video RAM
36,40
37
VSS
System ground
39
VDD
+5V Power supply
41
CRTRAS
a *2
Output signal to enable row address of
the MN1288
42
CRTRAS
a *2
Output signal to enable column address
of the MNI288
4J
PGAD1
a *2
Output address to the video RAM
44
RAS
I/O *2
Output RAS signal to the video RAM
45
CAS
0 *2
Output CAS signal to the video RAM
46
N
a *2
Output DE signal to the video RAM
47
WE
0 *2
Output WE signal to the video RAM
48
CPURAS
a *2
Output signal to enable row address of
the CPU
49
CPUCAS
a *2
Output signal to enable column addressof
the CPU
50
VDD
+5V Power supply
51
VSS
System ground
52
RAMA
a *2
Output address to the video RAM
53
DIR
a *2
Output signal to control the data bus
54
GATE
a *2
Output signal to control the data bus
55-62
07-DO
I/O *2 Bi
directional data with the CPU
63-66
A3-AO
I
Input address from the CPU
67
CE
I
Input Signal to enable the MNI292
CE is lOW: the MNI292 is active
66
lOR
I
Input signal to read internal registers
69
lOW
I
Input signal to write internal registers
70
MEMW
I
Input signal to write the video RAM
71
RESET
I
Input signal to reset the system
72
CPMES
I
Input signal to control the video RAM
access by the CPU
73
Q1
a
Output latch signal to the address MPX
74
ADRDEC
I
Input signal to address the internalregisters
by the CPU
75
VDD
+
5V Power supply
76
VSS
System ground
77
XACK
0 *2
Output write signal to the
CPU
78
V
D *2
Output vertical sync signal
79
H
a *2
Output horizontal sync signal
60
VIDEO
a *2
Output video signal
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