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Sharp PC-7200 Service Manual page 20

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. (256K-..bit-Er-RAMs); 1.92 milliseconds to cQunt up
J
28-row addresses
(~4K~bit
p-RAM,rFlgure2"16 showsi
D-RAMfef;estiin~n1,
and
Figure,2-17 shaws_]the; D-RAM--refresh~ent<ttrping, chart)
.1
'CF'UHlCA
,1'°'-0
'fiiC-v~
-
s Ysco."·· ·co
,-,·r-"Lrll ,,-••
,r-U"""L--,",-r,--,, ''-_'"L
• DMACLK
~,
~<
~,
~,
~,
CPUHRQ
-I,
Figure 2-17. Timing chart of D-RAM.refreshment
:,i
,.:",,)\'.1., ,'j,,-"':"
, ' ,
2-2-8_ 1/0
Address Decoding
Circuit (Figure 2-18)
This circUIt is"j'nclJded'lr, 'the 8C4752 as shown in Rgure 2-18. The
role-,of this circuit-·is tp
outp~t
the
chi~
_
select
si~nal$
to ·ei;l,ch related
Circuit
a:ccofdi~g
to Uie a:adress signals XAO fhrougn XA9.'However,
an~enable/disable'
status and channel- select status of
t_he~following
interlace
-arcult
is selected by DIP switches 84-1 through 84-5 as
shown_table.2~7.
.
Floppy di~k--drive interlace- circuit
Printer inteMace circuit'
Serial interlace
The AEN.signal, ob1ained 'by ANDing 1he HLDA and MASTER
-
sjgi1~ls.'ii').Qic:at_i;i~';tn~tJlje C~U-i~_'~xeputillg
hqld cycles. This signal
is emitted on these conditions: DMA operation, refreshment for
D-RAMs;
~md' accessln~r-of
the resources on the main PWB by an
extenw,J
miQrQP_JQ~e$SPI,
When_the AE;N signal becomes
HIGH,
the
I/O decoding--circuit-ts~deactivated. Tablei 2-8 shows the relationship
betwe~~t~~_lVP;~Rgr~~~:jand the;H:f:1,jJ?;s~lr~ sjQ~~h
,J, .• ,'.
,,;~,
1_
--j
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j.
L..- '',.'.'
;,-1 ,""
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:
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j
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iii·
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i-·l; 'I!) II Eo")·, di
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:]
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r
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:.'
MN1292
MONO
ADAPTER
MN1294
COLOR
ADAPTER
i!
Internal FDC
ON
,':.L.
'.,.3F"a.~._
.•
3,F7,. ,.',
Add[ess.:..~~I_~~t,.
"
'.
'--,
, - ;"t,r;;)I;'
'I
W2F,B,72Ff . ,
Internal Parallel Port'
L:m -37 A
_ ...... H. : . . 2,.7."B - . . ".2 . . . 7 A.
.
Addre,s.s, Select,··
:
:f~'Y: : 1:,,)
Signal Name
Address
R/W
Device
CSB042
60,64
R/W
Keyboard Interface
AS
70
W
RTC Address Strobe
CMSSEL
70
W
C MOS RAM SELECT
OS
71
R
RTC/C MOS RAM Read
R/W
71
W
RTC/MRS RAM W,i1e
CSNPX
FB-FF
R/M
B02B7 NPX
CSCRTC
JBO-JBF
R/W
Monochrome Adaptor
(MONO~LOW)
JOO-30F
R/W
Color Graphic Adaptor
(CllA~LOW)
10SI
R/W
This signal
lOW
indicates CPU or
MASTER Device accesses 1he
device in the SC4752.

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