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015 -00
'I l')ili'!Ii'l
,-
};;'~l:-r,
.'
.- -:-:'11,-,1'1
\~( '_i~iQOJ',ti~!:Ii~c!~~;(
fi1
c~:)il ill"'l!;
;i
,~il
ij)']';
i
j.
iJ 9H~r~ti,~.I?) 8~ Itry\t3f.~~386
begins after
,a:~fnGf'P~tO)Qr([)W}fransitiOf:i'O'f.,.·RESEl':)
;::Th'eii
HIGH
j
foJ
l:OWi;ttansiti6n
.'l~jQt
RESJ;:,Ti :mu§tl
~;~,.~ynchronous
to
inEi'r-~¥st~iTP
cr8clf!'
1Appfoxrm~h!lyr'50'::sys1e'm ~'adCkjcYcles·
-are':requli"e-d
by the'
CPU
for interanl initializations before the first bus cycle to
fet~R'-b;-~cba~Ef':Hm;
th-e
tp3iw'~r-'::i:in
-: tin)
1i!'Jr"
;;-:':exec'U'ti6fii1tBcfres'S\''is performed.
14.
Ji'"j
·)n;.; /\.o;J )
l~YI ~tf1oj
:
-)j:/V
~C6\v
1' t i
'
FifGF·fr'fr~l,sition
of RESET synchronous to the system clock will end a processor"·.c.ycle,.at
I
~
'_'">s.'&
(;\,;; tj'"
'r;,')~;:-~~ '>.o-xni,
i"ij
:';"Ji-~~~: ~;~~~~'i~'~'~~~jJO ~OW transiti~n
of the C!OCk.
·lh"~~:~-?;~:·t~ "I;l\~.Ij' ~f.'!r.~mo.n
..
~,f]1~"~-,S~T2!P;!l;}l-:P.~i:
,~
",'" lJ '
;li1;J.i":
,'j,]
~~',-;:T',
-,' . j;-
~:f)
;=-1nVT(
,~,a.~~~_~~~9~9~-tJ~\!r,t, system clock, however,{:._J[lltBiS) casecJthcaonoJ::be~_p(e~ejer"mrne9':'Y",hl.ch;p.ha:~');!';'Slf
:;,)
':J:;;
li',";/";' LJ) ;\', \;-;
'j.
E ,1:-,
~)
j; --
•
A9~>.pmc~~,~F!rj QJC!c~'Jwill occur durinItJ,tHe':ne~f\-systeiir:clbtj{.!·per'iod}'.;Sy(rChtdr:lCiuSi -lOW.;
to
.HIGH
,tran'sitidns
;·,q~;ij:£S;~T
:
ar~
l ,re,Q!"!!red only for syste ms
wh'ehjYtPle!~~roc-~:s)sOr ~'ero~l(':iri
us:tl
b' E !'
'ptia'se;,'gyrl'chrono\fsl,-to
ClK
\J"
;' - a1:- .,' "
: ' I
j
) 1
f;,
"-1' - :
~~,.
015
00
-'
51
36
'"
'
i-"
,7.:"?':
)1
1 0 -18
~ 1-~.3,4-'
4, 5
another clock.
'i b'!!:-'-l,---;, , ,
-->:' ,'J
--'<i.'\;"1:<;
L':J) <:H-':J
~:)jj)'ilf:n:'
J:-I'
!.;
~;.,
]3:;
~~):
;\
Sys:fem~
olobk':ProYides:'the fundamental timing for 80286 systems. It is divided by two inside''t'ri'e'
'CP'U
;
;~r
.
,i;~"'i ,-:,~ ::,::;~0'~~,~,~~r~,t4 '~e,)!d,l::essor
clock. The internal divide-by two
circuitry,:-,s~9.:,qe'I~~YDch5q~i~~~~;
tp_ja_p
&Jt_e~qal
l' -;
,:
'cloCK )gerieratclr'jj"y a lOW to
HIGtLtr;~F);;;jti91l .9nli,tJ1!L~~S,~)LiIlPJ-!t-..n)d _+--,r:j;L:~
,3-)i.,j'; -
"';:'
1 ,:
I/O
o
' . Q
,
o
Data Bus inputs data during memory,-:I/O.' and interr.tfpt 'acknoWledge r.ead' cycles;,,0l:ltputs:,da_taldurjng
1
~;"D0~~ ~nd 1/~"wr~~
cycles. The data bus
IS
active HIGH and floats to 3-state OFF 'during! blisnold
ackno,wle,dge.
IBlIS-'Hi~\rEnable indicates transfer of data on the upper bytes
o't
the data bus.
015
08. Eight-bit
.-_,1
;'
.'
,~,
_ _
oriented- dev:ic8$-, assigned to the upper bytes of the data bus would
norn;rclUIl,:_!.l.se-'.BHEjto~con:.dition
chip
selec~,
1u,I'
nctidns. BHE is active; LGW ahd'-floats
,ta,
3'''-,st~te
OfFliii:lurihg.
:'b~~, ·h~ld'-~~Ckri~,~;e:<;1~'~.
'o"'!I'"
'::"1--,,
"
.-"n"
.
I::, 1
BHE~--V:alue
"
, 'l
L
L
L
L
L
L
H
H
H
H
H
H
H
H
M/iO
L
L
L
L
H
H
H
H
L
L
H
H
H
H
BHE and
AO
Encodings
'~);'
'J,lWord transfe',,',
'
'1:
>'"
"')jJn,~:
H
Byte translEWbn'i,upper;'h~lf of;
dati
-bus,
W1-5
~:D8'¥;
,
L
Byte transfer on lower half of data bus (07 - DO)
H
Reserved
S1
so
Bus Cycle Initiate-if"
,:J,
t ,'J
L
L
1
~
h;
}')j';';
.ID~~!,r;~p,~,:..ctqMo;~}~.q,~~
J)
ld~_
':,;' , ;. \ ..
hI!
L
!:i
-IIH; 'i,'11
,R,e,~e.~v-!;!,d\"T;J"-·
H'
H"
L
L
H
H
r:_~
_'l'.d,;_
"H
Re.s,erli,ed,,1(;i
,.:;;,-.):
I! ;Ii':
,:~j:-,:
'i.l,
i
l '
',)
None,~)rrib'twa
tshitos:"cycle-"
H:;
"
"!'-::J !~'( I).,::
If
A 1
=
1
then halt; els'e,Js'h'ut'doWHl
s
'~.iJ
J1J.si:,,\.---
Memory data read
Memory
data';JY{~ji.W'I~:;:\:' '~:l'~:';it~:
:: , .. ",
::·~,;j],::./Ti
None; not a status cycle
L
II
117:1:
H
L
H
L
Res~'~'l'9]9 i~,
,!,
I
'-:,'n":>h;;
')]:j:
':,Itrj:;;~']f)~q .l- ),B~'-;
')Hl;n;l~;tlOijr~adrjJ JjJ~I'/v
,_;l,I,j,'
'lj!!,.',i,:
'J,'
,;'<','
)i!'JU
fPi
;,:r;'.11.1:.
'-11:J
)cll/.O-,w:r.itel'l)
;:U
",;'1.j,r:');'J:J
;;,1:.,
,lV!};-:
,_»ITHJyj
Hi '.
p; -'
~r i,.'I;~, NO'n'e;:j-rIM"ai'staiti~',;'dycle
;1.
:-,-r
':V;)
,)J
J:
'.J
- .
.-j
L
L
Reserved
L
H
H
H
H
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