Sharp PC-7200 Service Manual page 57

CE -
CHIP ENABLE, INPUT
-
P C-72DO
TI
Ie
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bus cycle
In
which the MC146818IS to be accessed. CE
IS
not
latched and must be stable during OS and AS (Motorola
case of MOTEL! and during RD and WR lin the other
MOTEL case). Bus cycles which take place without asserting
CE cau.2f: no actions to take place within the MC14681a
When CE
IS
high, the multiplexed bus output
IS In
a high-
Impedance state
When
CE
is high, all address, data, OS, and
R/W
Inputs
from the processor are disconnected within the MC146818.
This permits the MC146818 to be Isolated from a powered-
down processor. When
EE
is held high, an unpowered
device cannot receive power through the input pins from the
real-time clock power source, Battery power consumption
can thus be reduced by using a pullup resistor or active
clamp on CE when the main power is off. When CE is not us-
ed, it should be grounded.
IRQ - INTERRUPT REQUEST, OUTPUT
The IRO pin is an active low output of the MCl46818 that
may be used as an interrupt input to a processor.. The lAO
output remains low as long as the status bit causing the in-
terrupt is present and the corresponding interrupt-enable bit
is set. To clear the IRO pin, the processor program normally
reads Register C. The RESET pin also clears pending inter-
rupts.
When no interrupt conditions are present, the IRO level is
in the high-impedance state. Multiple interrupting devices
may thus be connected to an IRO bus with one pull up at the
processor.
RESET - RESET, INPUT
The RESET pin does not affect the clock, calendar, or
RAM functions. On powerup, the RESET pin must be held
low for the specified time, tRLH, in order to allow the power
supply to stabilize. Figure 13 shows a typical representation
of the RESET pin circuit.
When RESET is low the following occurs:
al Periodic Interrupt Enable (P!EI bit is cleared to zero,
bl Alarm Interrupt Enable (AlE) bit is cleared to zero,
c) Update ended Interrupt Enable (UIE) bit is cleared to
zero,
d) Update ended Interrupt Flag (UFI bit is cleared to zero,
el Interrupt Request status Flag (lROFI bit is cleared to
zero,
f)
Periodic Interrupt Flag (PF) bit is cleared to zero,
g) The part is not accessible.
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