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P C-7200
2-2-13. Timer and Speaker Driver Circuit (Figure
2-2-14. Real Time Clock and C-MOS RAM Circuit
___
2-27)
(Figure 2-28)
Figure
2-2"7~sh~o~w;;;s"'th;;:e:-t;Cim=er;-;;an;;:d;n;b:;-;u"'zz;;;e'ro"nvcce'"rccc"I"rc"'u"II-,
"' 1
h"l~s~c"',,"'c"'ulwl ------r:JrnLm'tVlloes
U Ie F\Te"'( 1"4'581"8, ael as a leal:ttime-clock;-truil"t itit-ll ...
as.._---
has the following functional features:
a 64-byte RAM backed up by the battery. The CPU can access the
*
Generates an interruption signal when the
predetermin~
timer
becomes active.
Determines the frequency of a signal to be sent to the buzzer.
(Counter 2)
These operations are based on 1.19 MHz of clock signal which is
obtained by dividing 14.31818 MHz signal into 12 at SC4752. The
PIT has three 16-bit counters. The QUTo signal sends an interruption
request toi the CPU via PIC when the predetermined timer counting
has been completed. The QUT1 terminal is not used by the system.
The QUT2 signal and audio frequency signal to the speaker
according toi the requirements of the software. This signal is
NANDed with the signal sent from the PORTS, and then drives
transistor Q2 to sound the buzzer.
Command signals related to the speaker are output by writing data
to the latch assigned at the lID address 61 H, called PORTS.
Similarly, these states can be read from the buffer assigned at the
110 address 61 H. Table 2-14 lists data loading and reading for each
counter.
Table 2-14. Counter assignments
I/O
A1
AO
RD-
WR-O
Address
0040
L
L
L
H
Read counter No.O
0040
L
L
H
L
Load counter No.O
0041
L
H
L
H
Read counter No.1
0041
L
H
H
L
LOad counter No.1
0042
H
L
L
H
Read counter No.2
0042
H
L
H
L
Load counter No.2
0043
H
H
L
H
No-operation (3-state)
0043
H
H
H
L
Write control word
---1
14.31818
I
MHzOSC
SC4752
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----r-
MSPO
(from INTERNAL MODEM)
Figure 2-27. Timer & speaker driver circuit
-
5 1:475'
F.om
IIOOROSS
~,~
2-19
RTC only when the POWER GOOD signal sent from the power
supply unit is HIGH, Normally, a HIGH level POWER GOOD signal
means that the system unit is turned on.
When the CPU writes/reads data to/from the ATC, it first assigns
an internal address of the RTC to be written/read data at the 110
address 70H, then transfers data via the lID address 71 H. When
the CPU sends a write command to the liD address 70H, a short
HIGH Jevel pulse is sent to the AS (Address Strobe) terminals of
the RTC. The AS terminal is used to latch contents of ADo-AD7
into the address latch of the RTC.
Then the CPU sends a read/write command to the I/O address 71 H,
the HIGH/LOW level R/W signal according to the read/write
command and LOW/HIGH level DS signal are output from the
address decoding circuit, in the SC4752. At this time, the RTC puts
the data of its RAM addressed by the
110 address 70H tolfrom the
data bus.
)
A~e";Og
C-MOS RAM
Accessing RTe
Figure 2-28. Timing chart of ATC & C-MOS RAM access
"\"
m.
SC4'"
.:.
~
~"
•
~,.
~
Figure 2·29, RTC & C-MOS RAM circuit
Fourteen bytes of the 64-byte RAM in the RTC are used for real-time
clock function. Figure 2-9 shows the RTC circuit, and Table 2-15
shows the memory map of the RTC.
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