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-,
---=PGR'720l)F"·--------------------------------~
SIGNAL DESCRIPTIONS
IIQq"j'.;D7
-
MULTIPLEXED
BIDIRECTIONAL AD-
DRESS/DATA BUS
.:T_tl~ _~19~'::.~~J~.@,m inFi~~r~.-.-1,::§.hQ~S.JtteLPJa..-C09J1_eC~iQn
_
. _ ;;.... _ _ .. __ Multiplexed ,.bus ...
proce~sors
save pins by presenting the
wIth
the:n~Jor mt=r:n~l,f~,~~t.lq~: 9~
the
MC1~18 ~e~I-Tlme ~
____
L _____
~C!~r~_s.~rduring
the first portion of the bus cycle and using
croc_~
j
ptus
-AAM.--.!T~e
-foll0'j"1r.I1::!
paragraph~ des~nbe--the-
1
the
sam~ins
during
the
~second
portion
for data. Address-
functIon of
each
pln"':'-=- ~~=
:
I
I
!
Ij'"
.
.
!
.
I
then-da~a
multiplexing do;es not slow the access
time
of the
Voo. VSS
F-'~=r==1,
.=~,~-~«~"~~
'~-(~1
i
=~ ~MCl1681g sinc.e"tbR,b,us ~eve(saUwm"B_~dress to data is ac-
DC
poweflS
.IJ~O~id~,d
to
th~-p~rt
ani
t~~se
tWo(pi'ns,
Vbo
-~---'
j _,
curri~goduhn~g
the
int~rna! RAiyta~q~~s ~jr'ne:-·
' ),-,,-,
being the more PQsitive' voltage. ---The! n'iini'(nu'm' and}maxi.
_
-n
j
>-
l!h~ addr~ss mast
qe
valicf'justi_pr,iQr; tal the~ [all
o-f.,A-SI
ALE
mum voltages
i
arel=listed-ih-J the
' I i
Erectrjcal=~h~r~cteristics~" _~=_,-.~t
(
LF"~-at~w~iCh t(m~tAe=M-gl46818~latGheS=tRs
address' from ADO
bJ
1
j
i -\
i i ' ; "
I
I
I i :
1
\
ta es.
'
j ,
j
"J'
•
1
I i i
"
j
I i i to AD5-:-Valid:wfit,e data must be presented and held stable
OSC1,
OSC21
TJM~.JA~~, IN-~U'TS,1--.L! ~,,-~~~-<
- -
.-.~
_ _ ,
---~~-~:::} :~diI-[mg:~tb£~i~ltte~ ~ortion
of the OS
~~
WR
p~lses.
In a read
I
.I
i '.'
i , ' ,
, I '
~I
'f
cycle, the MC ,
1 4t)?18
outputs eight bits of data during the
The time
ba~e
fqrth-e-time-func,tiar1s_--may
~-e-~arr-e!x\E'ifriar:'.
-~,-- ~''-''-'
' , --
!
,
I
I
-
signal or the 9rySt,'al oscillator.' External' SqJuar,'e, ' " ,
¥f~"v,J~s
I
'at
I
J,t",
J;~.n~f, pprtio~
9f
}hj3 OS or .RO pulses, th.en
~eases
driving the
o.on'M
",
,
ousJreturns:tHe'DlJtput drivers to the high-Impedance state)
4.1~
Hz.!1.048576MHz.or32.768k,H~,.T_~y;~~con.,
" 1 "
F '
I '
_
nected to OSC1 aso_shown.jr.LEjgu[e~JO.,Ihejriternak.tjme_.
." __ "_.,~>_~_whe~ q>S falils \,i~,tte Motorola case of MOTEL or
RD
rises in
base frequencyjto be used is ,chosen in Register
A.
the o,tHer
ca~e:
i
The on·chip
~osci~aror~~~?~~lgn-e~
for a
p~raHel
resopant
!
!
i
2
r""'·~~I~.:;"~:::"-l
,:]0
<~'~~i
,.:;,.",>
i-~?--';
:
AS T
!MUILTIR~EXED,
fDDRESS
STRO~E,INP,UT,
AT
cut crystal
~t 4Ll~iYJH~OJjl.D4t3576.Jy1.J:iz=keJl_l.Jen-
A
posltivErgo,.fn-g~multiplexed
addressstfob-e-puise serves
cres. The crystal connection$ are shown in Figure 11 and the
crystal
charact~ristics
in Fig;ure 1 2 . :
1-
to--de:m!bJltiplex"tnef5us. The falling edge of AS or ALE causes
,
!
··tfre---B'ddreS's:·~'ra--be·
latched within th'ir"·MC14681,8. The
CKOUT"-ClOCK OUT, OUTPUT
,
"
I
,
!
'
i
Th_e'~e,Kp!LI
pin,jsLanoutiftif-at"ihe
-tfnie-oase--frequency
divided -by
1
or
4' - --4
major use for' CI(:OtlT-
is"' a s
the inp).J1J
clock t6 the--misroprocessor;
thereby'sa~in'g
the cost of a
se~
cond crystal. The
freql:JencY'"'oHSK0Uf~depends·upon-'the
-
time-base frequency and the sta.te oflh_e .CKFS pin as shown
in Table 2.
,-, . -'--
""->.
,-
~-- ~~~-
.
~
CKFS - CLOCK OUT FREQUENCY'SELECT, INPUT
I
•
I
When the CKFS
pin'is~tied~to=-VEl6"il.
causes.G:KOU1--to,be
the same frequency as the time base at the OSCl pin. When
CKFS is tied to
Vss:~CKOOT-nnhe~OSCl
'time-base
fre-
quency divided by lour. Table-Z-Sul'hri'l3T1Tes' the effect 'Of
CKFS.
Table 2. Clock output frequencies
Time Base
;_
t:lop.k
~e~C!.~~~cl.~ O~ ~!oo<;k._E.~~q~~ncy
IOSC1J
.
Select Pin
Output Pin
Frequency
(CKFSI
ICKOUTI
4.194304 MHz
High
~.194304
MHz
4.194304
MHz
Low
1..048576 MHz
1.048576 MHz
High
1.'048576_
MHz
1.048576 MHz
Low
2,62!~~
kHz
32.768 kHz
High
32':768 kHz
32.768 kHz
Low
8.192 kHz
SQW - SQUARE WAVE, OUTPUT
The SOW pin can output a signal from
ci~r;ie:
df
the
15
taps
provided by the 22 internal-divider
stages-."~The
frequency-of
the SOW may be altered by programming,
R~gister
A, as
shown in Table 5. The SOW signal ~,y:·~e,t~rn~d on and off
using the SOWE bit in Register B. \ ' - \\_'
I
;
,
.
aufom~tic
-MOTEL
circuit in the MCl46818 also latches the
state oi the DS pin with the falling edge of AS or ALE.
_______ ..J,_
;_'~_o~~~~~'_~'
~'~'I
-OS'-- ,OATASTROBE:OR READ, INPJT
The
bs
pin
has~two i~terpretations
via·the MOTEL circuit.
W·hen-·emanating
:fro~
:a Motorola type
:p·rocesso'r~
OS is a
positive pylse
d~ring"fh~
latter portion of the bus cycle, and
is variously calleld,DS. (data strobel, E (enablel, and ",2 (",2
~I<?c~).
Du/in,g.
~e~d
cytles, OS
signifie~
the time that the
ATC is to 9rive th~ bidirectional bus. In w:rite.Gycles".-the trail·
ing edge of DS'
cause~
the ReaJ- Time tlock pJus RAM to
-l8iCh-ttievi"itte~
data.
I I ., ..
The second
~d)TEL
;interpretation of:'-OSis, 'that 'of Ro,
MEMR, oti7o"R
~manating
from the comJpethor type pro-
cessor. In this
c~s,e,
oS--identifies"the-tirhe period when the
reaHime clock plu:s AAM drives the bus with read data. This
interpretation
o~
QS is also the same as an output-enable
signC!1
or:UU'i~igali
memory.
The MOTEL circuit, within the MCl4681S, latches the
state of the DS pin on the falling edge of AS/ ALE. When the
Motorola mode of MOTEL is desired OS must be low during
ASlAI::E1,l;which is the case with the Motorola multiplexed
bus processors. To ensure the competitor mode of MOTEL,
the D;S
,pin
must. remain high during the time
ASI
ALE is
_high._c
RiW -
REAo/WRITE,'INPUT
-
'~1h~'_MOJEL circuit.t~~~~t~-the
A/W pin in one of two ways,
When.i3 Motorola-type--pmcessor is connected, R/W is a
leve'l wrich indicates
w~etfier
the current cycle is a read or
write.
-A_i
read cycle is indicated with a high level on
R/V\!
. while-;1?S' is-high, whereas a -wr·ite,cycle is a Iowan A/W dur.
ing D.S\.).. _,_"-__ _
iThe
s~cond
interpretation of
R/W
is as a negative write
pulse,
W8~-,.MEMW,
and
I/OW from competitor type pro-
cessor~. ~~~ ,fV!.Oy~,C-cir;<t·~H
in .this mode gives R/W pin the
sama _meaning as/tKe/write
IWl
pulse on many generic
RAMs.,.
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