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2-2-7-2. RAM addressing (Figures 2-12 and 2-13)
Two chips of 256K-bit (32xB-bit) ROMs are mounted on the main
- -boardas a ·8TOBtmM.
- - - - -
Fig.2-12 below shows the block diagram and Fig.2-13 the timing
chart.
S~'.'5::===========~~~'·'5=:j.
oo,W·"oo"., _ _ --'\
.,~
7
XDo·,5
H'OA _ _
~
SO,S!
MilO
SC"5'
1l0lMCS
Figure 2-12
Ao,~l
:=:::X=============::JxC======
ROMes _ _ _ _
J-------------, __ _
•
- -
,:=
:=
-
V
!iii
~
~
I
1Jl1'2
I
OLYl
~
L -
AA.
~,
. .
"
SC41~t
"~,
~
""
CASH
L;--,
-
P C-7200
"' "
"~
,-----< ""
OO,.,ODIHI7FFFEH
~---aT~
""
""
OODOO1H.cl7FFFH
'"
STANCI.RDIODD)
'"
"
tJBOOOO1H'IIFFFEH
..
"
STANDARD (EVEN)
:::fJ,----
I=:rJ,-
"~
~
IlIiOQQOH.oIIFFfEH
f--n,-
'"
1-<'"
STAND~AD(ODIll
~
"~
"~
HIOOOOH·I7fFFEll
""
'"
OPTION (EVEN)
"~
'"
HIOOIl1H·17FFHH
"'
'"
OI'TKlNIDODI
'"
ox
ISODOH·'FFFFEH
'"
'"
"O!'TION(EVENI
"~
"'"
,~
"
I8ODOH·'FFFFEH
~--------L_
________ - ' - - - -
'00"' _ _ _ _ _ _ _ _ _
---<=====::>--___ _
Figure 2-13. Timing chart of ROM addressing
2-2-7-3. RAM addressing
As a standard configuration, 20 chips of DRAMs (16 chips of
256K-bitX1 DRAMs and 4 chips of 64K-bitx4 DRAMs) are mounted
on the main board, and, it is possible as an option to implement 8
chips of 1 M·bit DRAMs (256K-bitx4 DRAMs).
Fig.2-14 below shows the block diagram and Fig.2-15 the timing
chart.
The RAM areas are divided into eight groups.
CD
OOQOOOH through 07FFFEH having even addresses
®
000001 H through 07FFFFH having odd addresses
®
OeOODOH through 09FFFEH having even addresses
@
080001 H through 09FFFFH having odd addresses
®
10DaOOH through 17FFFEH having even addresses
®
100001H through 17FFFFH having odd addressses
o
180000H through 1 FFFFEH having even addresses
®
180001 H through 1 FFFFFH having odd addresses
CD
to
@
are the standard configuration RAM area and
®
to
®
are
option RAM area. Each group is selected by CASL, CASH, RASa,
RAS1, RAS2, and RAS3 sent from the SC4751.
. •
2-13
..
,---<"
'OPT~N(OOO)
---\
1
-I
•••
,~
I>
Figure 2-14. RAM addressing
~.
~~==============~x~=======
________ ,--,L ____________________ __
-=~~~
I
,oonS
R,OJ,IfL',S
I
r-
7OnS--j
r-~--I
=====X
ROW
X
CATAOIJT
_ _ _ _ _ _ _ _ _ _ _ _ _
--(=:::;""~~"""~;;;:"=:::>_---
DATAIN
WI1ITEOATA
>---
Figure 2-15. Timing chart of RAM addressing
2-2-7-4. D-RAM Refreshment (Figures 2-16 and
2-17)
Refreshment for D-RAM chips is performed by the refresh address
counter and the hold control logic inside the GA1. D-RAM
refreshment starts on a clock signal sent every 15 microseconds
from the OUT1 terminal of the PIT. After the OUT1 terminal becomes
HIGH, the GA1 sends the CPUHRQ signal to the CPU at the second
falling edge of the DMACLK signal.
When the CPU receives the CPUHRQ (D-RAM refresh request)
signal, it returns the CPUHLDA signal to the GA 1 at the next CPU
cycle, and then repeats the hold cycle. At this time, the REFRESH
signal become LOW, and the GA 1 makes the simulative memory
read signal MEMR LOW for refreshment. Then the GA1 outputs a
refresh address to the SAO through SA7 address bus, after it counts
up the refresh address counter inside it. Therefore, it requires 256
x 0.015
=
3.84 milliseconds to count up 256 row addresses
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