Sharp PC-7200 Service Manual page 33

2-3. KEYBOARD UNIT
--.ntroduCtion
The keyboard is separated from the main unit and is attached
modular plug connector on the right side of the main unit.
keyboard cable can be disconnected from both the keyboard
the main unit. The curled, shielded keyboard cable is approxim
0.9" long (260mm).
by a
The
and
alely
nsist
The interface lines between the keyboard and the system unit co
of a power supply (+5V DC), GND, and two bidirectional signal lin
The keyboard contains its own microprocessor to implemen
es.
t all
functions normally required of a keyboard.
Key Controller
The keyboard employs an 80C49 (8
M
bit one-chip microproces sor)
and a 2464 (64K-byte one time PROM).
r.
The 80C49 has 238-byte RAM which is used as the key buffe
The 2464 contais the control program including self-diagnostics.
The keyboard is connected to the keyboard interface on the main
PCB with the
two
signal lines, KBDDATA and KBDCLK. Using these
lines, a bi-directional data transfer is performed.
With various commands from the keyboard interface, the keyboard
mainly performs the following operations:
0;
Resets the keyboard itself.
0;
Re-outputs the key scan codes.
0;
Varies the detection period for the key auto-repeat function.
*
Turns the LEOs on the keyboard on or off.
Conversely, the keyboard performs the following for the system unit:
* Requests that a command be reset.
* Telis the result of the self-diagnostic at power on or at reset.
* Denoted that the
16~byte
keyboard buffer is full.
Signals P10 through P13 in the figure are used as key scan signals,
and DBO through DB? are used as key return signals. The interface
between the main PCB and tlie keyboard is performed by P2?, P26,
TO and INT terminals.1 P2? transmits a key clock signal; P26 also
transmits key data. The keyboard CPU checks the TO and tNT
terminals to judge whether the keyboard interface on the main PCB
is ready to receive data.
When the keyboard CPU is ready to send key data, it first checks
these line. If the KBDCLD line is LOW, the key data is stored in the
RAM of the keyboard CPU. If the KBDCLK line is HIGH and
KBDDATA line is LOW, the key data is stored in the RAM of the
keyboard CPU and the keyboard CPU receives data from the 8042.
The keyboard CPU sends the key scan signals to the key matrix
and judges conditions for each key by reading the key return signals.
When one of the keys is pressed, the keyboard CPU emits a key
code signal corresponding to that key, and sends it to the 8042
together with a key clock signal sequentially. At this time, the
keyboard CPU sends a start bit, an
8~bit
key code, and odd parity
bit, and a stop bit.
If the parity bit sent from the keyboard CPU does not match with
the one in the keyboard interface, the 8042 sends a resend command
"FE" to the keyboard.(Ref. CHAPTER t for keylayout.)
2-27
A10 -
~
.
-
~~·O
...-
..
0, _ Po
~-~
[111.-_
~
-
P C-7200
--
,,[--J
:~
·~w
,,-.~
"'~
~
D=
~.
x;; _
xo
~I~,.
p" - p ..
~
I-E~'"
LEO'
, ,
r-
co.
,,,
co"
~
,,,
Figure 2-45. Block diagram of keyboard
..
----~u.---'u.---------~~
u
u---
TIMING CHART OF KEY STROBE
8742 - _ KEYllOARO
87~2
_ _ KEY60ARO
~
IUIt>DATA
tto-b7 OATA bll
(pooIl"')
P , p_ttty bH (odd)
Figure 2-46. Timing chart of data transmission