Sony HCD-V909AV Service Manual page 51

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Pin No. Pin Name
35 TD9
36 TD8
37 XTEST1
38 XTEST2
39 XTEST3
40 V
SS
41 TRST
42 V
DD
43 TDI
44 TMS
45 TCK
46 TDO
47 V
SS
48 SI
TE
L 13942296513
49 SCK
50 XCS
51 XVRST
52 F1
53 V
DD
54 XTEST4
55 XRST
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56 SYSCLK
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I/O
O
Test data bus.
In the test mode, used for internal circuit test data bus.
O
The test mode is allowed to use only for device vendors (Not used)
I
Test mode control input pin. Pulled-up.
I
When these pins are "H", CXD1913Q is not in the test mode.
I The test mode is allowed to use only for device vendors
–
Digital ground
Test mode reset input pin.
I
During power on/reset, set to "L" for more than 40 clocks (SYSCLK) (Not used)
–
Digital power supply
I
Test mode control input pin. (Not used)
I
I
Test mode control input pin. Fix at "H"
O Test data bus pin. (Not used)
– Digital ground
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is "H", sets into the SONY SIO mode, and becomes the SI serial
I
data input pin.
When the XIICEN pin is "L", sets into the I
output pin
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is "H", sets into the SONY SIO mode, and becomes the SCK serial
I
clock input pin.
When the XIICEN pin is "L", sets into the I
The functions of this pin are selected by Pin 64 XIICEN. Pulled-up.
When the XIICEN pin is "H", sets into the SONY SIO mode, and becomes the XCK chip
I
select input pin.
When the XIICEN pin is "L", sets into the I
address selection input signal which selects the I
Active "L" vertical sync reset input pin. Pulled-up.
I Used for synchronizing external vertical sync and internal vertical sync.
When XVRST is "L", the internal digital sync generator is reset according to the F1 state
Field ID input pin.
When externally synchronizing with the XVRST signal, the field to be reset is determined
I by this signal.
"H" indicates the first field.
"L" indicates the second field
– Digital power supply
Test mode control input pin. Pulled-up.
I When these pins are "H", CXD1913Q is not s test mode.
The test mode is allowed to use only for device vendors
System reset input pin when active "L".
I
During power on/reset, set to "L" for more than 40 clocks (SYSCLK)
System clock input pin.
I
To generate the correct sub carrier frequency, precisely 27MHz is required
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2 9
8
Function
Q Q
3 6 7 1 3 1 5
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— 89 —
9 4 2 8
2
C-BUS mode, and becomes the SDA input/
0 5 8 2 9 9 4 2 8
2
C-BUS mode, and becomes the SCL input pin
2
C-BUS mode, and becomes the SA slave
2
C-BUS slave address
m
9 9
9 9