Sony HCD-V909AV Service Manual page 44

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• IC201 MPEG DECODER (CXD1852AQ)/VIDEO board
Pin No. Pin Name
1 V
SS
2 XTL0O
3 XTL0I
4 V
DD
5 HA2
6 HA3
7 HD0
8 HD1
9 HD2
10 HD3
11 HD4
12 HD5
13 HD6
14 V
DD
15 V
SS
16 HD7
17 MA3
18 MA4
19 MA2
20 MA5
TE
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21 MA1
22 V
SS
23 MA6
24 MA0
25 BC
26 TCKI
27 TDI
28 TENAI
29 TDO
30 VST
31 V
SS
32 MA7
33 MA8
34 XRAS
35 XMWE
XCAS2
36
/MA9
37 XCAS0
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38 MD7
39 MD8
40 MD6
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I/O
– Ground
Video decoder master clock pin. Input the XTL0I clock or connect an oscillator between
O
XTL0I and XTL0O. The recommended frequencies are 27MHz, 28.6363MHz (NTSC
I 8fsc), and 35.4686 MHz (PAL 8fsc).
– +5V power supply
Address input pin. In some cases, serves as the control signal and data input according to
I
I the setting of the control mode.
I/O
I/O
I/O
I/O Data input/output
I/O
I/O
I/O
– +5V power supply
– Ground
I/O Data input/output
O
O
O Address signal pin. Connect to the DRAM address pin with the same number.
O
O
– Ground
O
Address signal pin. Connect to the DRAM address pin with the same number.
O
I
I
I For test (Not used)
I
I
I For test (Connect to ground)
– Ground
O
Address signal pin. Connect to the DRAM address pin with the same number.
O
RAS signal pin. Connect to the RAS pin of the DRAM. Same for the 256Kw × 16b,
O
256Kw × 16b × 2, and 512Kw × 8b × 2 DRAM structures.
O WE signal pin. Connect to the WE pin of the DRAM.
CAS signal. Connect to the CAS pin of the DRAM so as to control the lower bytes of the
upper word (256K to 512K-1) for the 256Kw × 16b × 2 DRAM structure. / Address signal
O
pin. Connect to the DRAM address pin with the same number. (Not used)
CAS signal. Connect to the CAS pin of the DRAM so as to control the lower bytes (MD0
to MD7) for 256Kw × 16b and 512Kw × 8b × 2 DRAM structures, and to control the
O
lower bytes of the lower word (0 to 256K-1) for the 256Kw × 16b × 2 DRAM structure.
I/O
Data input/output signal pin. Connect to the DRAM data pin so that the lower and upper
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I/O
bytes of the data correspond to the CAS0 to CAS3 controls.
I/O
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