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A.3 Advanced Chipset Features
Since the features in this section are related to the chipset on the
CPU board and are completely optimized, you are not recommended
to change the default settings in this setup table unless you are well
oriented with the chipset features.
CMOS Setup Utility-Copyright © 1984-2001 Aw ard Softw are
Ad vanced Chipset Featu res
DRAM Timing
CA Ss Latency Ti me
Acti ve to Re charge De lay
D RAM RA S # to CA S# De l a y
DRAM RAS# Re charge
D RAM Data In te g r ity Mo de
MGM Co re Fr eq uency
System B IOS C acheable
Video
BIOS Ca cheable
Memory Ho le At 15 M-16M
Delayed Transacti on
Delay Prior to Thermal
AGP Aperture S i ze (M B)
In it Di splay Fi rst
** On-Chip VGA Se tting **
On-Chip VG A
On-Chip Frame Bu ffe r Size
Boot Displ ay
l Scaling
Panel Number
ÇÈ ÆÅ : Mo ve
E n te r: S e le ct
F 5 : P r evious Values F6: Fail- Saf e D e f a ults F7: O p timize d D e f a ults
SDRAM CAS latency Time
You can select CAS latency time in HCLKs 2, 3, or Auto. The board
designer should set the values in this field, depending on the DRAM
installed. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU.
DRAM Data Integrity Mode
This option sets the data integrity mode of the DRAM installed in the
system. The default setting is "Non-ECC".
SBC83810 BIOS Setup
PC 6170 User's Manual
By SPD
2.5
7
3
3
No n -E CC
Au to Max 400/333MHz
Enable
Di sabled
Di sabled
Di sabled
16 Min
64
Onboard
Enabled
32 MB
Au to Pane
Au to
640 x480
+/- / P U /P D : Va lu e
F 1 0 : S a ve
Gene ral He lp
Ite m He lp
Menu Level f
E S C : E xi t F 1 :
45
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