Sony SRX-R320 Service Manual page 307

PR_RX
BANK1
100 R353
7
CL351 NM
005 CLK_77M_IC2 CLK0/LVDSCLK1p[G1] IO4/PLL1_OUTp[J1]
0.8
8
CL352
CLK1/LVDSCLK1n[H1] IO42/PLL1_OUTn[K2]
0.8
R351
1k
R354 47 113
ref_clk_77M_IC2_IC33
018 IO84/LVDS14n[C3] IO5/LVDS6p[K1]
GND
2
002 AUX_IC1_IC2_0 IO0/LVDS13n[B1] IO6/LVDS6n[L1]
195
IO157/VREF0B1[G5] IO43/LVDS5p[L2]
R409 22
159
016 AUX_IC2_IC31_2 IO126[F4] IO7/LVDS5n[M1]
R355 22 114
018 AUX_IC2_IC33_1 IO85/LVDS12p/DQ0L0[D3] IO8/LVDS4p[N1]
CL356 0.8 158
002 AUX_IC1_IC2_io IO125/LVDS12n/DQ0L1[E4] IO44/LVDS4n[M2]
R412 22
194
CL357 0.8 IO156/DPCLK1/DQS0L[F5] IO45/LVDS3p/DQ0L4[N2]
R407 22
115
018 AUX_IC2_IC33_2 IO86/LVDS11p/DQ0L2[E3] IO91/LVDS3n/DQ0L5[M3]
R356 47 63
016 ref_clk_77M_IC2_IC31 IO38/LVDS11n/DQ0L3[D2] IO160/DPCLK0[L5]
R357 47 64
017 ref_clk_77M_IC2_IC32 IO39/LVDS10p[E2] IO129/LVDS2p/DQ0L6[M4]
R358 22
4
016 AUX_IC2_IC31_1 IO1/LVDS10n[D1] IO92/LVDS2n/DQ0L7[N3]
R408 22
116
017 AUX_IC2_IC32_2 IO87/LVDS9p[F3] IO159/VREF2B1[K5]
117
IO88/LVDS9n[G3]
R359 22 65
002 AUX_IC2_IC1_0 IO40/LVDS8p[F2] IO9/LVDS1p[R1]
R360 22
5
017 AUX_IC2_IC32_1 IO2/LVDS8n[E1] IO46/LVDS1n[P2]
R361
0 66
001,002 SDA2-PR_RX IO41/LVDS7p[G2] IO93/LVDS0p[P3]
6
001,002 SCL2-PR_RX IO3/LVDS7n/DM0L[F1] IO130/LVDS0n[N4]
196
R362
0 IO158/VREF1B1[H5]
IC2 (1/5)
FPGA LVDS RX
EP1C6F256C6N(300)
+3.3V
IC2
R352
10k
S351
1 2
FG1
C386
3 4
0.1uF
GND
BANK3
39
R363 100
001 QDI_DCLK- CLK3/LVDSCLK2n[H16] IO171/VREF1B3[H12]
40
001 QDI_DCLK+ CLK2/LVDSCLK2p[G16] IO109/LVDS43n/DM1R[G14]
IO143/LVDS43p[G13]
R364 100 175
001 QDI_D15- IO139/LVDS51n[N13] IO66/LVDS42n[G15]
135
001 QDI_D15+ IO104/LVDS51p[P14] IO24/LVDS42p[F16]
88
R365 100
001 QDI_D14- IO61/LVDS50n[P15] IO110/LVDS41n[F14]
32
001 QDI_D14+ IO18/LVDS50p[R16] IO144/LVDS41p[F13]
R366 100 89
001 QDI_D12- IO62/LVDS49n/DQ1R7[N15] IO67/LVDS40n[F15]
34
001 QDI_D12+ IO19/LVDS49p[N16] IO25/LVDS40p[E16]
209
IO170/VREF2B3[K12] IO68/LVDS39n[E15]
139
IO108/DQ1R6[K14] IO26/LVDS39p[D16]
208
IO169/DPCLK5/DQS1R[L12] IO69/LVDS38n[D15]
136
R367 100
001 QDI_D13- IO105/LVDS48n/DQ1R5[N14] IO111/LVDS38p/DQ1R3[E14]
176
001 QDI_D13+ IO140/LVDS48p/DQ1R4[M13] IO173/DPCLK4[F12]
137
IO106/LVDS47n[M14] IO145/LVDS37n/DQ1R2[E13]
177
IO141/LVDS47p[L13] IO112/LVDS37p/DQ1R1[D14]
90
R368 100
001 QDI_D10- IO63/LVDS46n[M15] IO142/DQ1R0[H13]
35
001 QDI_D10+ IO20/LVDS46p[M16] IO172/VREF0B3[G12]
R369 100 138
001 QDI_D11- IO107/LVDS45n[L14] IO27/LVDS36n[B16]
91
001 QDI_D11+ IO64/LVDS45p[L15] IO70/LVDS36p[C15]
36
R370 100
001 QDI_D8- IO21/LVDS44n[L16] IO113/LVDS35n[C14]
37
001 QDI_D8+ IO22/LVDS44p[K16] IO146/LVDS35p[D13]
92
0.8
IO65/PLL2_OUTn[K15]
CL353
38
0.8
IO23/PLL2_OUTp[J16]
CL354
LVDS IN
77Mx4 308MHz
IC2 (3/5)
FPGA LVDS RX
EP1C6F256C6N(300)
SRX-R320
A B
DFD_IN_DWN_EV_RED
011 DFD_IN_DWN_EV_RED
DATA OUT
DFD_IN_DWN_EV_GRN
011 DFD_IN_DWN_EV_GRN
RATE:77MHz
DFD_IN_DWN_EV_BLU
011 DFD_IN_DWN_EV_BLU
TP355
DFD IN
DWN VD
TP354 001,002 NC_CN1_3
TP351
001,002 NC_CN1_2
DFD IN
DWN HD
9
CL360 TP352
0.8
69
CL361
0.8
121
IO90[L3]
10 22 R371
011,013
VDQDI_DWN
11 22 R372
HDQDI_DWN 011,013
70
RST_DFD_DWN_EV_UP 012
12
RST_DFD_DWN_EV_LW 012
13
RST_DFD_DWN_OD_UP 014
71
RST_DFD_DWN_OD_LW 014
72
122
199
CL362
0.8
165
+3.3V
123 2 1
198 4 3
164
6 5
IO128[L4]
15
LED_IC2_0 8 7
73 LED_IC2_1
RB351
124 10k
LED_IC2_3
S352
166
LED_IC2_2
+3.3V IC2
GND
R392 R394 R396
NM
NM 10k
IC2
R398 CL-196YG-CD-T
D351
1k
LED_IC2_0
0
R399 CL-196YG-CD-T
1k D352
LED_IC2_1
1
R393 R395 R397
NM R400 CL-196YG-CD-T
10k 10k
D353
1k
LED_IC2_2
2
CL-196YG-CD-T
SLAVE 0x62 R401
1k D354
LED_IC2_3
GND 3
DFD_IN_DWN_OD_RED
013 DFD_IN_DWN_OD_RED
DATA OUT
DFD_IN_DWN_OD_GRN
013 DFD_IN_DWN_OD_GRN
RATE:77MHz
DFD_IN_DWN_OD_BLU
013 DFD_IN_DWN_OD_BLU
211
142
R373 100
QDI_D9- 001
181
QDI_D9+ 001
95 R374 100
QDI_D6-
001
41
QDI_D6+ 001
143
R375 100
QDI_D7- 001
DFD IN
182
DWN CLK-O
QDI_D7+ 001
96 R376 100
TP353
QDI_D4- 001
42
QDI_D4+ 001 CLK OUT 77MHz
97
R377 100
QDI_D2- 001
43
013 CLKQDI_DWN_OD
QDI_D2+ 001
98
R378 100
QDI_D3- 001
144
QDI_D3+ 001
213
183 R379 100
QDI_D5- 001
145
QDI_D5+ 001
180
212
45 R380 100
QDI_D0- 001
99
QDI_D0+ 001
146
R391 100
QDI_D1- 001
184
QDI_D1+ 001
LVDS IN
77Mx4 308MHz
C
PR-300 (3/20) PR-300 (3/20)
SUFFIX: -11 SUFFIX: -11
RB352
RB355
22
%EGRN[4] 1 2 %EGRN[4] 22
%EBLU[2] 1 2 %EBLU[2]
%EGRN[2] 3 4 %EGRN[2]
%EBLU[0]
3 4 %EBLU[0]
%EGRN[0] 5 6 %EGRN[0]
%EGRN[8]
%EGRN[8] 5 6
%ERED[8] 7 8
%ERED[8]
%EGRN[6] 7 8 %EGRN[6]
1 2
1 2
%ERED[5] %ERED[5] RB359
RB353 3 4
22
%ERED[7] 3 4 %ERED[7]
%ERED[1] 5 6 %ERED[1]
%ERED[9] 5 6 %ERED[9]
%ERED[3] 7 8
%ERED[3]
%EGRN[1] 7 8 %EGRN[1]
%ERED[6]
1 2 %ERED[6]
RB356
%ERED[4] 3 4 %ERED[4]
22
%ERED[2] 5 6 %ERED[2]
%ERED[0] 7 8
%ERED[0]
RB354
22
BANK2 BANK2
100 218
0.8
IO71/LVDS34n[B15] IO178[E8]
CL363
47 152
%EGRN[3]
0.8
IO28/LVDS34p[A15] IO119/LVDS24n[C8]
CL364
R410 NM
101 189 %EGRN[8]
IO72/LVDS33n[B14] IO151/LVDS24p[D8]
R411 CL365 0.8
NM 147 54
%EGRN[6]
IO114/LVDS33p[C13] IO32/LVDS23n[A8]
CL366 0.8
102 107
%EGRN[4]
IO73/LVDS32n/DQ0T0[B13] IO78/LVDS23p[B8]
49 190
%EGRN[1]
IO29/LVDS32p/DQ0T1[A13] IO152/LVDS22n[D7]
%EBLU[9] 103 153
IO74/LVDS31n/DQ0T2[B12] IO120/LVDS22p[C7]
148 108
%EBLU[5] %EGRN[2]
IO115/LVDS31p/DQ0T3[C12] IO79/LVDS21n[B7]
214 56
%EGRN[0]
0.8
IO174/DPCLK3/DQS0T[E12] IO33/LVDS21p[A6]
CL367
215 219
IO175/VREF0B2[E11] IO179[E7]
217 109
IO177[E9] IO80/LVDS20n[B6]
185 154
%EBLU[7] CL371
IO147/LVDS30n[D12] IO121/LVDS20p[C6]
0.8
186 191
%EBLU[3]
IO148/LVDS30p[D11] IO153/LVDS19n[D6]
149 192
%EBLU[1]
IO116/LVDS29n[C11] IO154/LVDS19p[D5]
104 220
%EBLU[8]
IO75/LVDS29p[B11] IO180/VREF2B2[E6]
51 193 R403 22
%EBLU[6]
IO30/LVDS28n[A11] IO155/DPCLK2[E5]
105 155
%EBLU[4]
IO76/LVDS28p[B10] IO122/LVDS18n/DQ0T4[C5]
150 110
0.8
IO117/LVDS27n[C10] IO81/LVDS18p/DQ0T5[B5]
CL368
187 58
%EGRN[9]
IO149/LVDS27p[D10] IO34/LVDS17n/DQ0T6[A4]
53 111
%EBLU[0]
IO31/LVDS26n[A9] IO82/LVDS17p/DQ0T7[B4]
106 156
%EBLU[2]
IO77/LVDS26p[B9] IO123/LVDS16n[C4]
188 112
%EGRN[5]
IO150/LVDS25n/DM0T[D9] IO83/LVDS16p[B3]
151
%EGRN[7]
IO118/LVDS25p[C9]
216
IO176/VREF1B2[E10]
IC2 (2/5)
FPGA LVDS RX
EP1C6F256C6N(300)
RB361 RB364
22 22
%ORED[1] 1 2 %ORED[1] %ORED[9] 1 2 %ORED[9]
%ORED[3] 3 4 %ORED[3] %OGRN[1] 3 4
%OGRN[1]
%ORED[5] %OGRN[3]
5 6 %ORED[5] 5 6 %OGRN[3]
%OGRN[5]
%ORED[7] 7 8 %ORED[7] 7 8 %OGRN[5]
%ORED[6] 1 2 %ORED[6] %OGRN[4] 1 2 %OGRN[4]
RB362
RB368
RB365
22 %ORED[4] 3 4 %ORED[4] %OGRN[2] 3 4
%OGRN[2] 22
22
%ORED[2] %OGRN[0]
5 6 %ORED[2] 5 6 %OGRN[0]
%ORED[8]
%ORED[0] 7 8 %ORED[0] 7 8 %ORED[8]
%OGRN[7] 1 2
%OGRN[7]
%OGRN[9]
3 4 %OGRN[9]
%OBLU[1]
5 6 %OBLU[1]
%OBLU[3] 7 8 %OBLU[3]
RB366
22
BANK4
74 205
%OBLU[7]
IO47/LVDS71p[R2] IO166/VREF1B4[M10]
17 81
%OBLU[9]
IO10/LVDS71n[T2] IO54/LVDS61p/DM1B[R9]
75 24
%OBLU[5]
IO48/LVDS70p[R3] IO14/LVDS61n[T9]
125 130
%OBLU[3]
IO94/LVDS70n[P4] IO99/LVDS60p[P9]
76 171
%OBLU[8]
IO49/LVDS69p[R4] IO135/LVDS60n[N9]
19 82
%OBLU[6]
IO11/LVDS69n[T4] IO55/LVDS59p[R10]
77 26
%OBLU[4]
IO50/LVDS68p/DQ1B7[R5] IO15/LVDS59n[T11]
126 172
%OBLU[1]
IO95/LVDS68n/DQ1B6[P5] IO136/LVDS58p[N10]
R402 22 200 131
IO161/DPCLK7/DQS1B[M5] IO100/LVDS58n[P10]
201 83
IO162/VREF2B4[M6] IO56/LVDS57p[R11]
167 132
NEAR IC2
IO131/LVDS67p[N5] IO101/LVDS57n[P11]
168 173
%OGRN[9]
IO132/LVDS67n/DQ1B5[N6] IO137/LVDS56p[N11]
0.8 127 174
CL369 IO96/LVDS66p/DQ1B4[P6] IO138/LVDS56n[N12]
78 204
%OBLU[2]
IO51/LVDS66n[R6] IO165[M9]
202 206
IO163[M7] IO167/VREF0B4[M11]
21 207
%OBLU[0]
IO12/LVDS65p[T6] IO168/DPCLK6[M12]
79 133
%OGRN[8]
IO52/LVDS65n[R7] IO102/LVDS55p/DQ1B3[P12]
128 84
%OGRN[7]
IO97/LVDS64p[P7] IO57/LVDS55n/DQ1B2[R12]
169 28
%OGRN[5]
IO133/LVDS64n[N7] IO16/LVDS54p/DQ1B1[T13]
80 85
%OGRN[6]
IO53/LVDS63p[R8] IO58/LVDS54n/DQ1B0[R13]
%OGRN[4] 23 86
IO13/LVDS63n[T8] IO59/LVDS53p[R14]
170 134
0.8
IO134/LVDS62p[N8] IO103/LVDS53n[P13]
CL370
129 30
%OGRN[3]
IO98/LVDS62n[P8] IO17/LVDS52p[T15]
203 87
IO164[M8] IO60/LVDS52n[R15]
IC2 (4/5)
FPGA LVDS RX
EP1C6F256C6N(300)
C-107 C-107
D E
RB358
22
%EBLU[1] 1 2 %EBLU[1]
%EBLU[3] 3 4 %EBLU[3]
%EBLU[5] 5 6 %EBLU[5]
7 8
%EBLU[7] %EBLU[7]
%EBLU[9] 1 2 %EBLU[9]
%EBLU[8] 3 4 %EBLU[8]
22
%EBLU[6] 5 6 %EBLU[6]
7 8
%EBLU[4] %EBLU[4]
%EGRN[3] 1 2 %EGRN[3]
%EGRN[5] 3 4 %EGRN[5]
%EGRN[7] 5 6 %EGRN[7]
7 8
%EGRN[9] %EGRN[9]
RB360
0.1uF
22
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
1608
0.1uF
60at100M
500mA
0.1uF
C351
3216 22uF
10V
C FB351
C352
22uF 3216 140038221
10V
C 180at100M
C388
3216 22uF
C 10V
C353
0.1uF
C354
%ERED[9]
0.1uF
C355
0.1uF
C356
0.01uF
C357
0.01uF
C358
%ERED[8] 0.1uF
DFD IN C359
0.1uF
DWN CLK-E
C360
%ERED[7]
0.1uF
TP356
C361
%ERED[3]
0.1uF
CLK OUT 77MHz C362
NEAR IC2
0.1uF
C363
0.1uF
CLKQDI_DWN_EV 011
C364
%ERED[5]
0.01uF
C365
%ERED[6]
0.01uF
C366
%ERED[4] 0.01uF
C367
%ERED[2] 0.1uF
C368
%ERED[1]
0.1uF
C369
%ERED[0]
0.1uF
C370
0.1uF
GND
002,004 TCK_PR_RX
R383
FROM IC1
002 TDO_PR_RX_IC1
R384
TO EPC4 PR_TX PROM 019 TDO_PR_RX_IC2
002,004 TMS_PR_RX
+3.3V
RB367 R385
002,004 nCONFIG_PR_RX
22
%OBLU[9] 1 2 %OBLU[9]
R382
3 4 10k
%OBLU[8] %OBLU[8] +3.3V
R386
%OBLU[6] 5 6 %OBLU[6]
001,002,004 nSTATUS_PR_RX
R387
%OBLU[4] 7 8 %OBLU[4]
DATA0_PR_RX
002,004
NM
%OBLU[5] 1 2 %OBLU[5] R388
R381
002,004 DCLK_PR_RX
GND
3 4 R389
%OBLU[7] %OBLU[7]
001,002,004 CONF_DONE_PR_RX
5 6
R406 10
7 8
002,004 INIT_DONE_PR_RX
1 2
%OBLU[2] %OBLU[2]
%OBLU[0] 3 4 %OBLU[0]
%OGRN[8] 5 6 %OGRN[8]
%OGRN[6] 7 8 %OGRN[6]
RB369 RESET 002,004 RESET_PR_RX
22
%OGRN[0]
%OGRN[2]
%OGRN[1]
CL372
0.8
%ORED[8]
%ORED[6]
%ORED[9]
%ORED[7]
%ORED[4]
CL373
0.8
%ORED[5]
%ORED[1]
CL374
SCL3-FOR_RESET_DW_EV
001
0.8
%ORED[3]
%ORED[2]
%ORED[0]
CL375
SDA3-FOR_RESET_DW_EV
001
0.8
CL376
SCL4-FOR_RESET_DW_OD 001
0.8
CL377
SDA4-FOR_RESET_DW_OD 001
0.8
CL378
R413
0.8 R414
CL379
47k 47k
0.8
R415 R416
47k 47k
GND
F G
1
+1.5V
FB353
1608
180at100M
1.5A
C371
22uF
3216
6.3V
C372
22uF
6.3V
C373 3216
C374
C375 55 1
VCCINT4[A7] GND1[A1]
C376 52 46
VCCINT3[A10] GND6[A16]
C377 252 57
VCCINT10[G8] GND8[A5]
C378 250 50
VCCINT9[G10] GND7[A12]
C379 242 221
VCCINT5[H7] GND9[F6]
C380 256 239
VCCINT12[H9] GND18[F8]
254 238
+3.3V
VCCINT11[J8] GND17[F9]
GND
248 236
VCCINT8[J10] GND16[F11]
244 241
VCCINT6[K7] GND19[G7]
FB352 246 251
1608 VCCINT7[K9] GND24[G9]
1.5A 22 235
VCCINT1[T7] GND15[G11]
25 253
VCCINT2[T10] GND25[H8] 2
249
GND23[H10]
3 243
VCCIO1_1[C1] GND20[J7]
222 255
VCCIO1_3[G6] GND26[J9]
+1.5V-PLL_PR_RX
14 225
VCCIO1_2[P1] GND10[K6]
245
GND21[K8]
48 247 1608
VCCIO2_1[A14] GND22[K10] 60at100M
FB354
237 226 500mA
VCCIO2_3[F10] GND11[L6]
240 228
VCCIO2_4[F7] GND12[L8]
59 229 C387
VCCIO2_2[A3] GND13[L9]
10uF
231
GND14[L11] 6.3V 2012
33 16
VCCIO3_1[P16] GND2[T1] C381
232 20
10uF
VCCIO3_3[K11] GND3[T5]
44 27 6.3V 2012
VCCIO3_2[C16] GND4[T12]
31
C382
GND5[T16]
1000pF
18
VCCIO4_1[T3]
227 223
VCCIO4_3[L7] VCCA_PLL1_1[H6]
230 224 C383
VCCIO4_4[L10] GNDA_PLL1_1[J6] 0.1uF
29 197
C384
VCCIO4_2[T14] GNDG_PLL1_1[J5]
1000pF
140 234
TCK_3[J14] VCCA_PLL2_3[H11]
10 141 233
C385
TDI_3[H14] GNDA_PLL2_3[J11] 0.1uF
10 94 BANK3 210
TDO_3[H15] GNDG_PLL2_3[J12]
3
93
TMS_3[J15]
GND
10k R390 119
MSEL0_1[J3]
PS 68 BANK1
MSEL1_1[J2]
10 GND 118
nCONFIG_1[H3]
161
CL388
nCEO_1[H4] BANK1
0.8
162
nCE_1[J4]
10 179
nSTATUS_3[J13] BANK3
10 67
DATA0_1[H2]
10
163 BANK1
DCLK_1[K4]
10 178
CONF_DONE_3[K13] BANK3
0.8 157
CL389
IO124/LVDS14p/INIT_DONE_1[D4]
62
CL390
IO37/LVDS13p/CLKUSR_1[C2]
0.8
160
CL391 IO127/nCSO_1[G4] BANK1
0.8
120
CL392
IO89/ASDO_1[K3]
0.8 60
CL393
IO35/LVDS15n/DEV_OE[A2]
0.8 R404 10
61 BANK2
IO36/LVDS15p/DEV_CLRn[B2]
IC2 (5/5)
EP1C6F256C6N(300) FPGA LVDS RX
4
5
PR-300 (3/20)
BOARD NO. 1-873-515-11
H