Sony SRX-R320 Service Manual page 306

PR_RX
1
BANK1
2
100 R203
7
NM
CL201
CLK_77M_IC1 CLK0/LVDSCLK1p[G1]
005 0.8
8
CL202
CLK1/LVDSCLK1n[H1]
0.8
R202
1k
R245 47 113
018 ref_clk_77M_IC1_IC33 IO84/LVDS14n[C3]
GND
2
003 AUX_IC2_IC1_0 IO0/LVDS13n[B1]
195
IO157/VREF0B1[G5]
R259 22 159
016 AUX_IC1_IC31_2 IO126[F4]
R246 22 114
018 AUX_IC1_IC33_1 IO85/LVDS12p/DQ0L0[D3]
CL245 0.8
158
003 AUX_IC1_IC2_io IO125/LVDS12n/DQ0L1[E4]
R262 22 194
CL206 0.8 IO156/DPCLK1/DQS0L[F5]
R257 22 115
018 AUX_IC1_IC33_2 IO86/LVDS11p/DQ0L2[E3]
R241 47 63
016 ref_clk_77M_IC1_IC31 IO38/LVDS11n/DQ0L3[D2]
R243 47
64
017 ref_clk_77M_IC1_IC32 IO39/LVDS10p[E2]
R242 22
4
016 AUX_IC1_IC31_1 IO1/LVDS10n[D1]
R258 22 116
017 AUX_IC1_IC32_2 IO87/LVDS9p[F3]
117
IO88/LVDS9n[G3]
R253 22
65
003 AUX_IC1_IC2_0 IO40/LVDS8p[F2]
R244 22
5
017 AUX_IC1_IC32_1 IO2/LVDS8n[E1]
R204
0 66
001,003 SDA2-PR_RX IO41/LVDS7p[G2]
6
001,003 SCL2-PR_RX IO3/LVDS7n/DM0L[F1]
R205 196
3
0 IO158/VREF1B1[H5]
IC1 (1/5)
FPGA LVDS RX
EP1C6F256C6N(300)
+3.3V
IC1
R255
10k
S202
1 2
FG1
C236
3 4
0.1uF
GND
4
BANK3
39
R206 100
001 QDI_UCLK- CLK3/LVDSCLK2n[H16]
40
001 QDI_UCLK+ CLK2/LVDSCLK2p[G16]
175
R207 100
001 QDI_U15- IO139/LVDS51n[N13]
135
001 QDI_U15+ IO104/LVDS51p[P14]
R208 100 88
001 QDI_U14- IO61/LVDS50n[P15]
32
001 QDI_U14+ IO18/LVDS50p[R16]
89
R209 100
001 QDI_U12- IO62/LVDS49n/DQ1R7[N15]
34
001 QDI_U12+ IO19/LVDS49p[N16]
209
IO170/VREF2B3[K12]
139
IO108/DQ1R6[K14]
208
IO169/DPCLK5/DQS1R[L12]
136
R210 100
001 QDI_U13- IO105/LVDS48n/DQ1R5[N14]
176
001 QDI_U13+ IO140/LVDS48p/DQ1R4[M13]
137
5
IO106/LVDS47n[M14]
177
IO141/LVDS47p[L13]
90
R211 100
001 QDI_U10- IO63/LVDS46n[M15]
35
001 QDI_U10+ IO20/LVDS46p[M16]
138
R212 100
001 QDI_U11- IO107/LVDS45n[L14]
91
001 QDI_U11+ IO64/LVDS45p[L15]
R213 100 36
001 QDI_U8- IO21/LVDS44n[L16]
37
001 QDI_U8+ IO22/LVDS44p[K16]
92
0.8
IO65/PLL2_OUTn[K15]
CL214
38
0.8
IO23/PLL2_OUTp[J16]
CL215
LVDS IN
77Mx4 308MHz
IC1 (3/5)
FPGA LVDS RX
EP1C6F256C6N(300)
A B
006 DFD_IN_UP_EV_RED
DATA OUT
006 DFD_IN_UP_EV_GRN
RATE:77MHz
006 DFD_IN_UP_EV_BLU
TP205
DFD IN
UP VD TP204
001,003
TP201
DFD IN 001,003
UP HD
TP202
9
CL216
IO4/PLL1_OUTp[J1]
0.8
69
CL217
IO42/PLL1_OUTn[K2]
0.8
121
IO90[L3]
10 22 R214
IO5/LVDS6p[K1] VDQDI_UP 006,008
11 22 R215
IO6/LVDS6n[L1] HDQDI_UP 006,008
70
IO43/LVDS5p[L2] RST_DFD_UP_EV_UP 007
12
IO7/LVDS5n[M1] RST_DFD_UP_EV_LW 007
13
IO8/LVDS4p[N1] RST_DFD_UP_OD_UP 009
71
IO44/LVDS4n[M2] RST_DFD_UP_OD_LW 009
72
IO45/LVDS3p/DQ0L4[N2]
122
IO91/LVDS3n/DQ0L5[M3]
199
CL218
IO160/DPCLK0[L5]
0.8
165
IO129/LVDS2p/DQ0L6[M4]
123 2
IO92/LVDS2n/DQ0L7[N3]
198
4
IO159/VREF2B1[K5]
164
6
IO128[L4]
15 LED_IC1_0 8
IO9/LVDS1p[R1]
73 LED_IC1_1
IO46/LVDS1n[P2] RB201
124 10k
LED_IC1_3
IO93/LVDS0p[P3]
S201
166
LED_IC1_2
IO130/LVDS0n[N4]
+3.3V
IC1
GND
R247 R249 R251
NM
NM NM
R225 CL-196YG-CD-T
1k D201
LED_IC1_0
R226 CL-196YG-CD-T
1k D202
LED_IC1_1
R248 R250 R252
R227 CL-196YG-CD-T
10k 10k 10k
D203
1k
LED_IC1_2
SLAVE 0x60 R228 CL-196YG-CD-T
1k D204
LED_IC1_3
GND
008 DFD_IN_UP_OD_RED
DATA OUT
008 DFD_IN_UP_OD_GRN
RATE:77MHz
008 DFD_IN_UP_OD_BLU
211
IO171/VREF1B3[H12]
142 R216 100
IO109/LVDS43n/DM1R[G14] QDI_U9- 001
181
IO143/LVDS43p[G13] QDI_U9+ 001
95
R217 100
IO66/LVDS42n[G15] QDI_U6- 001
41
IO24/LVDS42p[F16] QDI_U6+ 001
143 R218 100
IO110/LVDS41n[F14] QDI_U7- 001
182
IO144/LVDS41p[F13] QDI_U7+ 001
96
R219 100
IO67/LVDS40n[F15] QDI_U4- 001
42 CLK OUT 77MHz
IO25/LVDS40p[E16] QDI_U4+ 001
97 R220 100
IO68/LVDS39n[E15] QDI_U2- 001
008
43
IO26/LVDS39p[D16] QDI_U2+ 001
98
R221 100
IO69/LVDS38n[D15] QDI_U3- 001
144
IO111/LVDS38p/DQ1R3[E14] QDI_U3+ 001
213
IO173/DPCLK4[F12]
183
R222 100
IO145/LVDS37n/DQ1R2[E13] QDI_U5- 001
145
IO112/LVDS37p/DQ1R1[D14] QDI_U5+ 001
180
IO142/DQ1R0[H13]
212
IO172/VREF0B3[G12]
45
R223 100
IO27/LVDS36n[B16] QDI_U0- 001
99
IO70/LVDS36p[C15] QDI_U0+ 001
146 R224 100
IO113/LVDS35n[C14] QDI_U1- 001
184
IO146/LVDS35p[D13] QDI_U1+ 001
LVDS IN
77Mx4 308MHz
C
PR-300 (2/20) PR-300 (2/20)
SUFFIX: -11 SUFFIX: -11
RB202
RB205
22
%EGRN[4] 1 2 %EGRN[4] 22
%EBLU[2] 1 2
%EGRN[2] 3 4 %EGRN[2]
%EBLU[0]
3 4
%EGRN[0] 5 6 %EGRN[0]
%EGRN[8] 5 6
%ERED[8] 7 8
%ERED[8]
%EGRN[6] 7 8
1 2
RB203
1 2
22 %ERED[5]
3 4
%ERED[7] 3 4
%ERED[1] 5 6 %ERED[1]
%ERED[9] 5 6
%ERED[3] 7 8
%ERED[3]
%EGRN[1] 7 8
%ERED[6]
1 2 %ERED[6]
RB206
%ERED[4] 3 4 %ERED[4]
22
%ERED[2] 5 6 %ERED[2]
%ERED[0] 7 8
%ERED[0]
RB204
22
DFD_IN_UP_EV_RED
DFD_IN_UP_EV_GRN
DFD_IN_UP_EV_BLU
BANK2
100
0.8
IO71/LVDS34n[B15] IO178[E8]
CL222
47
0.8
IO28/LVDS34p[A15] IO119/LVDS24n[C8]
CL223
R260 NM
101
NC_CN1_3 IO72/LVDS33n[B14] IO151/LVDS24p[D8]
R261 CL224 0.8
NM 147
NC_CN1_2 IO114/LVDS33p[C13] IO32/LVDS23n[A8]
CL225 0.8
102
IO73/LVDS32n/DQ0T0[B13] IO78/LVDS23p[B8]
49
IO29/LVDS32p/DQ0T1[A13] IO152/LVDS22n[D7]
%EBLU[9] 103
IO74/LVDS31n/DQ0T2[B12] IO120/LVDS22p[C7]
148
%EBLU[5]
IO115/LVDS31p/DQ0T3[C12] IO79/LVDS21n[B7]
214
0.8
IO174/DPCLK3/DQS0T[E12] IO33/LVDS21p[A6]
CL248
215
IO175/VREF0B2[E11] IO179[E7]
217
IO177[E9] IO80/LVDS20n[B6]
185
%EBLU[7]
IO147/LVDS30n[D12] IO121/LVDS20p[C6]
186
%EBLU[3]
IO148/LVDS30p[D11] IO153/LVDS19n[D6]
149
%EBLU[1]
IO116/LVDS29n[C11] IO154/LVDS19p[D5]
104
%EBLU[8]
IO75/LVDS29p[B11] IO180/VREF2B2[E6]
51
%EBLU[6]
IO30/LVDS28n[A11] IO155/DPCLK2[E5]
105
%EBLU[4]
IO76/LVDS28p[B10] IO122/LVDS18n/DQ0T4[C5]
150
0.8
IO117/LVDS27n[C10] IO81/LVDS18p/DQ0T5[B5]
CL226
187
%EGRN[9]
IO149/LVDS27p[D10] IO34/LVDS17n/DQ0T6[A4]
53
+3.3V %EBLU[0]
1
IO31/LVDS26n[A9] IO82/LVDS17p/DQ0T7[B4]
106
%EBLU[2]
3 IO77/LVDS26p[B9] IO123/LVDS16n[C4]
188
%EGRN[5]
5 IO150/LVDS25n/DM0T[D9] IO83/LVDS16p[B3]
151
%EGRN[7]
7 IO118/LVDS25p[C9]
216
IO176/VREF1B2[E10]
IC1 (2/5)
FPGA LVDS RX
EP1C6F256C6N(300)
IC1
0
1
RB211 RB214
22 22
%ORED[1] %ORED[1] %ORED[9]
2 1 2 1 2 %ORED[9]
%OGRN[1]
%ORED[3] 3 4 %ORED[3] 3 4 %OGRN[1]
%OGRN[3]
%ORED[5] 5 6 %ORED[5] 5 6 %OGRN[3]
3
%ORED[7] 7 8 %ORED[7] %OGRN[5] 7 8
%OGRN[5]
%ORED[6] %OGRN[4]
1 2 %ORED[6] 1 2 %OGRN[4]
RB215 %OGRN[2]
%ORED[4] 3 4 %ORED[4] 3 4 %OGRN[2]
22
%ORED[2] 5 6 %ORED[2] %OGRN[0] 5 6 %OGRN[0]
%ORED[0] 7 8 %ORED[0] %ORED[8] 7 8
%ORED[8]
%OGRN[7]
1 2 %OGRN[7]
RB212
22 %OGRN[9]
3 4 %OGRN[9]
%OBLU[1] 5 6 %OBLU[1]
%OBLU[3] 7 8
%OBLU[3]
RB216
DFD_IN_UP_OD_RED
22
DFD_IN_UP_OD_GRN
DFD_IN_UP_OD_BLU
BANK4
74
%OBLU[7]
IO47/LVDS71p[R2] IO166/VREF1B4[M10]
17
%OBLU[9]
IO10/LVDS71n[T2] IO54/LVDS61p/DM1B[R9]
75
%OBLU[5]
IO48/LVDS70p[R3] IO14/LVDS61n[T9]
125
%OBLU[3]
IO94/LVDS70n[P4] IO99/LVDS60p[P9]
DFD IN 76
%OBLU[8]
UP CLK-O IO49/LVDS69p[R4] IO135/LVDS60n[N9]
19
%OBLU[6]
IO11/LVDS69n[T4] IO55/LVDS59p[R10]
TP203
77
%OBLU[4]
IO50/LVDS68p/DQ1B7[R5] IO15/LVDS59n[T11]
126
%OBLU[1]
IO95/LVDS68n/DQ1B6[P5] IO136/LVDS58p[N10]
R229 22
200
CLKQDI_UP_OD IO161/DPCLK7/DQS1B[M5] IO100/LVDS58n[P10]
201
IO162/VREF2B4[M6] IO56/LVDS57p[R11]
NEAR IC1 167
IO131/LVDS67p[N5] IO101/LVDS57n[P11]
168
%OGRN[9]
IO132/LVDS67n/DQ1B5[N6] IO137/LVDS56p[N11]
0.8 127
CL228 IO96/LVDS66p/DQ1B4[P6] IO138/LVDS56n[N12]
78
%OBLU[2]
IO51/LVDS66n[R6] IO165[M9]
202
IO163[M7] IO167/VREF0B4[M11]
21
%OBLU[0]
IO12/LVDS65p[T6] IO168/DPCLK6[M12]
79
%OGRN[8]
IO52/LVDS65n[R7] IO102/LVDS55p/DQ1B3[P12]
128
%OGRN[7]
IO97/LVDS64p[P7] IO57/LVDS55n/DQ1B2[R12]
169
%OGRN[5]
IO133/LVDS64n[N7] IO16/LVDS54p/DQ1B1[T13]
80
%OGRN[6]
IO53/LVDS63p[R8] IO58/LVDS54n/DQ1B0[R13]
%OGRN[4] 23
IO13/LVDS63n[T8] IO59/LVDS53p[R14]
170
0.8
IO134/LVDS62p[N8] IO103/LVDS53n[P13]
CL229
129
%OGRN[3]
IO98/LVDS62n[P8] IO17/LVDS52p[T15]
203
IO164[M8] IO60/LVDS52n[R15]
IC1 (4/5)
FPGA LVDS RX
EP1C6F256C6N(300)
C-106 C-106
D E
RB208
22
%EBLU[1] 1 2 %EBLU[1]
%EBLU[2]
%EBLU[3] 3 4 %EBLU[3]
%EBLU[0]
%EBLU[5] 5 6 %EBLU[5]
%EGRN[8]
7 8
%EBLU[7] %EBLU[7]
%EGRN[6]
%EBLU[9] 1 2 %EBLU[9]
%ERED[5] RB209
%EBLU[8] 3 4 %EBLU[8]
22
%ERED[7]
%EBLU[6] 5 6 %EBLU[6]
%ERED[9]
7 8
%EBLU[4] %EBLU[4]
%EGRN[1]
%EGRN[3] 1 2 %EGRN[3]
%EGRN[5] 3 4 %EGRN[5]
%EGRN[7] 5 6 %EGRN[7]
7 8
%EGRN[9] %EGRN[9]
RB210
22
218
152
%EGRN[3]
1608
60at100M
189 %EGRN[8]
500mA
54
%EGRN[6] C201
3216 22uF
107
%EGRN[4] C 10V
190
%EGRN[1]
C202
153 %ERED[9]
22uF 3216
10V C
108
%EGRN[2] C240
3216 22uF
56
%EGRN[0]
C 10V
219 C203
0.1uF
C204
109
%ERED[8] 0.1uF
154 DFD IN C205
CL230 0.1uF
UP CLK-E
0.8
191 C206
%ERED[7] 0.01uF
TP206
192 C207
%ERED[3]
0.01uF
CLK OUT 77MHz C208
220 NEAR IC1
0.1uF
193 R230 22 C209
0.1uF
CLKQDI_UP_EV 006
155 C210
%ERED[5]
0.1uF
110 C211
%ERED[6]
0.1uF
C212
58
%ERED[4] 0.1uF
111 C213
%ERED[2] 0.1uF
156 C214
%ERED[1]
0.01uF
112 C215
%ERED[0]
0.01uF
C216
0.01uF
C217
0.1uF
C218
0.1uF
C219
0.1uF
C220
0.1uF
GND
003,004 TCK_PR_RX
FROM EPC2 PR_RX PROM
004 TDO_EPC2_PR_RX_PROM
TO IC2 003 TDO_PR_RX_IC1
003,004 TMS_PR_RX
RB217
22
nCONFIG_PR_RX
003,004
%OBLU[9] 1 2 %OBLU[9]
R232
%OBLU[8] 3 4 %OBLU[8] +3.3V
10k
%OBLU[6] 5 6 %OBLU[6]
001,003,004 nSTATUS_PR_RX
7 8
%OBLU[4] %OBLU[4]
NM
DATA0_PR_RX
003,004
%OBLU[5] 1 2 %OBLU[5] R231
RB218 DCLK_PR_RX
003,004
%OBLU[7] 3 4 %OBLU[7]
22 GND
001,003,004 CONF_DONE_PR_RX
5 6
7 8
R256 10
003,004 INIT_DONE_PR_RX
%OBLU[2] 1 2 %OBLU[2]
%OBLU[0] 3 4 %OBLU[0]
%OGRN[8] 5 6 %OGRN[8]
7 8
%OGRN[6] %OGRN[6]
RB219
RESET 003,004 RESET_PR_RX
22
205
81
%OGRN[0]
24
%OGRN[2]
130
%OGRN[1]
171
CL231
0.8
82
%ORED[8]
26
%ORED[6]
172
%ORED[9]
131
%ORED[7]
83
%ORED[4]
132
CL227
0.8
173
%ORED[5]
174
%ORED[1]
204
206
207
CL232
SCL1-FOR_RESET_UP_EV
001
0.8
133
%ORED[3]
84
%ORED[2]
28
%ORED[0]
85
CL233
SDA1-FOR_RESET_UP_EV
001
0.8
86
CL234
SCL2-FOR_RESET_UP_OD 001
0.8
134
CL235
SDA2-FOR_RESET_UP_OD 001
0.8
30
CL236
R265
0.8 R266
87
CL237
47k 47k
0.8
R263 R264
47k 47k
GND
F
+1.5V
FB203
140038221
1608
180at100M
1.5A
C221
22uF
6.3V 3216
C222
22uF
6.3V 3216
C223
0.1uF
C224
0.1uF
C225 55 1
0.1uF
VCCINT4[A7] GND1[A1]
C226 52 46
0.1uF
VCCINT3[A10] GND6[A16]
C227 252 57
0.1uF
VCCINT10[G8] GND8[A5]
C228 250 50
0.1uF
VCCINT9[G10] GND7[A12]
C229 242 221
0.1uF
VCCINT5[H7] GND9[F6]
C230
256 239
0.1uF
VCCINT12[H9] GND18[F8]
254 238
+3.3V
VCCINT11[J8] GND17[F9]
GND
248 236
FB201
VCCINT8[J10] GND16[F11]
244 241
VCCINT6[K7] GND19[G7]
FB202 246 251
140038221 1608 VCCINT7[K9] GND24[G9]
180at100M 1.5A 22 235
VCCINT1[T7] GND15[G11]
25 253
VCCINT2[T10] GND25[H8]
249
GND23[H10]
3 243
VCCIO1_1[C1] GND20[J7]
222 255
VCCIO1_3[G6] GND26[J9]
+1.5V-PLL_PR_RX
14 225
VCCIO1_2[P1] GND10[K6]
245
FB204
GND21[K8]
146909421
48 247 1608
VCCIO2_1[A14] GND22[K10] 60at100M
237 226 500mA
VCCIO2_3[F10] GND11[L6]
240 228
VCCIO2_4[F7] GND12[L8]
59 229 C239
VCCIO2_2[A3] GND13[L9]
10uF
231
GND14[L11] 6.3V 2012
33 16
VCCIO3_1[P16] GND2[T1] C231
232 20
10uF
VCCIO3_3[K11] GND3[T5]
44 27 6.3V 2012
VCCIO3_2[C16] GND4[T12]
31
C232
GND5[T16]
1000pF
18
VCCIO4_1[T3]
227 223
VCCIO4_3[L7] VCCA_PLL1_1[H6]
230 224 C233
VCCIO4_4[L10] GNDA_PLL1_1[J6] 0.1uF
29 197
C234
VCCIO4_2[T14] GNDG_PLL1_1[J5]
1000pF
140 234
TCK_3[J14] VCCA_PLL2_3[H11]
R233 10 141 233
C235
TDI_3[H14] GNDA_PLL2_3[J11] 0.1uF
R234 10 94 BANK3 210
TDO_3[H15] GNDG_PLL2_3[J12]
93
TMS_3[J15]
GND
+3.3V
R240 10k
119
MSEL0_1[J3]
PS 68 BANK1
MSEL1_1[J2]
R235 10 GND 118
nCONFIG_1[H3]
161
CL238
nCEO_1[H4] BANK1
0.8
162
nCE_1[J4]
R236 10 179
nSTATUS_3[J13] BANK3
R237 10 67
DATA0_1[H2]
10
R238 163 BANK1
DCLK_1[K4]
R239 10 178
CONF_DONE_3[K13] BANK3
0.8 157
CL239
IO124/LVDS14p/INIT_DONE_1[D4]
62
CL240
IO37/LVDS13p/CLKUSR_1[C2]
0.8
160
CL241
IO127/nCSO_1[G4] BANK1
0.8
120
CL242
IO89/ASDO_1[K3]
0.8 60
CL243
IO35/LVDS15n/DEV_OE[A2]
0.8 R254 10
61 BANK2
IO36/LVDS15p/DEV_CLRn[B2]
IC1 (5/5)
EP1C6F256C6N(300) FPGA LVDS RX
PR-300 (2/20)
BOARD NO. 1-873-515-11
SRX-R320
G H