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The JP22, 23, 24 used to setting the system PLL clock rate for meet with
the best feature of I/O interface performance. Please set the clock rate
at a necessary operating condition. An over specification setting will
cause the system malfunction or un-stateable.
PLL Clock setting
PLL Clock
50 MHz
60 MHz
*66 MHz
75 MHz
*) : default setting
The above default setting of JP3, JP4, JP5, JP9, JP12, JP16, JP22,
JP23 and JP24 show a AMDK6-166(2.9V) CPU in used. ( i.e. 66.6 x 2.5
≈ 166 MHz ). Please contact with your CPU supplier for detail
specification in correcting selected setting of all.
2.8 CMOS Data Clear
The JP14 provides a hardware CMOS data clear function with an ON to
it. Never clear CMOS data during power on in case of damage the
sensitive electronic components or the board.
CMOS Data Clear (Only for DS12B887)
JP14
ON
*OFF
14
JP22 JP23 JP24
1-2
2-3
1-2
1-2
1-2
2-3
2-3
1-2
2-3
1-2
2-3
2-3
DESCRIPTION
Clear Data
Normal
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