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PROCESSOR/ RESERVED
CFG Straps for Processor
PEG Stati c Lan e Reve rsal - CFG 2 is for t he 16 x
CFG2
1: (Defa ult) Norma l Ope ration ; Lan e #
de finit ion m atche s soc ket pi n map defi nitio n
0: Lane Rever sed
C F G 2
R 11 1
*1 K _ 0 4
Disp lay P ort P resenc e Str ap
1: (Defa ult) Disab led; No Phy sical Disp lay P ort
CFG4
at tache d to Embed ded D isplay Port
0: Enabl ed; A n ext ernal Displ ay Po rt de vice is
co nnect ed to the Embed ded Di splay Port
C F G 4
R 11 0
*1 K _ 0 4
PCIE Port Bifu rcatio n Str aps
11: ( Defau lt) x 16 - Devic e 1 f unctio ns 1 and 2 disa bled
10: x 8, x8 - De vice 1 fun ction 1 ena bled ; fun ction 2 di sabled
CFG[6:5]
01: R eserv ed - (Devi ce 1 funct ion 1 disab led ; func tion 2 enab led)
00: x 8,x4, x4 - Devic e 1 f uncti ons 1 and 2 enab led
C F G 5
R 99
*1 K _ 0 4
C F G 6
R 92
*1 K _ 0 4
PEG DEFER TRAI NING
1: (Def ault) PEG Train immed iatel y fol lowin g xxR ESETB de as serti on
CFG7
0: PEG Wait for B IOS f or tra ining
C F G 7
R 93
*1 K _ 0 4
3 . 3 V
Sandy Bridge Processor 7/7
( RESERVED )
U 3 4 E
A K 2 8
C F G 0
C F G [ 0]
A K 2 9
C F G [ 1]
A L 2 6
C F G 2
C F G [ 2]
A L 2 7
A K 2 6
C F G [ 3]
C F G 4
C F G [ 4]
C F G 5
A L 2 9
A L 3 0
C F G [ 5]
C F G 6
C F G [ 6]
C F G 7
A M 3 1
A M 3 2
C F G [ 7]
C F G [ 8]
A M 3 0
A M 2 8
C F G [ 9]
C F G [ 10 ]
A M 2 6
A N 2 8
C F G [ 11 ]
C F G [ 12 ]
A N 3 1
A N 2 6
C F G [ 13 ]
C F G [ 14 ]
A M 2 7
A K 3 1
C F G [ 15 ]
C F G [ 16 ]
A N 2 9
C F G [ 17 ]
A J 3 1
H _ C P U _R S V D 1
V A X G_ V A L _ S E N S E
H _ C P U _R S V D 2
A H 3 1
V S S A X G_ V A L _ S E N S E
H _ C P U _R S V D 3
A J 3 3
V C C _V A L_ S E N S E
H _ C P U _R S V D 4
A H 3 3
V S S _ V A L _S E N S E
A J 2 6
R S V D 5
V R E F _ C H _ A _ D I MM
B 4
R S V D 6
V R E F _ C H _ B _ D I MM
D 1
R S V D 7
F 2 5
R S V D 8
F 2 4
F 2 3
R S V D 9
R S V D 1 0
D 2 4
G 2 5
R S V D 1 1
R S V D 1 2
G 2 4
E 2 3
R S V D 1 3
R S V D 1 4
D 2 3
C 3 0
R S V D 1 5
R S V D 1 6
A 3 1
B 3 0
R S V D 1 7
R S V D 1 8
B 2 9
D 3 0
R S V D 1 9
R S V D 2 0
B 3 1
A 3 0
R S V D 2 1
R S V D 2 2
C 2 9
R S V D 2 3
J 2 0
R S V D 2 4
B 1 8
A 1 9
R S V D 2 5
V C C I O_ S E L
J 1 5
R S V D 2 7
1 0/2 9
P Z 9 8 82 7 -3 64 B -0 1 F
R 3 9 2
10 K _ 0 4
R 3 9 1
* 10 m i l _ 0 4
H _ S N B _ I V B # _P W R C TR L
On CRB
H_S NB_IVB #_PWR CTRL = low , 1.0 V
H_S NB_IVB #_PWR CTRL = hig h/NC, 1.05 V
L 7
R S V D 2 8
A G 7
R S V D 2 9
A E 7
R S V D 3 0
A K 2
R S V D 3 1
W 8
R S V D 3 2
A T 2 6
R S V D 3 3
A M 33
R S V D 3 4
A J 2 7
R S V D 3 5
T 8
R S V D 3 7
J 1 6
R S V D 3 8
H 1 6
R S V D 3 9
G1 6
R S V D 4 0
A R 35
R S V D 4 1
A T 3 4
R S V D 4 2
A T 3 3
R S V D 4 3
A P 3 5
R S V D 4 4
A R 34
R S V D 4 5
B 3 4
R S V D 4 6
A 3 3
R S V D 4 7
A 3 4
R S V D 4 8
B 3 5
R S V D 4 9
C 3 5
R S V D 5 0
1. 5 V
R 40
* 0_ 0 4
A J 3 2
R S V D 5 1
A K 3 2
R 3 8
R S V D 5 2
Q 7
1 K _ 1 % _0 4
* A O3 4 02 L
A H 27
S
D
V R E F _C H _ A _ D I M M
MV R E F _ D Q _D I M0
V C C _ D I E _ S E N S E
R 3 9
R 3 1
A N 35
*1 K _ 04
R S V D 5 4
A M 35
1 K _ 1 % _0 4
R S V D 5 5
D R A MR S T _C N T R L 3 , 1 4
A T 2
R S V D 5 6
A T 1
R S V D 5 7
A R 1
1 . 5 V
R S V D 5 8
R 44
* 0_ 0 4
B 1
R 2 8
K E Y
Q 6
* A O3 4 02 L
1 K _1 % _ 0 4
V R E F _C H _ B _ D I M M
S
D
MV R E F _ D Q _ D I M 1
R 4 9
R 2 9
*1 K _ 04
1 K _1 % _ 0 4
D R A MR S T _C N T R L
3 , 6 , 9 , 1 0, 2 0 , 2 7, 3 2 , 3 4
1. 5 V
2 , 3 , 11 , 1 3 , 1 5, 1 7 , 1 9, 20 , 2 2 , 23 , 2 7 , 2 9, 3 1 , 3 2, 3 4 , 3 6
3. 3 V
Schematic Diagrams
Sheet 8 of 46
PROCESSOR/
RESERVED
M V R E F _ D Q_ D I M MA 9
1 0/ 29
M V R E F _ D Q_ D I M MB 1 0
1 0/ 29
PROCESSOR/ RESERVED B - 9
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