Processor/ Power1 - Clevo W243HWQ Series Service Manual

Schematic Diagrams

PROCESSOR/ POWER1

PROCES SOR CORE POWER
ICCMAX Maximum Process or
Sheet 5 of 46
PROCESSOR/
POWER1
B - 6 PROCESSOR/ POWER1
Sandy Bridge Processor 4/7
POWER
U 3 4 F
layout? check
V C O R E
48A
A G3 5
V C C 1
A G3 4
V C C 2
A G3 3
V C C 3
A G3 2
SV 48
V C C 4
A G3 1
A G3 0 V C C 5
V C C 6
V C OR E A G2 9
V C C 7
A G2 8
A G2 7 V C C 8
C 3 5 3 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 9
A G2 6
V C C 10
A F 3 5
C 3 7 1 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 11
A F 3 4
A F 3 3 V C C 12
C 3 6 6 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 13
A F 3 2
V C C 14
C 3 5 4 2 2u _ 6 . 3 V _ X 5 R _ 0 8 A F 3 1
A F 3 0 V C C 15
V C C 16
A F 2 9
C 3 5 9 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 17
A F 2 8
A F 2 7 V C C 18
C 3 6 3 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 19
A F 2 6
V C C 20
A D 3 5
C 3 3 7 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 21
A D 3 4
A D 3 3 V C C 22
C 3 3 2 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 23
A D 3 2
V C C 24
C 3 5 1 2 2u _ 6 . 3 V _ X 5 R _ 0 8 A D 3 1
A D 3 0 V C C 25
V C C 26
A D 2 9
C 3 3 6 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C 27
A D 2 8
V C C 28
A D 2 7
V C C 29
A D 2 6
V C C 30
A C 3 5
V C C 31
V C OR E A C 3 4
A C 3 3 V C C 32
V C C 33
A C 3 2
C 6 9 1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 34
A C 3 1
A C 3 0 V C C 35
C 3 3 1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 36
A C 2 9
V C C 37
A C 2 8
C 7 4 1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 38
A C 2 7
A C 2 6 V C C 39
C 5 6 1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 40
A A 3 5
V C C 41
C 3 4 1 0u _ 6 . 3 V _ X 5 R _ 0 6 A A 3 4
A A 3 3 V C C 42
V C C 43
A A 3 2
C 5 3 1 0u _ 6 . 3 V _ X 5 R _ 0 6
V C C 44
A A 3 1
V C C 45
A A 3 0
V C C 46
A A 2 9
V C C 47
V C OR E A A 2 8
V C C 48
A A 2 7
A A 2 6 V C C 49
C 3 6 2 *2 2 u _ 6. 3V _X 5 R _ 08
V C C 50
Y 3 5
V C C 51
C 3 6 0 *2 2 u _ 6. 3V _X 5 R _ 08 Y 3 4
Y 3 3 V C C 52
V C C 53
Y 3 2
C 3 3 4 *2 2 u _ 6. 3V _X 5 R _ 08
V C C 54
Y 3 1
V C C 55
C 3 3 3 *2 2 u _ 6. 3V _X 5 R _ 08 Y 3 0
Y 2 9 V C C 56
V C C 57
Y 2 8
C 3 5 6 *2 2 u _ 6. 3V _X 5 R _ 08
V C C 58
Y 2 7
Y 2 6 V C C 59
C 6 2 *1 0 u _ 6. 3V _X 5 R _ 06
V C C 60
V 3 5
V C C 61
V 3 4
C 7 2 *1 0 u _ 6. 3V _X 5 R _ 06
V 3 3 V C C 62
V C C 63
V 3 2
C 5 9 *1 0 u _ 6. 3V _X 5 R _ 06
V C C 64
V 3 1
V C C 65
C 6 6 *1 0 u _ 6. 3V _X 5 R _ 06 V 3 0
V 2 9 V C C 66
V C C 67
V 2 8
V C C 68
V 2 7
V 2 6 V C C 69
V C C 70
U 3 5
V C C 71
U 3 4
V C C 72
U 3 3
V C C 73
U 3 2
V C C 74
U 3 1
V C C 75
U 3 0
U 2 9 V C C 76
V C C 77
U 2 8
V C C 78
U 2 7
U 2 6 V C C 79
V C C 80
R 3 5
V C C 81
R 3 4
V C C 82
R 3 3
R 3 2 V C C 83
V C C 84
R 3 1
V C C 85
R 3 0
R 2 9 V C C 86
V C C 87
R 2 8
V C C 88
R 2 7
R 2 6 V C C 89
V C C 90
P 3 5
V C C 91
P 3 4
V C C 92
P 3 3
P 3 2 V C C 93
V C C 94
P 3 1
V C C 95
P 3 0
P 2 9 V C C 96
V C C 97
P 2 8
V C C 98
P 2 7
V C C 99
P 2 6
V C C 10 0
P Z 9 88 2 7 -3 6 4 B -0 1 F
PROCESSOR UNCORE POWER
A H 1 3
V C C I O1
A H 1 0
V C C I O2
A G1 0
C 3 6 1 C 3 5 7 C 3 6 5
V C C I O3
A C 1 0
V C C I O4 Y 1 0
2 2 u _ 6 . 3 V _ X5 R _ 0 8 2 2 u _ 6 . 3V _ X5 R _ 0 8 2 2 u _ 6. 3V _X 5 R _ 08
V C C I O5
U 1 0
V C C I O6
P 1 0
V C C I O7 L 10
V C C I O8
J 14
V C C I O9
J 13
C 3 5 5 C 3 4 4 C 3 6 4
V C C I O 10
J 12
V C C I O 11 J 11
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C I O 12
H 1 4
V C C I O 13
H 1 2
V C C I O 14 H 1 1
V C C I O 15
G1 4
V C C I O 16
G1 3
C 3 9 6 C 4 1 9 C 4 0 6
V C C I O 17 G1 2
V C C I O 18
F 1 4
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C I O 19
F 1 3
V C C I O 20
F 1 2
V C C I O 21 F 1 1
V C C I O 22
E 1 4
V C C I O 23
E 1 2 C 3 2 1 C 4 1 8 C 3 7 5
V C C I O 24
E 1 1
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 2 2 u _ 6. 3V _X 5 R _ 08
V C C I O 25
D 1 4
V C C I O 26
D 1 3
V C C I O 27
D 1 2
V C C I O 28
D 1 1
V C C I O 29
C 1 4 C 4 0 7 C 3 7 2 C 3 5 2
V C C I O 30 C 1 3
V C C I O 31
C 1 2
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 2 2 u _ 6 . 3V _ X5 R _ 0 8 2 2 u _ 6. 3V _X 5 R _ 08
V C C I O 32
C 1 1
V C C I O 33 B 1 4
V C C I O 34
B 1 2
V C C I O 35
A 1 4
V C C I O 36
A 1 3 C 3 8 1 C 3 9 4 C 4 2 0
V C C I O 37 A 1 2
V C C I O 38
A 1 1
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8 * 2 2u _ 6 . 3 V _ X 5 R _ 0 8
V C C I O 39
J 23
+ V 1 . 0 5 S _ V C C P _ F R 6 2 *2 0 m i l _0 4
V C C I O 40 1 . 0 5V S _ V T T
CAD Note: H_CPU_SVIDALRT#_R, H_CPU_SVIDDAT_R
Place the PU resistors close to CPU
A J 2 9 H _ C P U _ S V I D A L R T #_ R
R 4 0 6 4 3_ 1 % _ 0 4
H _ C P U _S V I D A L R T # 3 7
V I D A L E R T# A J 3 0
H _ C P U _ S V I D C LK _ R R 8 8 0 _0 4
V I D S C L K H _ C P U _S V I D C L K 3 7
A J 2 8
H _ C P U _ S V I D D A T _ R R 8 5 0 _0 4
V I D S O U T H _ C P U _S V I D D A T 3 7
CAD Note: H_CPU_SVIDCLK_R
Place the PU
resistors close to VR
V C OR E _ V C C _ S E N S E
V C OR E _ V S S _ S E N S E
1126
V C OR E 1 . 0 5 V S _V TT
A J 3 5
R 6 87 R 3 7 9
V C C _ S E N S E A J 3 4
V S S _ S E N S E
* 10 _ 0 4 10 _ 0 4
B 1 0
V C C I O _ S E N S E _ R R 38 4 * 0 _ 04
V C C I O _ S E N S E V C C I O _ S E N S E 3 5
A 1 0 V S S I O _ S E N S E
V S S I O _ S E N S E
R 38 3
1 0 _0 4
layout? check
8.5A 1 . 0 5 V S _ V T T
C 3 98 C 3 50 C 4 0 2
+
* 22 u _ 6 . 3 V _ X 5 R _ 0 8 * 22 u _ 6 . 3 V _ X 5R _ 0 8
2 2 0 u _ 6. 3 V _6 . 3 * 6 . 3* 4 . 2
C 3 58 C 3 46 C 4 1 7
+
* 22 u _ 6 . 3 V _ X 5 R _ 0 8 2 2 u _6 . 3 V _ X 5 R _0 8
2 2 0 u _ 6. 3 V _6 . 3 * 6 . 3* 4 . 2
C 3 97 C 3 84
* 22 u _ 6 . 3 V _ X 5 R _ 0 8 2 2 u _6 . 3 V _ X 5 R _0 8
C 3 83 C 3 82
2 2 u _ 6. 3 V _X 5 R _ 08 * 22 u _ 6 . 3 V _ X 5R _ 0 8
C 3 67 C 3 85
2 2 u _ 6. 3 V _X 5 R _ 08 2 2 u _6 . 3 V _ X 5 R _0 8
C 3 68
* 22 u _ 6 . 3 V _ X 5 R _ 0 8
SVID Signals
1 . 0 5 V S _ V T T
H _ C P U _ S V I D A L R T #
7 5 _ 1 % _0 4 R 4 0 8
H _ C P U _ S V I D C L K * 5 4. 9_ 1 % _ 0 4 R 8 9
H _ C P U _ S V I D D A T _ R 1 3 0 _ 1 %_ 0 4 R 8 6
3 7
3 7
3 7 , 3 8 V C OR E
2 , 3 , 18 , 1 9 , 2 0 , 3 5 , 3 7 1 . 0 5V S _ V T T