768
DE
DE
DCLK
DATA
Tckh
DCLK
DATA
DE
Panel Specification
INPUT SIGNAL TIMING DIAGRAM
T
vdb
1
T
hp
T
hdb
Valid display data (1024 Tck)
Tckl
T
vp
T
vda
768
2
T
hda
T
ck
T
ch
T
T
sd
hd
T
T
sde
hde
Invalid
Valid
0.7VDD
0.5VDD
0.3VDD
0.7VDD
0.3VDD
0.7VDD
