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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
Parameter
DCLK
Pixel clock Frequency
Pixel clock period
Duty ratio (%Tch)
H
g i
h
i t
m
L
o
w
t
m i
DATA
S
e
u t
p
t
m i
DE
H
o
d l
i t
m
S
e
u t
p
t
m i
H
o
d l
i t
m
Vertical Frequency
Vertical
Vertical display active period
Vertical display blank period
Vertical period
Horizontal
Horizontal
period
Horizontal display blank period
Horizontal period
Note (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low logic level or ground. Otherwise, this module would operate abnormally.
Panel Specification
e
e
e
e
e
e
display
active
Symbol
Min
Typ
Fck
-
65
Tck
12.5
15
-
45
50
T
k c
h
5
-
c T
l k
5
-
s T
d
4
-
T
h
d
4
-
s T
d
e
4
-
T
h
d
e
4
-
Fv
-
60
Tvda
768
768
Tvdb
1
38
Tvp
769
806
Thda
1024
1024
Thdb
76
320
Thp
1100
1344
Max
Unit
Remarks
80
MHz
20
ns
55
%
Tch/Tck
-
n
s
-
n
s
-
n
s
-
n
s
-
n
s
-
n
s
75
Hz
768
Thp
-
Thp
-
Thp
1024
Tck
776
Tck
1800
Tck
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