Table of Contents
Advertisement
IC BLOCK DIAGRAMS
IC2A2 SAA7114H
30
RESON
27
CE
4
XTOUT
7
XTALI
6
XTAL
20
AI11
18
AI12
16
AI21
14
AI22
12
AI23
10
AI24
22
AOUT
19
AI1D
13
AI2D
21
AGND
PCB-MAIN DIGITAL2
IC410,416 HD74LVC245AT
2
A0
3
A1
4
A2
5
A3
A
DATA
PORT
6
A4
7
A5
8
A6
9
A7
1
T/R
19
OE
4
IC2A1 NJM431U
1
REFERENCE
28 29 36 34 35
94 95 81,82,
84-87,
89,90,
RT out
eXpansion port pin mapping
X port I/O formatting
digital
decoder
analog
with
dual
adaptive
ADC
comb
filter
boundary
audio
scan
clock
test
ganeration
8
97
98 99 3 2
37 40 39 41
18
B0
17
B1
16
B2
15
B3
B
DATA
PORT
14
B4
13
B5
12
B6
11
B7
92 91 96 80
64-67,
32 31
69-72,
I/O control
IIC
chroma of 16 bit input
Note:
The pins RTCO and ALRCLK
are used for configuration
programming
A/B
of the IIC Interface and the
Register
Reg.
definition of the crystal osc.
array
MUX
frequency at RESET
(pin strapping)
event controller
Horizonal
FIR-Prefilter
Line
Perscaler
Vertical
FIFO
(Phase)
and
Scaling
buffer
Scaling
scaler BCS
general purpose
VBI data sllcer
33,43,
58,68,
1,25,
11,17, 38,63, 26,50, 9,15,
5
83,93
51,75
23
88
TRUTH TABLE
IN
OUT
OE
T/R
L
L
B DATA A DATA
L
H
A DATA B DATA
H
X
ISOLATION
H
: HIGH LEVEL
L
: LOW LEVEL
X
: DON'T CARE
3
CATHODE
2
ANODE
79
78 77 74 73 44
54-57,
59-62
46
53
Fine
video
52
FIFO
48
32
to
49
8(16)
MUX
text
45
FIFO
42
video/text
47
arbiter
76,100 24
IC411,419 AZ10ELT22D
8
1
Q0
V
CC
2
7
Q0
D0
PECL
TTL
3
6
D1
Q1
4
5
GND
Q1
IPD[7:0]
IDQ
IGPH
IGPV
IGP0
IGP1
ICLK
ITRDY
ITRI
Advertisement
Table of Contents
