IDEC DD3S Series Manual page 6

DD3S Display Units
Series
Terminal Connection
Connection Diagram
Standard
(Terminal No.)
Vcc 4
Power
Regulating Circuit
GND 12
Latch
8
+
10
–
9
1
5
BL
7
LT 6
DP 2
Standard
(Terminal No.)
Vcc 4
Power
Regulating Circuit
GND 12
Latch
8
A ( 2 )
0 10
B ( 2 )
1 3
C ( 2 )
2 5
D ( 2 ) 3
9
BL
7
LT 6
DP
2
2-color Alternate Display
(Terminal No.)
Vcc 4
Power
Regulating Circuit
GND
12
Latch 8
A ( 2 )
0 10
B ( 2 )
1 3
C ( 2 )
2 5
D ( 2 )
3
9
BL 7
R/G 6
DP
2
Zero-suppress
(Terminal No.)
Vcc
4
Power
Regulating Circuit
GND 12
Latch 8
A ( 2 )
0 10
B ( 2 )
1 3
C ( 2 ) 5
2
D ( 2 )
3 9
BL 7
LT
6
RBI 1
DP 2
RBO 11
(Terminal No.)
Power
Regulating Circuit
Control Input
Latch
Data Input
6
Terminal Arrangement
Standard
(Terminal No.)
12.
11.
−
10.
9.
Power
8.
12 to 24V DC
7.
+
6.
5.
4.
3.
2.
1.
Standard
(Terminal No.)
12.
11.
− 10.
9.
Power
8.
12 to 24V DC
7.
+
6.
5.
4.
3.
2.
1.
2-color Alternate Display
(Terminal No.)
12.
11.
−
10.
9.
Power
8.
12 to 24V DC
7.
+
6.
5.
4.
3.
2.
1.
Zero-suppress
(Terminal No.)
12.
11.
−
10.
9.
Power
8.
12 to 24V DC
7.
+
6.
5.
4.
3.
2.
1.
5 x 7 dot matrix LED
Data Input
Power
Control Input
GND
NC
+
–
Latch
BL
LT
1
Vcc
NC
DP
NC
GND
NC
A ( 2 )
0
Positive Logic
D ( 2 )
3
Latch
BL
LT
Data Input
C ( 2 )
2
Vcc
B ( 2 )
1
DP
NC
Negative Logic
GND
NC
A ( 2 )
0
D ( 2 )
3
Data Input
Latch
BL
R/G
C ( 2 )
2
Vcc
B ( 2 )
1
DP
NC
GND
RBO
A ( 2 )
0
D ( 2 )
3
Latch
BL
LT
C ( 2 ) 2
Vcc
B ( 2 )
1
DP
RBI
Positive Logic
Data Input
(Terminal No.)
Negative Logic
Latch
Data Input
Internal Input Circuit
200 k
12 k 200 k
GND
12 to 24V DC
12 kΩ
200 kΩ
200 kΩ
GND
470 kΩ
12 kΩ 470 kΩ
GND
12 to 24V DC
12 kΩ
470 kΩ
470 kΩ
GND