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Digital Equipment DECmpp 12000/Sx 100 Hardware Service Manual

Decmpp 12000/sx series
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DECmpp 12000/Sx Model 100
Hardware Service Manual
Part Number: EK–DECAC–SM. C01
September 1992
This document provides service and diagnostic procedures for DECmpp
12000/Sx and DECmpp 12000–LC/Sx Series systems.
Revision/Update Information:
Operating System and Version: ULTRIX Version 4.2A.
Software Version:
Digital Equipment Corporation
Maynard, Massachusetts
This document has been revised for
DECmpp Version 1.1.
Future releases may require higher
versions.
DECmpp 12000/Sx Version 1.1.

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Summary of Contents for Digital Equipment DECmpp 12000/Sx 100

  • Page 1 12000/Sx and DECmpp 12000–LC/Sx Series systems. Revision/Update Information: This document has been revised for DECmpp Version 1.1. Operating System and Version: ULTRIX Version 4.2A. Future releases may require higher versions. Software Version: DECmpp 12000/Sx Version 1.1. Digital Equipment Corporation Maynard, Massachusetts...
  • Page 2 Revised, September 1992 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.

  • Page 3: Table Of Contents

    Contents Preface ............1 System Overview Turning the System On and Off .
  • Page 4 6 Removal and Replacement Procedures Card Cage Access ..........6–1 DPU Card Cage Slots .
  • Page 5 Index Figures 1–1 Typical DECmpp 12000/Sx Installation with DECsystem 5900 Server ..........1–2 1–2 Typical DECmpp 12000/Sx Installation with DECstation 5000/240...
  • Page 6 Tables Related Documents ........viii 1–1 DPU Power Settings .

  • Page 7: Preface

    Preface This manual provides service and diagnostic procedures for DECmpp 12000/Sx systems. Anyone who services DECmpp 12000/Sx Series systems or needs to replace any items should read this manual and be familiar with the procedures. Intended Audience This guide is for use by Digital Services personnel and by self-maintenance customers who will be servicing the DECmpp 12000 and DECmpp 12000–LC systems.

  • Page 8: Related Documents

    Related Documents Table 1 lists documents that provide additional information about the DECmpp 12000/Sx system. Table 1 Related Documents Document Title Order Number DECmpp 12000/Sx System Overview Manual AA-PMAPB-TE DECmpp 12000/Sx System Administration Guide AA-PKU3C-TE DECmpp 12000/Sx Architecture Specification AA-PMASB-TE DECmpp 12000/Sx Parallel Disk Array Reference Manual EK-DECAB-RM DECmpp 12000/Sx Parallel VME Reference Manual...
  • Page 9 Conventions The following conventions are used throughout the DECmpp 12000/Sx documentation set: Convention Meaning In examples, a key name shown within a box indicates that Return you press a key on the keyboard. In text, a key name is not enclosed in a box but is printed with an initial capital letter, like Return.
  • Page 10 Both the DECmpp 12000/Sx and DECmpp 12000–LC/Sx Series hardware systems are described in this manual. However, because the two systems are very similar, references to the DECmpp 12000 system also apply to the DECmpp 12000–LC system, unless specific differences between the two systems are noted. Three types of notes are used in this manual: •...

  • Page 11: System Overview

    System Overview DECmpp 12000/Sx Series systems are powerful single-instruction, multiple data (SIMD) computers, consisting of a data parallel unit (DPU), which performs the parallel calculations, and a front-end server. The server runs the ULTRIX operating system and functions as a scalar processor. A high-speed VMEbus interface carries data between the DPU and the front-end server.

  • Page 12: Typical Decmpp 12000/Sx Installation With Decsystem 5900 Server

    Figure 1–1 Typical DECmpp 12000/Sx Installation with DECsystem 5900 Server Parallel Disk Array DECsystem 5900 Server Data Parallel Unit (Optional) DECmpp 12000 Sx Series Console Monitor MKV−040000314−19−RAGS Figure 1–2 Typical DECmpp 12000/Sx Installation with DECstation 5000/240 Server Data Parallel Unit Parallel Disk Array (Optional) DECstation 5000/240...

  • Page 13: Typical Decmpp 12000-Lc/Sx Installation

    Figure 1–3 Typical DECmpp 12000–LC/Sx Installation Parallel Disk Array (Optional) Data Parallel Unit DECstation 5000/240 Server DECmpp 12000 MKV−040000314−23−RAGS System Overview 1–3...

  • Page 14: Turning The System On And Off

    1.1 Turning the System On and Off 1.1 Turning the System On and Off The DPU has three switches that control power: the keyswitch, the power selector, and the circuit breaker. Figure 2–1, Figure 2–2, and Figure 2–4 show their locations. Chapter 2 provides details on these switches. The DPU keyswitch inside the front door has three positions: OFF, ON, and DIAGNOSTIC: •...

  • Page 15: Decsystem 5900 Power Switch

    1.1 Turning the System On and Off Figure 1–4 DECsystem 5900 Power Switch MKV-040000314-36-DG Figure 1–5 DECstation 5000 Power Switch MKV-040000314-50-DG System Overview 1–5...

  • Page 16: Powerup Sequence

    1.1 Turning the System On and Off 1.1.1 Powerup Sequence Caution To avoid unpredictable system operation, always turn the system components on or off in the correct sequence. Take these steps to power up the DECmpp 12000/Sx: 1. Set the DPU rear circuit breaker to ON. 2.

  • Page 17: Dpu Controls And Indicators

    DPU Controls and Indicators Chapter 2 provides descriptions and functional definitions of the data parallel unit (DPU) controls. Indicators on both the outside and the inside of the DPU show the status of the system and critical internal components. Figure 2–1 (DECmpp 12000) and Figure 2–2 (DECmpp 12000–LC) show the locations of the DPU front controls and indicators.

  • Page 18: Decmpp 12000/Sx Dpu Front Controls And Indicators

    Figure 2–1 DECmpp 12000/Sx DPU Front Controls and Indicators Power Status Indicators 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Front Controls (Located Inside Front Door) MKV−040000314−58−RAGS 2–2 DPU Controls and Indicators...

  • Page 19: Decmpp 12000-Lc/Sx Dpu Front Controls And Indicators

    Figure 2–2 DECmpp 12000-LC/Sx DPU Front Controls and Indicators Power Status Indicators 19 18 16 15 14 13 12 09 08 06 05 04 03 02 MKV−040000314−52−RAGS Figure 2–3 DPU Front Controls DISCONNECT CONNECT DIAGNOSTIC MODEM RESET POWER MKV−040000314−43−RAGS DPU Controls and Indicators 2–3...

  • Page 20: Dpu Rear Controls And Indicators

    Figure 2–4 DPU Rear Controls and Indicators Remote Daisy−chain Temperature Sensor DPU Interface PCA Fan Tray Power Selector Switch P1 P2 P13 Modem Power LEDs Backplane Sense Lines Lightpipe/ 1A Circuit Key Switch 30A Circuit Breaker Breaker Power Cable Connection MKV−040000314−81−RAGS 2–4 DPU Controls and Indicators...

  • Page 21: Overview Of Controls And Indicators

    2.1 Overview of Controls and Indicators 2.1 Overview of Controls and Indicators Several of the DECmpp 12000/Sx controls and indicators are described briefly in the list below. The rest are described in more detail in the following sections. • POWER (keyswitch) — Controls power to the DPU and enables the VMEbus RESET button.
  • Page 22 2.2 DPU Power System • The POWER SELECTOR switch is on the power tray panel inside the DPU enclosure at the rear. It is a toggle switch that must be pulled out slightly before it can be moved. It has three positions. LOCAL (middle position): Allows the DPU to power up independent of the server.

  • Page 23: Indicators

    2.3 Indicators 2.3 Indicators The DPU has indicators on the front panel, the ACU PCB, the MVIB Front-end VME interface PCB (T6000), the PVME PVB, the PE array PCBs, the router PCBs, and on the power tray. All of these indicators provide information about the status of the system.

  • Page 24: Pcb Service Indicator Locations

    2.3 Indicators Figure 2–5 PCB Service Indicator Locations PVME Indicators MVIB Indicator Indicators Modem (USA Only) PE or Router PCBs (Shown with 4 PE PCBs and 12 Router PCBs) PE and Router Indicators DECmpp 12000 Card Cage MVIB Indicator Modem (USA Only) Indicators PE and Router Indicators...

  • Page 25: Power Tray Indicators

    2.3 Indicators 2.3.2.1 Power Tray Indicators Figure 2–6 shows the ten indicators located on the DPU power tray rear panel. These indicators provide information about the power tray. They all show the status of some part of the power tray and are green during normal operation. If a failure is detected, the corresponding indicator changes to red, and the power tray shuts down.

  • Page 26: Array Control Unit Pcb Indicators

    2.3 Indicators The chassis ground circuit detects differences in potential between chassis ground and logic ground and shuts down the power tray when the potential exceeds a preset 70 mV threshold. 2.3.2.2 Array Control Unit PCB Indicators Figure 2–5 shows indicator locations on the array control unit (ACU) PCB. The 12 indicators on the ACU PCB are arranged in three groups of four (Figure 2–7).
  • Page 27 2.3 Indicators Table 2–3 ACU Indicators Indicator Function Power ON when the ACU PCB is powered Bus Grant ON when the ACU has VMEbus grant Microcode ON when a microcode interrupt is in progress Interrupt Any_Reg ON during a valid ACU access over the VMEbus DSVME Data strobe ASVME...

  • Page 28: Pe Array And Router Pcb Indicators

    2.3 Indicators 2.3.2.3 PE Array and Router PCB Indicators Each PE array PCB has eight indicators arranged into two 4-LED groups. The upper group provides status information about the PCB, and the lower bank displays the results of the global OR (GOR) for that PCB. Router PCBs have only the status indicators.

  • Page 29: Pvme Indicators

    2.3 Indicators 2.3.2.4 PVME Indicators The PVME PCB has 28 signal indicators, as shown in Figure 2–9. Table 2–5 lists the signal name and the signal abbreviation used on the PCB. When the indicator is ON (green), the signal is true. Figure 2–9 PVME Signal Indicators VAKI VAKO...

  • Page 30: Pvme Indicator Descriptions

    2.3 Indicators Table 2–5 PVME Indicator Descriptions Signal Abbreviation Description ON: +5 V power supply is ON AS1_ ON: VMEbus AS (address strobe) is true vmeDS ON: VMEbus DS (data strobe) is true DTACK_ ON: IOCTLR generated DTACK is true bIACK ON: VMEbus IACK (interrupt acknowledge) is true IACKCYC...

  • Page 31: Checking And Adjusting Dpu Power Supply

    Checking and Adjusting DPU Power Supply Chapter 3 describes how to measure and adjust power supply voltage levels. The data parallel unit (DPU) has four power supply output levels: +5 V, –5.2 V, +12 V, and –12 V. Measure these voltages at the DPU backplane, at the test points shown in Figure 3–1.

  • Page 32: Dpu Backplane Voltage Test Points

    Figure 3–1 DPU Backplane Voltage Test Points DECmpp 12000 Backplane IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15 AGND -12V +12V TERM -5.2V DECmpp 12000-LC Backplane IO15 IO15 IO15 IO15 IO15 IO15 IO15 IO15...

  • Page 33: Voltage Measurements And Adjustments

    3.1 Voltage Measurements and Adjustments 3.1 Voltage Measurements and Adjustments For all voltage measurements and adjustments: • Use a digital voltmeter to measure the supplies. • Measure the voltages at the points shown in Figure 3–1. • Use an insulated tool to make any adjustment. Note Adjust voltages only if they measure outside the tolerances specified in the following lists.

  • Page 34: Decmpp 12000 Power Supply Wiring And Voltage Adjustments

    3.1 Voltage Measurements and Adjustments Figure 3–2 DECmpp 12000 Power Supply Wiring and Voltage Adjustments Use an Insulated Tool Jumper +12V -12V Unused Caution: Overtightening the 12V wires can break BLACK BLACK the posts on the power supply. MKV-040000314-58-MPS 3–4 Checking and Adjusting DPU Power Supply...

  • Page 35: Decmpp 12000-Lc Hc Power Supply And Voltage Adjustments

    3.1 Voltage Measurements and Adjustments Figure 3–3 DECmpp 12000–LC HC Power Supply and Voltage Adjustments Fan Connector From System V1= +5V V2= -5V V3= +12V V4= -12V V3 Adj JUMPER V4 Adj V2 Adj V1 Adj Power Cable BLACK WHITE 115V 230V Figure 3–4 DECmpp 12000–LC Powertec Power Supply and Voltage...

  • Page 37: Cables, Connectors, And Auxiliary Pcbs

    Cables, Connectors, and Auxiliary PCBs Chapter 4 describes and identifies the connectors and cables in the DECmpp 12000/Sx system. It also describes PCBs that are not mounted in the data parallel unit (DPU) card cages. 4.1 Cables and Connectors DECmpp 12000 systems require a 30 A, 250 V twist lock connector on a dedicated circuit in the United States.

  • Page 38: Auxiliary Pcbs

    4.2 Auxiliary PCBs Figure 4–1 DPU-Server Cables Phone Line DECsystem 5900 Modem Internal Phone Cable 29-29373-01 Internal RS232 Cable 29-29566-01 External RS232 Cable 29-29564-01 Internal VME Data Cable External VME Front-End 29-29565-01 Data Cable 29-29563-01 Interface (MVIB) DECstation 5000/240 2T-T6000-AA Internal Cables Used on -LC Configuration Only External VME Data Cable External RS232 Cable...

  • Page 39: Using Diagnostic Software

    Using Diagnostic Software The DECmpp 12000/Sx contains diagnostics and related utility programs to test the array control unit (ACU) PCB, the processor element (PE) array PCBs, the PE array/router connections, the router PCB, EEPROMs, and memory. Appendix B provides reference pages for many of the diagnostics. Note Before running any DECmpp 12000/Sx diagnostics, make sure the front-end system is running correctly.

  • Page 40: Diagnostic Environment

    5.1 Diagnostic Environment 5.1 Diagnostic Environment The diagnostic programs run under the ULTRIX operating system, version 4.2, and reside in the directory $MP_PATH/field/bin 5.1.1 Running the Diagnostics To run a diagnostic test, enter the name of the test followed by a space and any desired option, and then press Return.

  • Page 41: Types Of Tests

    5.2 Types of Tests 5.2 Types of Tests DECmpp 12000/Sx diagnostics consist of two sets of programs: test suites and individual tests. 5.2.1 Test Suites The DECmpp 12000/Sx contains two test suites, . Run acu_diag pe_diag , then . The individual tests are described in Section 5.2.2. Total acu_diag pe_diag time for executing the full suite of diagnostics in a 4K PE system is approximately...

  • Page 42: Test Descriptions

    5.2 Types of Tests 5.2.2 Test Descriptions This section briefly describes the diagnostic and utility programs: • — ACU Boundary Test acu_bound Tests the ability of macro code to operate across page and row boundaries. • acu_clim Tests the action of the ACU when certain CMEM limits and alignments are violated.
  • Page 43 5.2 Types of Tests • Tests memory. To run , enter , a space, the type of memory you wish to test, and press Return. If you need to run more detailed tests with , you can get instructions by entering , and then pressing Return.
  • Page 44 5.2 Types of Tests • pe_diag This test suite checks the PE array PCBs and the backplane. The tests in the suite are listed in Section 5.2.1.2. • pe_func Tests various PE functions. • pe_macro Tests the instruction set. • pe_memdiag Tests PMem and reports the exact location of any errors found.

  • Page 45: Interpreting Log File Messages

    5.3 Interpreting Log File Messages 5.3 Interpreting Log File Messages Three logs provide useful information about the status of the DPU: • ./LOG • /usr/adm/dpujobmgr.log • /etc/uerf Many of these logs have references to , which is the Fault Code Word. Its fltcod value provides a clue to the cause of an error, as described in Table 5–1.

  • Page 46: The ./Log File

    5.3 Interpreting Log File Messages 5.3.1 The ./LOG File All diagnostic programs scroll output to the screen and copy it to the LOG file in the current directory (directory in which you executed diagnostics). If a LOG file already exists, diagnostic output is appended to it. If you do not have write-permission in the directory from which you are running the diagnostics, the LOG file is not changed.
  • Page 47 5.3 Interpreting Log File Messages The following list contains standard LOG file messages and brief explanations: • NOTE Provides information about the environment in which the test is running. It describes what the test is doing, so you understand the context if there is an error.

  • Page 48: The /Usr/Adm/Dpujobmgr.log File

    5.3 Interpreting Log File Messages 5.3.2 The /usr/adm/dpujobmgr.log File This file is a log of all the dpumanager daemon activity. This log reports background diagnostic errors, register status when errors are reported, and ACU kernel information. This log is especially helpful when you are trying to determine what might have caused a problem when a program aborts.
  • Page 49 5.3 Interpreting Log File Messages (dpu0) Wed Jul 22 18:24:32 1992 (@2) PE fault: PE number=0x1a (board 0, cluster 0,6, PE-in-cluster 0,2); error bits=0x2 ( ROUTER ) (dpu0) Wed Jul 22 18:24:32 1992 (@2) PE fault: PE number=0x19 (board 0, cluster 0,6, PE-in-cluster 0,1);...

  • Page 50: The /Etc/Uerf File

    5.3 Interpreting Log File Messages 5.3.3 The /etc/uerf File All errors are reported in this log. This is very helpful when the dpumanager is not running. To look at the log, enter the following commands: # cd /etc # uerf -R | more In the log examples below, Example 1 is a message from the DPU;...

  • Page 51: Removal And Replacement Procedures

    Removal and Replacement Procedures Chapter 6 describes how to remove and replace the following data parallel unit (DPU) components: • Array control unit (ACU) Printed Circuit Board (PCB) • Front-end VME interface PCB (T6000) • Processor element (PE) array PCB •...

  • Page 52: Decmpp 12000/Sx Card Cage Access

    6.1 Card Cage Access Figure 6–1 DECmpp 12000/Sx Card Cage Access Card Cage Fan Tray Power Supply MKV−040000314−59−RAGS 6–2 Removal and Replacement Procedures...

  • Page 53: Decmpp 12000-Lc/Sx Card Cage Access

    6.1 Card Cage Access Figure 6–2 DECmpp 12000–LC/Sx Card Cage Access Cardcage Fan Tray Power Supply Lower door (swings down) Removal and Replacement Procedures 6–3...

  • Page 54: Dpu Card Cage Slots

    6.2 DPU Card Cage Slots 6.2 DPU Card Cage Slots The DPU card cage is divided into two dedicated blocks: one for I/O PCBs and the other for PE array PCBs, as shown in Figure 6–3. The DECmpp 12000 supports the ACU, the VME interface PCB, 16 PE array PCBs, and 15 I/O PCBs. The DECmpp 12000–LC supports the ACU, the VME interface PCB, 4 PE array PCBs, and 5 I/O PCBs.

  • Page 55: Dpu Card Cage Slots

    6.2 DPU Card Cage Slots Figure 6–3 DPU Card Cage Slots Array Control Unit Input/Output Slots PE Array Slots Modem (USA Only) DECmpp 12000 Card Cage (Rear View) Modem (USA Only) I/O Slots PE Array Slots DECmpp 12000−LC Card Cage (Rear View) * Slot IO04 Reserved for Optional PDA Interface MKV−040000314−03−RAGS Removal and Replacement Procedures 6–5...

  • Page 56: Replacing Dpu Card Cage Pcbs

    6.3 Replacing DPU Card Cage PCBs 6.3 Replacing DPU Card Cage PCBs Warning To avoid personal injury or damage to equipment, make sure the system is turned off before replacing or adding any PC PCBs. 5 V power supplies deliver current in the 600 A range. Proper antistatic protection must be worn while servicing the DPU.

  • Page 57: Pcb Ejector Levers

    6.3 Replacing DPU Card Cage PCBs Figure 6–4 PCB Ejector Levers Ejector Levers MKV-040000314-37-MPS 9. With the ejector levers open (out), seat the PCB, and push the levers closed. Although you may have to push firmly to seat the PCB, do not force it. 10.

  • Page 58: Acu Jumpers

    6.3 Replacing DPU Card Cage PCBs Table 6–1 ACU Jumper Settings Jumper Function Factory Setting ACU VMEbus address 0xFCC000000 ACU VMEbus interrupt request level Level 1 ACU VMEbus interrupt acknowledge Level 1 level Independent scan path selection from the server (for diagnostics only) Selection of ACU as a VMEbus arbiter ACU VMEbus arbiter selected 16-bit or 32-bit word selection for ACU...

  • Page 59: Replacing Front-End Vme Interface Pcb

    6.3 Replacing DPU Card Cage PCBs 6.3.2 Replacing Front-End VME Interface PCB To replace the front-end VME interface PCB, follow these steps: 1. Turn off the system, as described in Chapter 1. 2. Open the DPU rear door. 3. Disconnect the 100-pin AMP connector on the PCB faceplate. 4.

  • Page 60: Replacing Pe Array And Router Pcbs

    6.3 Replacing DPU Card Cage PCBs 6.3.3 Replacing PE Array and Router PCBs To replace PE array or router PCBs, follow these steps: 1. Turn off the system, as described in Chapter 1. 2. Open the DPU rear door. 3. Loosen the captive screws at the top and bottom of the PCB faceplate. 4.

  • Page 61: Replacing Dpu Power Trays

    6.4 Replacing DPU Power Trays 6.4 Replacing DPU Power Trays This section contains instructions for removing and installing the DPU power trays. 6.4.1 Removing the DECmpp 12000/Sx Power Tray Caution It is important to label all cables as you disconnect them. Reinstalling cables with the wrong polarity can render the system inoperative.

  • Page 62: Decmpp 12000 Dpu Power Tray Rear

    6.4 Replacing DPU Power Trays Figure 6–6 DECmpp 12000 DPU Power Tray Rear Remote Daisy−chain Temperature Sensor DPU Interface PCA Fan Tray Power Selector Switch P1 P2 P13 Modem Power LEDs Backplane Sense Lines Lightpipe/ 1A Circuit Key Switch 30A Circuit Breaker Breaker Power Cable...

  • Page 63: Installing The Decmpp 12000/Sx Power Tray

    6.4 Replacing DPU Power Trays 6.4.2 Installing the DECmpp 12000/Sx Power Tray Follow these steps to install the power tray: 1. Gently slide the new power tray into place, feeding the AC power cord through the DPU rear skirt assembly. Again, make sure that the fan tray gasket does not get caught.

  • Page 64: Removing The Decmpp 12000-Lc/Sx Power Tray

    6.4 Replacing DPU Power Trays 6.4.3 Removing the DECmpp 12000–LC/Sx Power Tray Caution It is important to label all cables as you disconnect them. Reinstalling cables with the wrong polarity can render the system inoperative. Follow these steps to remove the power tray: 1.

  • Page 65: Installing The Decmpp 12000-Lc/Sx Power Tray

    6.4 Replacing DPU Power Trays 6.4.4 Installing the DECmpp 12000–LC/Sx Power Tray Take the following steps to install the power tray: 1. Slide the new power tray into place. 2. Lift the power supply cables out of the way and slide in the power tray. 3.

  • Page 66: Powertec Power Supply

    6.4 Replacing DPU Power Trays Figure 6–8 Powertec Power Supply Fan Connector +12V -12V JUMPER Caution: Overtightening the 12V wires can break the posts on the power supply. Table 6–2 Powertec Power Supply Wiring Voltage Value Wire Connection –5 V Black Ground from backplane –...

  • Page 67: Hc Power Supply

    6.4 Replacing DPU Power Trays Figure 6–9 HC Power Supply Fan Connector From System V1= +5V V2= -5V V3= +12V V4= -12V V3 Adj JUMPER V4 Adj V2 Adj V1 Adj Power Cable BLACK WHITE 115V 230V Table 6–3 HC Power Supply Wiring Connector Wire Connection...

  • Page 68: Replacing The Decmpp 12000/Sx Dpu Fan Tray

    6.5 Replacing the DECmpp 12000/Sx DPU Fan Tray 6.5 Replacing the DECmpp 12000/Sx DPU Fan Tray Take the following steps to replace the DECmpp 12000/Sx DPU fan tray: 1. Open the front and rear doors. 2. Turn off the DPU. Set the 30 A circuit breaker OFF, and disconnect the power cord from the power source.

  • Page 69: Replacing The Decmpp 12000-Lc/Sx Dpu Fan Tray

    6.6 Replacing the DECmpp 12000–LC/Sx DPU Fan Tray 6.6 Replacing the DECmpp 12000–LC/Sx DPU Fan Tray Take the following steps to replace the DECmpp 12000–LC/Sx DPU fan tray: 1. Turn off the system power, as described in Chapter 1. Set the 15 A circuit breaker to OFF (down), and unplug the power cord from the power source.

  • Page 70: Removing And Replacing The Lightpipe Pcb

    6.7 Removing and Replacing the Lightpipe PCB 6.7 Removing and Replacing the Lightpipe PCB The DECmpp 12000 and DECmpp 12000–LC DPUs use identical lightpipe PCBs. However, the bracketing and mounting locations are different and the method to access them differs somewhat. 6.7.1 DECmpp 12000/Sx Lightpipe In the DECmpp 12000 DPU, the lightpipe is mounted to the inside surface of the front door.

  • Page 71: Decmpp 12000-Lc/Sx Lightpipe

    6.7 Removing and Replacing the Lightpipe PCB 6.7.2 DECmpp 12000–LC/Sx Lightpipe In the DECmpp 12000–LC DPU, the top of the enclosure must be removed to access the lightpipe. Follow these steps to remove the top of the -LC DPU and replace the lightpipe.

  • Page 72: Removing The Decmpp 12000-Lc Enclosure Top

    6.7 Removing and Replacing the Lightpipe PCB Figure 6–10 Removing the DECmpp 12000–LC Enclosure Top MKV-040000314-60-MPS Figure 6–11 Replacing the Lightpipe PCB 6–22 Removal and Replacement Procedures...

  • Page 73: Backplane Jumpers And Upgrading Pe Arrays

    Backplane Jumpers and Upgrading PE Arrays Chapter 7 explains the various DPU backplane jumpers and describes how to add additional processor element (PE) array printed circuit boards (PCBs) for increased system performance. 7.1 DPU Backplane Jumpers To understand how to configure the backplane jumpers, you must understand the slot arrangement in the card cage.

  • Page 74: Dpu Card Cage Slots

    7.1 DPU Backplane Jumpers Figure 7–1 DPU Card Cage Slots Array Control Unit Input/Output Slots PE Array Slots Modem (USA Only) DECmpp 12000 Card Cage (Rear View) Modem (USA Only) I/O Slots PE Array Slots DECmpp 12000−LC Card Cage (Rear View) * Slot IO04 Reserved for Optional PDA Interface MKV−040000314−03−RAGS 7–2 Backplane Jumpers and Upgrading PE Arrays...

  • Page 75: Backplane Access

    7.1 DPU Backplane Jumpers 7.1.1 Backplane Access Backplane access is through the front of the DPU. DECmpp 12000 enclosures have a conventional front door which is opened by unlocking a 1/4-turn Allen head cap latch. DECmpp 12000–LC enclosures have three doors on the front of the DPU, as shown in Figure 7–2.

  • Page 76: Acu, Vmebus, And I/O Jumpers

    7.1 DPU Backplane Jumpers 7.1.2 ACU, VMEbus, and I/O Jumpers As shown in Figure 7–3, there are jumpers at the top of the backplane for the ACU, IO00 (MVIB), and each I/O slot (two shown). The jumpers over the ACU and IO00 slots should be installed exactly as shown.

  • Page 77: Decmpp 12000-Lc/Sx X-Net Jumper Configurations

    7.1 DPU Backplane Jumpers 7.1.3 X-Net Jumpers The X-Net jumpers control the X-Net connections between PE array PCBs. They are on the bottom of the backplane, beneath PE array slots 0 through 15 on DECmpp 12000 systems, and beneath slots 0 through 3 on DECmpp 12000–LC systems.

  • Page 78: Decmpp 12000/Sx X-Net Jumper Configurations

    7.1 DPU Backplane Jumpers Figure 7–5 DECmpp 12000/Sx X-Net Jumper Configurations 7–6 Backplane Jumpers and Upgrading PE Arrays...

  • Page 79: System Issues For Upgrades

    7.2 System Issues for Upgrades 7.2 System Issues for Upgrades Note Observe the following configuration rules: • Every DECmpp system must have the correct number of supported PE array PCBs. DECmpp 12000 systems may have 1, 2, 4, 8, or 16 PE array PCBs.

  • Page 80: Adding Processor Element Array Pcbs

    7.3 Adding Processor Element Array PCBs 7.3 Adding Processor Element Array PCBs Follow this procedure to add additional PE array PCBs. Refer to the guidelines in Section 6.3 for instructions on handling PCBs and Figure 7–1 for PCB placement in the DPU card cage. Caution Always wear antistatic straps.

  • Page 81: Reconfiguring Processor Element Array Pcbs

    7.4 Reconfiguring Processor Element Array PCBs 7.4 Reconfiguring Processor Element Array PCBs PE arrays can be downgraded so that a DECmpp system can be used with reduced performance while PE array spares are being acquired. However, this necessitates additional router PCBs because no PE array slot may be left unoccupied.

  • Page 83: Decmpp 12000/Sx Data Parallel Unit Rsl

    Recommended Spares List Table A–1 is a recommended spares listing (RSL) for the DECmpp 12000/Sx and DECmpp 12000–LC/Sx Series Data Parallel Units. Table A–1 DECmpp 12000/Sx Data Parallel Unit RSL DEC PN Vendor PN Description 29-29371-01 3400-0000-01 Array control unit PCB 29-29397-01 3400-0002-00 1K PE PCB w/16MB RAM...
  • Page 85 Data Parallel Unit Reference Pages This appendix contains the following Data Parallel Unit reference pages. • acu_ppdma(1) • mpconfig(1) • mpi(1) • mpq(1) • mpstat(1) • pe_arith(1) • pe_ckonet(1) • pe_diag(1) • pe_func(1) • pe_macro(1) • pe_memdiag(1) • pe_rtbp(1) • pe_rtdiag(1) •...

  • Page 86: Acu_Ppdma(1)

    acu_ppdma(1) acu_ppdma(1) — DECmpp Sx array control unit (ACU) Peek/Poke, DMA transfer test acu_ppdma Syntax acu_ppdma [-qtb] Description acu_ppdma command tests the ACU board’s ability to perform a DMA transfer between the front-end processor’s memory and PMem. It also exercises the peek /poke capability.

  • Page 87: Mpconfig(1)

    mpconfig(1) mpconfig(1) — DECmpp Sx data parallel unit (DPU) configuration information, mpconfig Version 1.1 Syntax mpconfig Description command prints out information about the DPU. This command mpconfig(1) can only be run from a machine attached to a DECmpp Sx DPU. The information generated is similar to the following: DECmpp Sx DPU Model MP-1204 (64 rows, 64 columns) Serial number: 0...

  • Page 88: Mpi(1)

    mpi(1) mpi(1) — DECmpp Sx data parallel unit (DPU) configuration information, network style, Version 1.1 Syntax mpi [ hostname ] Description command prints out information about all data parallel units (DPUs) on any attached local area network supporting SO_BROADCAST sockets and the broadcast address INADDR_BROADCAST.

  • Page 89: Mpq(1)

    mpq(1) mpq(1) — DECmpp Sx job queue examination program, Version 1.1 Syntax mpq [hostname] Description command examines the shared memory segment maintained by that contains the list of DECmpp Sx data parallel unit (DPU) dpumanager(8) jobs waiting for execution. When a host name is specified, information on that machine’s job queue is given.

  • Page 90: Mpstat(1)

    mpstat(1) mpstat(1) — Prints DECmpp Sx job accounting statistics, Version 1.1 mpstat Syntax mpstat [ options ] Description mpstat command examines, and optionally clears, the accounting file generated by the program. Depending on the options specified, it dpumanager(8) prints a list of all jobs run and/or a summary. Options Use this option to request a chronological list of all of the relevant jobs listed in the accounting file.
  • Page 91 mpstat(1) Files /usr/adm/dpuacct See Also dpumanager(8), mpq(1) Data Parallel Unit Reference Pages B–7...

  • Page 92: Pe_Arith(1)

    pe_arith(1) pe_arith(1) — DECmpp Sx processor element (PE) arithmetic operations test pe_arith Syntax pe_arith [-bqt] Description pe_arith command tests the operation of the arithmetic commands. Using peek/poke, the front-end program loads four buffers of data into each PE’s PMem: an 8-bit, 16-bit, 32-bit and 64-bit buffer. The front-end program starts the back-end program and gives it the op code and op size.

  • Page 93: Pe_Ckonet(1)

    pe_ckonet(1) pe_ckonet(1) — DECmpp Sx octagon net test pe_ckonet Syntax pe_ckonet [-qtb] Description pe_ckonet command tests the ability of processor elements (PE) to shift data using the xnet. The test takes a 32-bit pattern and does a zero distance 32-bit xnet move north, northeast, east, southeast, south, southwest, west, and finally northwest.

  • Page 94: Pe_Diag(1)

    pe_diag(1) pe_diag(1) — DECmpp Sx processor element (PE) board and backplane diagnostic pe_diag Syntax pe_diag [-qtb] Description pe_diag command performs the following diagnostics: 1. Serial Scan Tests (pe_scan) — Tests the serial scan chains on the array control unit (ACU) board, the PE board and the router boards: •...
  • Page 95 pe_diag(1) Options Use this option to specify the Burn-in test; runs the diagnostic repetitively, reporting the error count at the end of each pass. Use this option to select quick test; selects a brief version of some of the tests. Use this option to specify terse message style;...

  • Page 96: Pe_Func(1)

    pe_func(1) pe_func(1) — DECmpp Sx processor element (PE) function test pe_func Syntax pe_func [-t] Description pe_func command enables the entire array and has each PE perform the following functions: • div32: 0x12345678 / 1 = ? • mul64: 0x123456789abcdef0 * 0xfedcba9876543210 = ? •...

  • Page 97: Pe_Macro(1)

    pe_macro(1) pe_macro(1) — DECmpp 12000/Sx processor element (PE) board macro instruction pe_macro tests Syntax pe_macro [-qtb] Description command performs the following tests: pe_macro 1. Arithmetic and logic instruction tests • ortest1 — Global OR test • — E-bit operation test ebit1 •...
  • Page 98 pe_macro(1) • — MOV1: clear flag bits test (part 1) MoveTests4c • — MOV1: clear flag bits test (part 2) MoveTests4d • — MOV1: PReg to flag bit test MoveTests4e • MoveTests4f — MOV1: Immediate to PReg test • — MOV1UC: Flag to flag 1’s test (part 1) MoveTests5a •...
  • Page 99 pe_macro(1) 5. Router instruction tests • — 16-bit router send test rt0a • — 16-bit router fetch test rt0b • — Router send test (1, 8, 16, 32, 64 bits rt0c • rt0d — Router fetch test (1, 8, 16, 32, 64 bits) •...
  • Page 100 pe_macro(1) Sometimes the macro program sends data out the FRBEQ for awhile before halting. The front-end program reports which record it was waiting for when it timed out, and this information may prove useful. Individual Test Descriptions The following list describes the individual tests in alphabetical order: •...
  • Page 101 pe_macro(1) The test enables all the PEs. After each addition, the test performs a global OR of each PE’s answer. If it detects an error, the test prints an error message which gives the addition the test was attempting, the expected answer and the actual answer.
  • Page 102 pe_macro(1) The test starts by testing the ability to perform the AND1 function between the following sources and destinations: Destination Message Reference Each flag bit Message #1–#40 Each flag bit lflag Message #41–#80 Each flag bit cflag Message #81–#120 Each flag bit vflag Message #121–#160 Each flag bit...
  • Page 103 pe_macro(1) Carry flag Overflow flag Zero flag Negative flag MPP_FIG_276 • AndTests2 : Immediate To PReg AND Test (8, 16, 32 and 64 bit) — This test performs 8-bit, 16-bit, 32-bit, and 64-bit AND operations. After each AND, if it detects an error, the test prints an error message which gives the AND the test was attempting, the expected answer and the actual answer.
  • Page 104 pe_macro(1) • : ELSE1UC Instruction Test — The ELSE1UC instruction Else1ucTests complements the destination value, then ANDs the source with the destination, placing the results both in the destination and in lflag. This test uses the following bits as operands: Flag Bits PRegs 2[c4] —...
  • Page 105 pe_macro(1) Dest Init. Destination Message Reference Each flag bit Each PReg bit Message #423–#444 1025[c2] Each flag bit Message #445–#466 Each flag bit Each PReg bit Message #467–#488 After each ELSE1UC operation, it tests the lflag. If this is wrong, it prints an error message giving the expected and actual value of the flag.
  • Page 106 pe_macro(1) • : MOV1: Set Flag Bits Test (part 1) — This is a test of the MoveTests4a MOV1 instruction. It uses the following bits as operands: lflag cflag vflag zflag nflag tflag fflag rflag 64[c0] First, it tests that the MOV1 instruction can move an immediate 1 or 0 into each of the above flag bits, and that the lflag is correct after each move (message #1–#41).
  • Page 107 pe_macro(1) Destination Message Reference Each flag bit #61–#80 fflag Each flag bit #81–#100 rflag 64[c0] Each flag bit #101–#120 After each move, it checks that lflag is set properly. After moving into all of the flag bits, it checks that each was set properly. •...
  • Page 108 pe_macro(1) It successively moves a 0 from the source into each of the flag bits shown above. Destination Message Reference tflag Each flag bit #1–#20 fflag Each flag bit #21–#40 rflag Each flag bit #41–#60 64[c0] Each flag bit #61–#80 After each move, it checks that lflag is cleared properly.
  • Page 109 pe_macro(1) lflag cflag vflag zflag nflag tflag fflag rflag 64[c0] First, it tests that the MOV1UC instruction can move an immediate 1 or 0 into each of the above flag bits, and that the lflag is correct after each move (message #1–#41).
  • Page 110 pe_macro(1) Destination Message Reference rflag Each flag bit #41–#50 64[c0] Each flag bit #51–#60 After moving 1 into all of the flag bits, it checks that each was set properly. If the test detects an error, it prints an error message giving the operation, the expected result and the actual result.
  • Page 111 pe_macro(1) rflag 64[c0] It successively moves a 0 from the source into each of the flag bits in the list shown above. Destination Message Reference ~tsfag Each flag bit #1–#10 ~fflag Each flag bit #11–#20 ~rflag Each flag bit #21–#30 ~64[c0] Each flag bit #31–#40...
  • Page 112 pe_macro(1) Carry flag Overflow flag Zero flag Negative flag MPP_FIG_276 • OrTests2 : Immediate To Register OR Test — This test performs 8-bit, 16-bit, 32-bit and 64-bit OR operations. After each OR, if it detects an error, the test prints an error message which gives the OR the test was attempting, the expected answer and the actual answer.
  • Page 113 pe_macro(1) Test #7 (message #201–#240): This test uses the value in 128[c0] to determine how many places to shift the contents of acc. Test #8 (message #241–#260): This test uses the value 128[c0] = 7 to determine how many places to shift the contents of 16[c0]. Test #9 (message #261–#280): This test uses the contents of acc to determine how many places to shift the contents of 16[c0].
  • Page 114 pe_macro(1) • : 64-Bit Signed Integer DIVIDE Test — This test enables all the PEs, div1 then performs a series of 64-bit divisions. After each division, the test inverts all the bits of the answer and saves this separately. If an error occurs, the test prints an error message which gives the attempted division, the expected result, the actual result and whether or not this is the bit-inverted version of the answer.
  • Page 115 pe_macro(1) Exponent (in Fraction 1 Fraction 2 Fraction 3 excess of 1024) (Least Significant) Fraction 4 Sign bit (Most Significant) MPP_FIG_277 • msol0 : Brief Solitary LDSOL64/STSOL64 Test — This test enables a single PE per cluster for load/store operations. It performs a solitary 64-bit store and several solitary 64-bit load operations, and verifies that the data transfers correctly.
  • Page 116 pe_macro(1) • : LOAD/STORE Overlap Test — The purpose of this test is to mtest0 verify the ability to perform overlapping operations by overlapping store, multiplication and load operations. It is possible for the multiplication process to corrupt the load and store data; but it is much more likely that the process of loading and storing data upsets the multiplication process.
  • Page 117 pe_macro(1) • : Simple Indirectly Addressed LOAD/STORE Test — Performs a 64-bit, mtest3 32-bit, 16-bit and 8-bit indirectly addressed store followed by a similar set of indirectly addressed loads from the same locations. Checks the accuracy of the data. Repeats the above using different data. If an error occurs, the test prints an error message which gives the attempted operation, the expected result and the actual result.
  • Page 118 pe_macro(1) exclusive OR of the shifted result with the starting data. If no corruption occurred, the result is zero. The test begins with a distance of zero (shifts to itself), and successively widens the distance to a distance of 2047. If an error occurs with any PE, the test prints an error message which gives the distance shifted, the expected state of the error status bit and the actual state of the error status bit (which, of course, is 1 or the message would not...
  • Page 119 pe_macro(1) • : Router Send Test (1, 8, 16, 32, 64 Bits) — Sets the e-bit and the t-bit rt0c for PE 0,0 only. Opens the router channel (to itself) and sends data using the router. It performs 1-bit, 8-bit, 16-bit, 32-bit and 64-bit send operations. This test demonstrates not only that the data gets sent, but also that only the specified number of bits are sent.
  • Page 120 pe_macro(1) Message #11: The test attempts to send 0x8a using the command. rsend8 This word contains the low order bits of that operation. Message #12: This is the higher order bits of the destination. All these bits should remain zero. Message #13: The test attempts to fetch 0x8b using the rfetch8 command.
  • Page 121 pe_macro(1) Message #30: This displays the flag bits from the unselected PEs which should all remain at zero. Message #31: The test attempts to send 0x5a6a7a8a using the rsend32 command. This word contains the result of that operation. Message #32: This is the higher order bits of the destination. All these bits should remain zero.
  • Page 122 pe_macro(1) Message #50: This displays the flag bits from the unselected PEs which should all remain at zero. • : Router Send And Fetch (While Storing) Test — This test performs rt0f router send and fetch operations while the m-machine is busy doing 64-bit store operations.
  • Page 123 pe_macro(1) Message #14: This is the higher order bits of the destination. All these bits should remain zero. Message #15: Each cluster of 3 bits represents the state of the fflag, the rflag and the tflag after each stage of the test. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 After enable After ropen...
  • Page 124 pe_macro(1) Message #33: The test attempts to fetch 0x5b6b7b8b using the rfetch32 command. This word contains the result of that operation. The higher order bits should remain zero. Message #34: This is the higher order bits of the destination. All these bits should remain zero.
  • Page 125 pe_macro(1) also verifies that no data reaches disabled PEs, and none of their flags are affected. At each stage of the test, data and flags are checked. If an error occurs, the test prints an error message. This is the meaning of the expected and actual results mentioned in the following error messages: Message #1: The test attempts to open/send 0x8a using the rosend8...
  • Page 126 pe_macro(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Before rosend16 Unused After rosend16 Unused After rfetchc16 MPP_FIG_284 Messages #16–19: These words are comparable to words #11–14, except they are from the unselected PEs.
  • Page 127 pe_macro(1) Message #35: Each cluster of 3 bits represents the state of the fflag, the rflag and the tflag after each stage of the test. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Before...
  • Page 128 pe_macro(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Before ropen After ropen After rsend16 After rfetch16 After rclose MPP_FIG_289 Error message #4: This record is an exclusive OR of the correct flag bits with the flag bits as received in message #3.
  • Page 129 pe_macro(1) the PEs can be connected at any one time, so it takes 16 operations to complete. Error message #6: This is the exclusive OR comparison of the data sent over the router with the data received at the other end. 16 bits of data were sent using two rsend8 commands.
  • Page 130 pe_macro(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Before ropen After ropen After rsend16 After rfetch16 After rclose MPP_FIG_292 Error message #13: This is the number of operations before all PEs had completed their router transfer using the 32-bit commands.
  • Page 131 pe_macro(1) Error message #20: This is the exclusive OR comparison of the data fetched over the router with the data received. 64 bits of data were fetched using one command. Any bit set in this word indicates rfetch64 an erroneous bit in the data received. This word represents bits 0-31 of the 64-bit word.
  • Page 132 pe_macro(1) show the actual state of the flag bits, it only indicates which flags were in error. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Before rosend8 Unused After rosend8 Unused...
  • Page 133 pe_macro(1) Error message #11: This is the exclusive OR comparison of the data fetched over the router with the data received. 32 bits of data were fetched using one command. Any bit set in this word rfetchc32 indicates an erroneous bit in the data received. Error message #12: This is the exclusive OR comparison of the expected flag bits with the actual flag bits set during the rosend and the rfetchc operations.
  • Page 134 pe_macro(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Before rosend64 Unused After rosend64 Unused After rfetchc64 MPP_FIG_286 rt2c : Forward Router Send Test — This test asks each PE to make a router send transfer in the forward direction (to a PE whose address is higher).
  • Page 135 pe_macro(1) If the test detects an error, it prints an error message giving the router offset at which the error occurred, the nature of the error, the expected and actual result. : All PEs Send/Fetch To Self (m-machine busy) — In this test each rt2g PE uses the router to send to and fetch from itself at the same time that the m-machine is moving data from PReg to PMem.
  • Page 136 pe_macro(1) Error message #7: This is the exclusive OR comparison of the data fetched over the router with the data received. 16 bits of data were fetched using two commands. Any bit set in this word rfetch8 indicates an erroneous bit in the data received. Error message #8: This is the exclusive OR comparison of the expected flag bits with the actual flag bits set during the rsend and the rfetch operations.
  • Page 137 pe_macro(1) 1/16 of the PEs can be connected at any one time, so it takes 16 operations to complete. Error message #14: This is the exclusive OR comparison of the data sent over the router with the data received at the other end. 32 bits of data were sent using one rsend32 command.
  • Page 138 pe_macro(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Before ropen After ropen After rsend64 After rfetch64 After rclose MPP_FIG_294 sadd1 : Short ADD Test — This test enables all PEs, then moves two 32- bit numbers and their inverse into PRegs.
  • Page 139 pe_macro(1) The values returned in the error messages may be interpreted as follows: Error message #1–#159: Each word is a global OR of the data transferred to and from PMem by each PE. The sequence is: step 1: 0x00 --> 0[c1] step 2: 0x5a -->...
  • Page 140 pe_macro(1) Error word 2: Expected 0xffffffff. This number represents the last PMem byte offset the test accessed before ending. During the course of the test this number ranges between 0x3fff and 0x0. Error word 3: Expected 0x4f8. This number represents the last PReg base address the test accessed before ending.
  • Page 141 pe_macro(1) You can still glean some useful information because the front-end program indicates which message record it was waiting for when it timed out. This record number is the distance the test was attempting to shift data when the error occurred. This record number is also the row/column address of the PE which was attempting the shift.
  • Page 142 pe_macro(1) You can still glean some useful information because the front-end program indicates which message record it was waiting for when it timed out. This record number is the distance the test was attempting to shift data when the error occurred. This record number is also the row/column address of the PE which was attempting the shift.

  • Page 143: Pe_Memdiag(1)

    pe_memdiag(1) pe_memdiag(1) — DECmpp Sx indirect load/store tests pe_memdiag Syntax pe_memdiag [-bqt] Description pe_memdiag command loads and runs a back-end program which does the following operations: 1. Has each processor element (PE) do 1000 (hex) indirect stores followed by 1000 indirect loads; checks for error 2.

  • Page 144: Pe_Rtbp(1)

    pe_rtbp(1) pe_rtbp(1) — DECmpp Sx router backplane test pe_rtbp Syntax pe_rtbp [-qtb] [1100] Description pe_rtbp command tests various signal paths which pass between processor element (PE), backplane and router cards. When the test detects a failing path, it gives a complete report starting with the source board, chip and pin number, the signal name as shown on the schematic, the backplane connector and pin number, the destination board, backplane connector and pin number, and the destination chip and pin number.
  • Page 145 pe_rtbp(1) Files Executable binary: $MP_PATH/field/bin/pe_rtbp Data Parallel Unit Reference Pages B–61...

  • Page 146: Pe_Rtdiag(1)

    pe_rtdiag(1) pe_rtdiag(1) — DECmpp Sx processor element (PE) router diagnostic pe_rtdiag Syntax pe_rtdiag [-t] Description pe_rtdiag command uses a back-end program controlled by an HDB script. It performs three test routines: • Identity pattern: Using the router, each PE shifts data to itself •...

  • Page 147: Pe_Rtr(1)

    pe_rtr(1) pe_rtr(1) — DECmpp Sx processor element (PE) router diagnostic pe_rtr Syntax pe_rtr [-t] Description pe_rtr command uses a back-end program controlled by an HDB script. It shifts data and checks whether it is received. It has each PE keep its own error counter, which it polls at the end of the test (by peek/poking from HDB).

  • Page 148: Pe_Scan(1)

    pe_scan(1) pe_scan(1) — DECmpp Sx serial scan test pe_scan Syntax pe_scan [-qtb] Description pe_scan command tests the serial scan chains on the array control unit (ACU) board, the processor element (PE) board and the router boards: • ACU board Main scan chain EEPROM scan chain •...

  • Page 149: Dpumanager(8)

    dpumanager(8) dpumanager(8) — DECmpp Sx data parallel unit (DPU) job manager daemon, dpumanager Version 1.1 Syntax etc/dpumanager [ options ... ] Description The DECmpp Sx job manager daemon, , maintains the queue for data dpumanager parallel unit (DPU) jobs, determines which job has access to the DPU at any particular time, and ensures that the DPU state is properly initialized between jobs.
  • Page 150 dpumanager(8) machine, it must wait until it reaches the head of the queue before it is loaded into memory, and then it has exclusive access until it terminates. To get on the queue, it is necessary to make an call, DPUIOACCESS, to ioctl(2) the ACU driver.
  • Page 151 dpumanager(8) -maxtime t Use this option to specify a system maximum time limit (t), in seconds, for all jobs. -nodaemon Use this option to prevent the job manager from putting itself in background. -pmem k Use this option to specify the default amount of PE memory (in KB) that each job is assigned.

  • Page 152: Mpshutdown(8)

    mpshutdown(8) mpshutdown(8) — Terminates the DECmpp Sx data parallel unit (DPU) job manager, mpshutdown Version 1.1 Syntax etc/mpshutdown Description command sends a termination signal to the data parallel unit mpshutdown (DPU) job manager daemon, . When the job manager receives this dpumanager(8) signal, it should send a hangup signal to all pending DPU jobs and then exit.
  • Page 153 Index Commands acu_ppdma , B–2 dpumanager , B–65 ACU slot, 6–4 mpconfig , B–3 acu_bound, 5–4 , B–4 acu_clim, 5–4 , B–5 acu_diag, 5–4 mpshutdown , B–68 acu_int, 5–4 mpstat , B–6 acu_macro, 5–4 pe_arith , B–8 acu_micro, 5–4 pe_ckonet , B–9 acu_pgtbl, 5–4 pe_diag...
  • Page 154 Data parallel unit (cont’d) replacing front-end VME interface PCB, 6–9 replacing PCBs, 6–6 replacing PE array PCBs, 6–10 I/O jumpers, 7–4 replacing power tray, 6–11 I/O PCB slots replacing router PCBs, 6–10 DECmpp 12000, 1–1 Data parallel unit (-LC) DECmpp 12000–LC, 1–1 inner door, 7–3 I/O PCBs, 6–4 DECmpp 12000...
  • Page 155 mpstat command, B–6 Power system MPVMEbus jumpers, 7–4 replacing fan tray, 6–18 MVIB replacing fan tray (-LC), 6–19 indicator, 2–5 replacing power tray, 6–11 slot, 6–4 Power tray, 6–11 indicators, 2–9 Powerdown sequence, 1–6 Powerup sequence, 1–6 PCBs Powerup sequencer, 2–6 auxiliary, 4–2 Processor element array, 1–1 ejector levers, 6–6...
  • Page 156 Telephone connection cable, 4–1 replacing front-end VME interface PCB, 6–9 Terse mode, 5–2 VME interface PCBs, 6–4 VMEbus address ACU, 6–7 uerf , 5–12 VMEbus RESET, 2–5 Voltage measurement, 3–1 front-end interface, 6–4 X-Net jumpers, 7–5 Index–4...

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