Table Of Shared Memory Area - Panasonic FP2 -C1A Manual

Specifications
14.3

Table of Shared Memory Area

14.3 Table of Shared Memory Area
In the FP2 CPU unit with analog I/O, analog input unit, and analog output unit, in addition
to control of the analog input and output, shared memory that allows reading and writing
by the sequence program is stored.
14.3.1 Shared Memory of CPU Unit with Analog I/O
Address Descriptions
10 Preparation completion flag for analog input ch 0 to 3
16 No execution of conversion processing setting for analog input ch 0 to 3 H1111
18 Range setting for analog input ch 0 and 1
19 Range setting for analog input ch 2 and 3
22 Average times setting for analog input ch 0
23 Average times setting for analog input ch 1
24 Average times setting for analog input ch 2
25 Average times setting for analog input ch 3
30 Offset changing setting for analog input ch 0
31 Offset changing setting for analog input ch 1
32 Offset changing setting for analog input ch 2
Offset changing setting for analog input ch 3
33
38 Analog output hold setting
39 Analog output hold (any value) data setting
42 Broken wire detection flag for temperature sensor input (TC, R.T.D)
Notes
Shared memory addresses other than those listed above are
D
not used. Do not perform reading and writing with addresses
that are not used. And the addresses 10 and 42 cannot be
written to using a user program.
The shared memory addresses are all preset when the power
D
is turned from off to on (they return to the initial values).
Addresses 16, 22 to 25, 30 to 33, 38, and 39 can be written to
D
by the program as many times as desired when the mode is
changed from the PROG. mode to the RUN mode.
Addresses 10 and 42 cannot be written to using a user
D
program. Reading is possible all the time.
14 - 8
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FP2 Analog Unit
Initial value See section
H0000 14.4.1
14.4.2
HFFFF 14.4.3
HFFFF
K1 14.4.4
K1
K1
K1
K0 14.4.5
K0
K0
K0
H0000 14.5.1
K0000 14.5.2
H0000 14.4.6