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Table A-7 lists the delays in gross memory access time for several values of VDD
Clock to Address
Output Delay
VDD
IO
(V)
30 pF 60 pF 90 pF
3.3
6
1.8
18
The measurements are taken at the 50% points under the following conditions.
• T = -40°C to 85°C, V = VDD
• Internal clock to nonloaded CLK pin delay 1 ns @ 85°C/3.0 V
The clock to address output delays are similar, and apply to the following delays.
• T
, the clock to address delay
adr
• T
, the clock to memory chip select delay
CSx
• T
, the clock to I/O chip select delay
IOCSx
• T
, the clock to I/O read strobe delay
IORD
• T
, the clock to I/O write strobe delay
IOWR
• T
, the clock to I/O buffer enable delay
BUFEN
The data setup time delays are similar for both T
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is short-
ened (sometimes lengthened) by a maximum amount given in the table above. The shortening
takes place by shortening the high part of the clock. If the doubler is not enabled, then every clock
is shortened during the low part of the clock period. The maximum shortening for a pair of clocks
combined is shown in the table.
Technical Note TN227, Interfacing External I/O with Rabbit Microprocessor Designs, contains
suggestions for interfacing I/O devices to the Rabbit 4000 microprocessors.
User's Manual
Table A-7. Preliminary Data and Clock Delays
Data Setup
(ns)
Time Delay
(ns)
8
11
1
24
33
3
±10%
IO
Worst-Case
Spectrum Spreader Delay
0.5 ns setting
1 ns setting
no dbl / dbl
no dbl / dbl
2.3 / 2.3
3 / 4.5
7 / 6.5
and T
.
setup
hold
.
IO
(ns)
2 ns setting
no dbl / dbl
4.5 / 9
8 / 12
11 / 22
75
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