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Test Instructions Mono Board Sd5.31sl - Philips SD-5.31SL Service Manual

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5. Test Instructions Mono Board SD5.31SL

5.1
General
Impedance of measuring-equipment should be > 1MΩ.
Most tests have to be done by software commands.
Together with the software command you will find a Ref.#
nbr. This is the number of the diagnostic nulceus used for
this test. More detailed information can be find in the
chapter "Diagnostic Nuclei".
Levels: Most measurements are digital measurements.
The signal levels specification in this document are defined
in the chapter Technical Specifications.
All the waveforms measurement carried out in these test
instruction will be base on the testpoint indicated in the
Monoboard schematic diagram in the service manual.
5.2
General Start-up Measurements
5.2.1
Supply Check:
Table 5-1 Supply check
No
Testland
Signal Name
1
F810
2
F811
3
F813
The monoboard operates in power-off and power-on mode
only. There is no standby mode. In power-off mode, the
monoboard does not respond to any communication or signals.
Reset is via an internal reset circuit, which are tied to the +3V3
supply. To ensure proper power recycling, the following timing
should be observed:
+12V
+12V
0V
+12V
+12VSTBY
0V
+3.3V
+3.3V
0V
+5V
+5V
0V
3ms min
Internal
High
Reset
Low
50ms min
Modes:- Power-off
Reset mode
Figure 5-1 Timing chart
All tests that require the diagnostic software should be
performed in power-on mode only.
5.2.2
Reset Check:
To ensure a proper start-up of the monoboard, the back-end
reset signal SYS_RST is required at the ZIVA-5 input (testpoint
F501) after power-on.
To check the reset timing, measure the SYS_RST (testpoint
F501) and the +3V3ST supply (testpoint F503), reset circuit
trigger signal.
Test Instructions Mono Board SD5.31SL
DC Voltage (V)
Min
Typ
+3V3
3.15V
3.30V
3.50V
+5V
4.75V
5.00V
5.25V
+12V
10.0V
12.0V
13.2V
Operational mode
Standby mode
CL 36532043_044.eps
270503
ch1
ch2
NB: The SYS_RST rising edge,CH2, should be at least
100msec after the +3V3ST (refer to CH1 Figure Reset).
If the reset input does not go high then check the reset circuit
around IC7500.
Max
5.2.3
Clock Check
To check the correct functioning of the ZIVA, we first have to
check the presence of all clocks.
Table 5-2 Clock check
Test
No
land
1
F401
2
F209 ALI_CLK 33.6994 33.8688 34.0382
3
F421 DA_XCK 18.063
4
F502 SD_CLK 119.070 121.500 123.930
PM3380B
ch1
ch1
1
CH1 1.00V=
SD-5.31SL
PM3380B
T
1
2
CH1 1.00V=
CH2 1.00V=
MTB 500ms
4.96dv
Figure 5-2 Reset
Signal
Frequency (MHz)
name
Min
Typ
XTAL
13.4993 13.5000 13.5007
18.432
freq 18.5Mhz
MTB 20.0ns
Figure 5-3 DA_XCK
5.
EN 11
ch1+
CL 36532043_067.eps
030603
Descrip-
Max
tion
Back-end
clock
(± 50ppm)
Front-end
clock
(± 0.5%)
Audio
18.801
clock
SDRAM
clock
ch1+
CL 36532043_057.eps
030603

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