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Block Diagram and Testpoint Overview Bare Board
6. Block Diagram and Testpoint Overview Bare Board
Block Diagram
SD5.31 BLOCK DIAGRAM
OPU connector
1 TR-
2 TR+
MC34072
3 FO-
4 FO+
5 PDDVD
6 VCC
7 VR
8 GND
VC21
9 LDDVD
VC25
10 LDCD
PIN
VC21
11 VR
PI
12 GND
MEVO
13 PDCD
14 GND
Laser control
15 RFOUT
16 C
17 B
18 A
OPU
DVDLD
DVDLDO
connector
19 D
CDLD
CDLDO
20 F
21 E
22 VCC
23 VS
SP-3721A
24 GND
DVDMDI
CDMDI
A
B
C
D
E
F
RFOUT
SD-5.31SL
OUTSW
INSW
HOMESW
Tray connector
1 LD-
2 LD+
Slot
Motor
3 OUTSW
connector
connector
4 GND
5 INSW
H1+
H1-
A1
LD+
SL+
H2+
A2
LD-
SL-
H2-
A3
H3+
VH
H3-
TR+
TR-
Servo driver
Spindle motor driver
FO+
BA5954FP
BA6849FP
FO-
MVREF2
SFOCUS
SMOTOR
STRACK
SSPDON
TRAYSW
SFGIN
RFRP
SSLEG
SB
DRVSB
CEI
FEI
TEI
TEXI
SDFCT
SBAD
SEFGC
MIRR
ALi
SLDC
SCS
M5705
SDATA
SCLK
RFO
UPA[1:3]
UPD[0:15]
Power-on
HDMARQ
Clock
Reset
LDS
circuit
UDS
HDTACKn
HDMACK
ATAPIINTn
IDECS0n
IDECS1n
ATAPIRSTn
ATAPI connector
(for PCMCIA interface)
From Back-end Host
Front-End Engine
6.
31
Motor connector
1 SL-
2 SL+
3 GND
4 HOMESW
5 H+
6 H-
7 H3-
8 H3+
9 H2-
10 H2+
11 H1-
12 H1+
13 A1
14 A2
15 A3
Two SDRAM configuration option
MA[0:15]
A16
MD[0:7]
2x TSOP54 SDRAM
Flash / ROM
MFSCS
2pcs x 1M x 16 x 4 = 128Mbits
M29F002BT
MPSEN
MWR
Ext I2S Input
RA[0:11]
EDO DRAM
RD[0:15]
256K x 16
RRAS
SOJ40
RCAS
RWE
KAS161622D
ROE
Digital
audio
SPDIF - I2S
SPDIF
conv.
Input
Module interface bus
1M x 16 M29W160
Flash / ROM
2M Bytes
TSOP48
ATAPI connector
RESET 1 2 GND
DD7 3 4 DD8
DD6 5 6 DD9
ATAPI connector
UPA[1:22]
DD5 7 8 DD10
UPD[0:15]
DD4 9 10 DD11
SYSRSTn
DD3 11 12 DD12
UDS
DD2 13 14 DD13
FLASHCSn
DD1 15 16 DD14
DD0 17 18 DD15
UPA[1:3]
GND 19 20 NC
UPD[0:15]
DMARQ 21 22 GND
HDMARQ
Transparent latch
DIOWn 23 24 GND
LDS
74HCT573
DIORn 25 26 GND
UDS
74HCT573
IORDYn 27 28 NC
HDTACKn
74HCT573
DMACK 29 30 GND
HDMACK
INTRQ 31 32 NC
ATAPIINTn
DA1 33 34 NC
IDECS0n
DA0 35 36 DA2
IDECS1n
UPA[1:3]
CS0n 37 38 CS1n
ATAPIRSTn
UPD[0:15]
NC 39 40 GND
ALE
MA[0:11]
BA[0:1]
Host interface
ATAPI
MD[0:31]
MCS0n
MRASn
MCASn
SDRAM interface
MWEn
MCLK
LSI Logic
MDQM[0:3]
MCS1n
Ziva5+
Audio I2S input
XCLK
BCLK
LRCLK
MUX
Audio I2S output
GPIO
I2C
I2C
Analog
Digital
XCLK
Service and
(misc)
Master
Slave
video
audio
BCLK
diagnostic port
GPIO
MSCL
SCL
VDAC[0:4]
SPDIF
LRCLK
MSDA
SDA
ADATA[0:3]
I2C
INT.
MSCL
MSDA
DAC
(2/6 Ch)
64kbits
NVRAM
Analog Audio Out
Front-End Engine
ZK5 E-LINK connector
GND 1 2 +5V
MEDUSACSn 3 4 +5V
ZK5 E-LINK
ALE 5 6 SYSRSTn
connector
UPA2 7 8 UPA3
UPA15 9 10 UPA1
UPA13 11 12 UPD14
UPA11 13 14 UPD12
UPA[1:3]
UPA9 15 16 UPD10
UPD[0:15]
UPD8 17 18 GND
ALE
UPD6 19 20 UPD7
SYSRSTn
UPD4 21 22 UPD5
HDTACKn
UPD2 23 24 UPD3
MEDUSAINTn
UPD0 25 26 UPD1
UDS
MEDUSAINTn 27 28 DTACKn
LDS
LDS 29 30 UDS
RWn
RWn 31 32 GND
MEDUSACSn
E-LINK
Clock
circuit
SYSRSTn
Reset
circuit
I2S
KOK
A-D
Microphone
JTAG bus
Digital
Input
TRST
video
RTS1
TDO
VDATA(0:7)
RXD1
TDI
ITUT-656
TXD1
TMS
CTS1
TCK
CL 36532043_043.eps
030603
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