Circuit Descriptions, List of Abbreviations, and IC Data Sheets
Track Buffer Processor
An integrated Track Buffer Processor parses, frames, and
performs error processing on all DVD and CD sector types.
Flexible DVD Drive Interface
The DVD drive input of ZiVA-5 supports most serial stream and
parallel stream type drives, as well as EIDE (ATAPI) drives.
It incorporates a video encoder with five video DACs to provide
high-quality video. The video encoder supports PAL, NTSC,
RGB, SCART, interlaced 480i, and progressive 480p YPbPr
components, and is fully programmable for colour saturation,
contrast, brightness, and sharpness.
The video encoder is compliant with both MacroVision 7.1.L.1
for interlaced video (PAL, NTSC) and MacroVision AGC 1.03
for Progressive scan (480p). In addition to CSS, ZiVA-5
provides Copy Protection for Pre-recorded Media (CPPM),
Copy Protection for Recorded Media (CPRM), and audio
watermark detection, all of which are required for DVD-Audio.
It is fully compatible with DVD-Video, DVD-Audio, Chaoji-VCD
(CVD), SuperVCD, VCD, CD-DA, and CD-ROM formats such
On-chip peripherals include Inter-Device Communications
(IDC) master/slave interface, two standard UARTs, SPI, and a
direct multimode infrared (IR) input. All peripheral interfaces
can be configured as GPIO pins for added flexibility.
Input data comes via the ATAPI-bus. The front-end interface of
the ZiVA-5 accepts DVD, CD, and CD-DA information.
For video, the input data stream is decoded to the appropriate
MPEG, Sub Picture, and OSD data streams, after which they
are fed to the PAL/NTSC encoder. This cell will convert the
digital MPEG/Sub Picture/OSD stream into a standard base
band signal and into RGB components. It handles interlaced
and non-interlaced data, can perform CC/TXT encoding, and
allows MacroVision copy protection.
For audio, the processing cell is a fully compatible DTS, Dolby
Digital (AC-3), MPEG1, MPEG2, PCM decoder, capable of
decoding 5.1 and 2 channel streams.
The 2 MB flash memory (item 7501) is used to store the
application software. During normal operation, the application
is executed live from the (2 x 16 bit = 32 bit) SDRAM.
A 64 kb NVRAM (item 7400) is used to store the factory/user
settings. This memory is connected to the master I2C bus.
The audio interfaces available are I2S and S/PDIF for digital
audio output, and (optional) I2S karaoke microphone input.
The ZiVa-5 is capable of 2/6-channel PCM output. These
channels can be configured to output 5.1 Dolby Digital, DTS,
DA_DATA0 (pin 150): Down mixed left and right (LtRt).
DA_DATA1 (pin 151): Front left and right (LoRo).
DA_DATA2 (pin 154): Surround left and right (LsRs).
DA_DATA3 (pin 155): Centre and subwoofer (CSw)
The S/PDIF signal level (item 7402, pin 156, IEC_958) is
1Vp-p at module interface. To meet the complete S/PDIF
specifications, an external de-coupling circuit (item 7810,
diagram M8) is implemented.
This is a global audio mute, which blocks the final analogue
stage, and affects all channels simultaneously. The main
objective of this signal is to prevent switching noise at the audio
output as the player changes its mode of operation.
Apart from this global mute, additional audio (digital) mute is
applied to all stages of the audio path where possible. For
example, the decoder should apply digital mute to the audio
stream as and when needed. Note that the global mute does
not provide adequate attenuation to normal audio signals and
should not be used as an alternative to digital mute.
The MUTE pin must be set "high" immediately upon power-up
to avoid audible "plops". We can distinguish three states:
During normal operation. When the MUTE line is
activated (high), transistor 7600 will switch "on", biasing
7607, 7609, 7601, and 7603 to turn "on".
During initial power-up from standby. No mute signal
available, +5VSTBY will bias transistors 7607 and 7609 to
turn "on", which in turn switch "on" transistors 7601 and
During power off. No standby voltage available, the +5 V
across C1 and C2 will bias 7608 and 7615 to switch "on".
The digital output of the PAL/NTSC decoder is converted to the
analogue domain by on-chip DACs. The ZiVA-5 is capable of
5-channel analogue video. Three channels are in RGB/YUV
format (pins 125, 122, and 120), while the other two channels
are C and CVBS (pins 128 and 131). Table below shows the
multiplexed nature of the ZiVA-5 internal video DACs and the
jumper options on the PWB to cater for the different output
Table 9-1 Video DAC overview
DAC1 DAC2 DAC3 DAC4 DAC5
SCART Y/C CVBS
Via jumpers 4807, 4806, and 4816 selection is made for the
required video output on connector 1800. DACs that are not in
use are turned "off".
A video output buffer (see diagram M8) is implemented: a filter
stage (e.g. circuit around items 5801/ 5802 for CVBS) and a
drive stage (e.g. item 7800 for CVBS).
Miscellaneous I/O signals
Table 9-2 Chip select overview
E-Link daughter card
Pb (U) Pr (V)
Pb (U) Pr (V)
Ziva-5 Pin nr.