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9.
SD-5.31SL
•
Miscellaneous
Two SDRAM configuration option
2x TSOP54 SDRAM
2pcs x 1M x 16 x 4 = 128 Mbits
Audio I2S Input
Ext I2S input
Digital
audio
SPDIF - I2S
SPDIF
conv.
input
Module interface bus
DVD Back-end Host Processor
The SD5.31 is designed for the LSI-Logic ZiVA-5 family.
SDRAM (64/128Mbits)
SDRAM Controller
DVD Drive
Track Buffer
Decryption
Parallel/Serial
Processor
ZiVA
A/V Core
Audio
IDS Stereo In
Input Unit
Bus Interface Unit
UARTs
IR
ASYNC BUS
IDC
EIDE
GPIO
SPI
Figure 9-6 ZiVA-5 Block Diagram
Circuit Descriptions, List of Abbreviations, and IC Data Sheets
Flash/
ROM
1M x 16 M29W160
2M Bytes
TSOP48
UPA[1:22]
UPD[0:15]
SYSRSTn
UDS
FLASHCSn
Transparent Latch
74LVC573
74LVC573
74LVC573
UPA[1:3]
UPD[0:15]
ALE
MA[0:11]
BA[0:1]
Host interface
MD[0:31]
MCS0n
MRASn
MCASn
SDRAM interface
MWEn
MCLK
MDQM[0:3]
MCS1n
XCLK
BCLK
LRCLK
MUX
GPIO
I2C
(misc)
Master
GPIO
MSCL
MSDA
MSCL
MSDA
64 kbits
NV RAM
Figure 9-5 Block diagram back-end
CCIR 656
Digital Video
NTSC/PAL/480P
Multi-Plane
Video Encoder
2D
with
Five 10-bit
Graphics
TrueScan
Video
Engine
De-Interfacer
DACs
IEC958/1937
32-bit SPARC
Audio
Microprocessor
Output
LPCM 8-ch
+Audio DSP
Unit
Audio Out
Phase
JTAG
Lock
Interface
Loop
13.5 MHz Crystal
CL36532043_013.eps
(*byte swapped)
ATAPI connector
RESET
1
2
GND
3
4
DD8
DD7
5
6
DD9
DD6
ATAPI connector
7
8
DD10
DD5
9
10
DD11
DD4
11
12
DD12
DD3
13
14
DD13
DD2
DD1
15
16
DD14
UPA[1:3]
17
18
DD15
DD0
UPD[0:15]
19
20
NC
GND
HDTACKn
21
22
GND
DMARQ
23
24
GND
DIOWn
25
26
DIORn
GND
HDMACK
27
28
NC
IORDYn
HDMARQ
DMACK
29
30
GND
ATAPIINTn
31
32
NC
INTRQ
IDECS0n
33
34
NC
DA1
IDECS1n
35
36
DA2
DA0
ATAPIRSTn
37
38
CS1n
CS0n
NC
39
40
GND
ATAPI
LSI Logic
ZiVA 5+
Audio I2S output
Analog
Digital
XCLK
I2C
video
audio
BCLK
Slave
VDAC[0:4]
SPDIF
LRCLCK
SCL
ADATA[0:3]
SDA
I2C
INT
DAC
(2/6 Ch)
Analog Audio Out
Some of the DVD related features of this IC are:
•
Video decoder supports MPEG1 and MPEG2
•
Audio decoder supports AC-3, MPEG1, MPEG2, DTS,
PCM, S/PDIF, and MP3.
•
PAL/NTSC video encoder with simultaneously Y/C, CVBS
and RGB/YUV outputs
•
The video encoder supports Closed Caption and allows
MacroVision 7.0/6.1
Composite
•
Y/R
Full screen On Screen Display (OSD) generator
C
Cr/Pr/G
•
On-chip PLLs to generate all necessary clocks (as
Cb/Pb/B
reference a 13.5 MHz xtal is used).
CPU
The ZiVA-5 incorporates a 32-bit SPARC host CPU for audio
processing and special features. The SPARC CPU is designed
to act as the system host processor (thus removing the
requirement for an external host CPU with associated
memory).
150503
ZK5 E-LINK connector
ZK5 E-LINK
connector
MEDUSACSn
UPA[1:3]
UPD[0:15]
LDS
ALE
UDS
SYSRSTn
HDTACKn
MEDUSAINTn
MEDUSAIONTn
UDS
LDS
RWn
MEDUSACSn
E-LINK
SYSRSTn
I2S
Service and JTAG bus Digital
Digagnostic port
Digital
video
RST1
TDO
VDATA(0:7)
RXD1
TDI
ITUT -656
TXD1
TMS
CTS1
TCK
CL 36532043_010.eps
1
2
+5V
GND
3
4
+5V
5
6
SYSRSTn
ALE
UPA2
7
8
UPA3
9
10
UPA1
UPA15
11
12
UPD14
UPA13
13
14
UPD12
UPA11
15
16
UPD10
UPA9
UPD8
17
18
GND
19
20
UPD7
UPD6
UPD4
21
22
UPD5
23
24
UPD3
UPD2
25
26
UPD1
UPD0
27
28
DTACKn
29
30
UDS
LDS
RWn
31
32
GNG
Clock
circuit
Reset
Circuit
KOK
A-D
Microphone
input
190503
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