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Advanced Chipset Features - Acer Aspire X1301 Service Manual

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Advanced Chipset Features

Parameter
Hyper SLI
iGPU Frame Buffer Control
Frame Buffer Size
CPU Frequency
KB<->NB HT Speed
KB<->NB HT Width
PCIE Clock
DRAM Configuration
CPU Spread Spectrum
PCIE Spread Spectrum
SATA Spread Spectrum
Chapter 2
Description
Enable or disable the Scalable Link Interface (SLI) technology.
When set to auto, BIOS will automatically setup the frame buffer size.
When set to manual, you can set the frame buffer size. Frame buffer
size is the total amount of system memory allocated solely for the
onboard graphics controller.
This parameter can be configured if the iGPU Frame Buffer Control is
set to Manual.
Sets processor minimum and maximum frequency.
Controls the physical speed of the processor to the Northbridge HT link.
Controls the processor to the Northbridge link bandwidth.
Sets the PCI Express clock frequency.
Press Enter to configure memory timing and operation settings.
Allows you to reduce the EMI of the front side bus by modulating the
signals it generates so that the spikes are reduced to flatter curves.
Allows you to reduce the EMI of the PCI Express bus by modulating the
signals it generates so that the spikes are reduced to flatter curves.
When set to down spread, the chipset modulates the PCI Express bus'
baseline signal downwards by a small amount.
When set to disabled, the chipset disables any modulation of the PCI
Express bus' baseline signal.
Allows you to reduce the EMI of the SATA bus by modulating the
signals it generates so that the spikes are reduced to flatter curves.
When set to down spread, the chipset modulates the SATA bus'
baseline signal downwards by a small amount.
When set to disabled, the chipset disables any modulation of the SATA
bus' baseline signal.
Option
Disabled
Enabled
Auto
Manual
64, 16, 32, 128,
256 MB
200
Minimum 100
Maximum 500
Auto
200, 400, 600, 800
MHz, 1 GHz
Auto
Up 8/16
Down 8/16
100
Minimum 100
Maximum 200
Disabled
-0.5%, 1.0%
Disabled
Down Spread
Disabled
Down Spread
17

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