Table of Contents
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SERVICE MANUAL
CGMS, Teletext, WSS, VPS and close caption
• On-Chip Peripherals
4 ASCs (UARTS)
4 parallel 8-bit I/O banks
2 smartcard interfaces and clock generators
3 SSCs for I²C/SPI master/slave interfaces
Silicon Labs line side (DAA) interface
High-speed USB OHCI/EHCI compliant host interface
DiSEqC interface
3. Architecture overview
The figure below shows the architecture of the Sti5100.
This chapter gives a brief overview of each of the functional blocks of the STi5100.
4. STi5100 functional modules
4.1 Memory subsystem
Page 6
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