Ddram Hynix 512Mbits - Hitachi HDR081 Service Manual

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The HY5DU12422C(L)TP, HY5DU12822C(L)TP and HY5DU121622C(L)TP are a 536,870,912-bit
CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications
which requires large memory density This Hynix 512Mb DDR SDRAMs offer fully synchronous
operations referenced to both rising and falling edges of the clock. While all addresses and control inputs
are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data
masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and
2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with
• VDD, VDDQ = 2.5V ± 0.2V for DDR200, 266, 333
VDD, VDDQ = 2.6V ± 0.1V for DDR400
• All inputs and outputs are compatible with SSTL_2
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
• On chip DLL align DQ and DQS transition with CK
• DM mask write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 2/2.5 (DDR200, 266,
333) and 3 (DDR400) supported
• Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed /RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 8192 refresh cycles / 64ms
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