Renesas R5F5630ACDLC Manuals

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Renesas R5F5630ACDLC User Manual

Renesas R5F5630ACDLC User Manual (1654 pages)

32-Bit MCU RX Family / RX600 Series RX630 Group

Brand: Renesas | Category: Microcontrollers | Size: 14.99 MB

Table of Contents

Table of Contents
8
Overview
47
Outline of Specifications
47
List of Products
53
Block Diagram
56
Pin Functions
57
Pin Assignments
62
Cpu
97
Features
97
Register Set of the CPU
98
General-Purpose Registers (R0 to R15)
99
Control Registers
99
Interrupt Stack Pointer (Isp)/User Stack Pointer (USP)
99
Interrupt Table Register (INTB)
99
Program Counter (PC)
100
Processor Status Word (PSW)
100
Backup PC (BPC)
101
Backup PSW (BPSW)
102
Fast Interrupt Vector Register (FINTV)
102
Floating-Point Status Word (FPSW)
102
Register Associated with DSP Instructions
105
Accumulator (ACC)
105
Processor Mode
105
Supervisor Mode
105
User Mode
105
Privileged Instruction
105
Switching between Processor Modes
106
Data Types
106
Endian
107
Switching the Endian
107
Access to I/O Registers
110
Notes on Access to I/O Registers
110
Data Arrangement
111
Data Arrangement in Registers
111
Data Arrangement in Memory
111
Notes on the Allocation of Instruction Codes
111
Vector Table
112
Fixed Vector Table
112
Relocatable Vector Table
112
Operation of Instructions
113
Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions
113
Pipeline
113
Overview
113
Instructions and Pipeline Processing
115
Instructions Converted into Single Micro-Operation and Pipeline Processing
115
Instructions Converted into Multiple Micro-Operations and Pipeline Processing
117
Pipeline Basic Operation
120
Calculation of the Instruction Processing Time
122
Numbers of Cycles for Response to Interrupts
122
Operating Modes
123
Operating Mode Types and Selection
123
Register Descriptions
124
Mode Monitor Register (MDMONR)
124
Mode Status Register (MDSR)
124
System Control Register 0 (SYSCR0)
125
System Control Register 1 (SYSCR1)
126
Details of Operating Modes
127
Single-Chip Mode
127
On-Chip ROM Enabled Extended Mode
127
On-Chip ROM Disabled Extended Mode
127
Boot Mode
127
USB Boot Mode
127
User Boot Mode
127
Transitions of Operating Modes
129
Operating Mode Transitions Determined by the Mode-Setting Pins
129
Operating Mode Transitions According to Register Setting
130
Address Space
131
External Address Space
133
I/O Registers
134
I/O Register Addresses (Address Order)
136
Resets
178
Overview
178
Register Descriptions
181
Reset Status Register 0 (RSTSR0)
181
Reset Status Register 1 (RSTSR1)
183
Reset Status Register 2 (RSTSR2)
183
Software Reset Register (SWRR)
184
Operation
185
RES# Pin Reset
185
Power-On Reset and Voltage Monitoring 0 Reset
185
Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset
186
Deep Software Standby Reset
188
Independent Watchdog Timer Reset
188
Watchdog Timer Reset
188
Software Reset
188
Determination of Cold/Warm Start
189
Determination of Reset Generation Source
190
Option-Setting Memory
191
Overview
191
Register Descriptions
192
Option Function Select Register 0 (OFS0)
192
Option Function Select Register 1 (OFS1)
196
Endian Select Register B (MDEB), Endian Select Register S (MDES)
197
UB Codes
198
UB Code a
198
UB Code B
198
Usage Note
198
Setting Example of Option-Setting Memory
198
Voltage Detection Circuit (LVDA)
199
Overview
199
Register Descriptions
202
Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1)
202
Voltage Monitoring 1 Circuit Status Register (LVD1SR)
202
Voltage Monitoring 2 Circuit Control Register 1 (LVD2CR1)
203
Voltage Monitoring 2 Circuit Status Register (LVD2SR)
203
Voltage Monitoring Circuit Control Register (LVCMPCR)
204
Voltage Detection Level Select Register (LVDLVLR)
204
Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0)
205
Voltage Monitoring 2 Circuit Control Register 0 (LVD2CR0)
206
VCC Input Voltage Monitor
208
Monitoring Vdet0
208
Monitoring Vdet1
208
Monitoring Vdet2
208
Reset from Voltage Monitor 0
209
Interrupt and Reset from Voltage Monitor 1
210
Interrupt and Reset from Voltage Monitor 2
212
Clock Generation Circuit
214
Overview
214
Register Descriptions
216
System Clock Control Register (SCKCR)
216
System Clock Control Register 2 (SCKCR2)
218
System Clock Control Register 3 (SCKCR3)
219
PLL Control Register (PLLCR)
220
PLL Control Register 2 (PLLCR2)
221
External Bus Clock Control Register (BCKCR)
222
Main Clock Oscillator Control Register (MOSCCR)
223
Sub-Clock Oscillator Control Register (SOSCCR)
224
Low-Speed On-Chip Oscillator Control Register (LOCOCR)
225
IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR)
226
High-Speed On-Chip Oscillator Control Register (HOCOCR)
227
Oscillation Stop Detection Control Register (OSTDCR)
228
Oscillation Stop Detection Status Register (OSTDSR)
229
Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
230
High-Speed On-Chip Oscillator Power Supply Control Register (HOCOPCR)
231
Main Clock Oscillator
231
Connecting a Crystal Resonator
231
External Clock Input
233
Notes on the External Clock Input
233
Sub-Clock Oscillator
233
Connecting 32.768-Khz Crystal Resonator
233
Handling of Pins When Sub-Clock Is Not Used
234
Oscillation Stop Detection Function
235
Oscillation Stop Detection and Operation after Detection
235
Oscillation Stop Detection Interrupts
236
PLL Circuit
237
Internal Clock
237
System Clock
237
Peripheral Module Clock
237
Flashif Clock
237
External Bus Clock
237
USB Clock
238
CAN Clock
238
IEBUS Clock
238
RTC-Dedicated Clock
238
IWDT-Dedicated Clock
238
JTAG Clock
238
Pin Settings When an Oscillator Is Connected
239
Pin Settings When an External Clock Is Connected
239
Usage Notes
239
Notes on Clock Generation Circuit
239
Notes on Resonator
239
Notes on Board Design
239
Notes on Resonator Connect Pin
240
Notes on Sub-Clock Oscillator
240
Frequency Measurement Circuit (MCK)
242
Overview
242
Register Descriptions
245
Counter-Clock Extension Register N (Sckn) (N = 1, 2)
245
Operation
246
Usage Notes
248
Setting the Module-Stop Control Registers
248
Low Power Consumption
249
Overview
249
Register Descriptions
252
Standby Control Register (SBYCR)
252
Module Stop Control Register a (MSTPCRA)
253
Module Stop Control Register B (MSTPCRB)
254
Module Stop Control Register C (MSTPCRC)
256
Operating Power Control Register (OPCCR)
257
Sleep Mode Return Clock Source Switching Register (RSTCKCR)
259
Main Clock Oscillator Wait Control Register (MOSCWTCR)
260
Sub-Clock Oscillator Wait Control Register (SOSCWTCR)
261
PLL Wait Control Register (PLLWTCR)
263
Deep Standby Control Register (DPSBYCR)
265
Deep Standby Interrupt Enable Register 0 (DPSIER0)
267
Deep Standby Interrupt Enable Register 1 (DPSIER1)
268
Deep Standby Interrupt Enable Register 2 (DPSIER2)
269
Deep Standby Interrupt Enable Register 3 (DPSIER3)
270
Deep Standby Interrupt Flag Register 0 (DPSIFR0)
271
Deep Standby Interrupt Flag Register 1 (DPSIFR1)
272
Deep Standby Interrupt Flag Register 2 (DPSIFR2)
273
Deep Standby Interrupt Flag Register 3 (DPSIFR3)
275
Deep Standby Interrupt Edge Register 0 (DPSIEGR0)
276
Deep Standby Interrupt Edge Register 1 (DPSIEGR1)
277
Deep Standby Interrupt Edge Register 2 (DPSIEGR2)
278
Deep Standby Interrupt Edge Register 3 (DPSIEGR3)
278
Deep Standby Backup Register (Dpsbkry) (y = 0 to 31)
279
Reducing Power Consumption by Switching Clock Signals
279
Module-Stop Function
279
Function for Lower Operating Power Consumption
280
Setting Operating Power Consumption Control Mode
280
Low Power Consumption Modes
281
Sleep Mode
281
Transition to Sleep Mode
281
Canceling Sleep Mode
281
Sleep Mode Return Clock Source Switching Function
282
All-Module Clock Stop Mode
282
Transition to All-Module Clock Stop Mode
282
Canceling All-Module Clock Stop Mode
283
Software Standby Mode
283
Transition to Software Standby Mode
283
Canceling Software Standby Mode
284
Example of Software Standby Mode Application
285
Deep Software Standby Mode
286
Transition to Deep Software Standby Mode
286
Canceling Deep Software Standby Mode
287
Pin States When Deep Software Standby Mode Is Canceled
287
Example of Deep Software Standby Mode Application
288
Flowchart to Use Deep Software Standby Mode
289
Usage Notes
290
I/O Port States
290
Module-Stop State of DMAC and DTC
290
On-Chip Peripheral Module Interrupts
290
Write Access to MSTPCRA, MSTPCRB, and MSTPCRC
290
Input Buffer Control by Dirqne Bit (N = 0 to 15)
290
Timing of Wait Instructions
290
Rewrite the Register by DMAC and DTC in Sleep Mode
290
Transition to Software Standby Mode for Products with 1.5-Mbyte ROM or more or Products with 176 Pins or more
290
Canceling All-Module Clock Stop Mode
291
Point for Caution When Using the Sub-Clock as the Source of the System Clock
291
Points for Caution on Return from Software Standby
291
Point for Caution When Shifting from Low-Speed Operation Mode to Software Standby Mode
291
Battery Backup Function
292
Overview
292
Operation
293
Battery Backup Function
293
Usage Notes
294
Register Write Protection Function
295
Register Descriptions
296
Protect Register (PRCR)
296
Exception Handling
297
Exception Events
297
Undefined Instruction Exception
297
Privileged Instruction Exception
297
Access Exceptions
297
Floating-Point Exception
297
Reset
297
Non-Maskable Interrupt
298
Interrupt
298
Unconditional Trap
298
Exception Handling Procedure
299
Acceptance of Exception Events
300
Acceptance Timing and Saved PC Value
300
Vector and Site for Saving the Values in the PC and PSW
301
Hardware Processing for Accepting and Returning from Exceptions
301
Hardware Pre-Processing
302
Undefined Instruction Exception
302
Privileged Instruction Exception
302
Access Exceptions
302
Floating-Point Exception
302
Reset
303
Non-Maskable Interrupt
303
Interrupt
303
Unconditional Trap
303
Return from Exception Handling Routine
304
Priority of Exception Events
304
Interrupt Controller (Icub)
305
Overview
305
Register Descriptions
307
Interrupt Request Register N (Irn) (N = Interrupt Vector Number)
307
Interrupt Request Enable Register M (Ierm) (M = 02H to 1Fh)
308
Interrupt Source Priority Register N (Iprn) (N = 000 to 253)
309
Fast Interrupt Set Register (FIR)
310
Software Interrupt Activation Register (SWINTR)
311
DTC Activation Enable Register N (Dtcern) (N = Interrupt Vector Number)
311
DMAC Activation Request Select Register M (Dmrsrm) (M = DMAC Channel Number)
312
IRQ Control Register I (Irqcri) (I = 0 to 15)
313
IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)
314
IRQ Pin Digital Filter Enable Register 1 (IRQFLTE1)
315
IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0)
316
IRQ Pin Digital Filter Setting Register 1 (IRQFLTC1)
317
Non-Maskable Interrupt Status Register (NMISR)
318
Non-Maskable Interrupt Enable Register (NMIER)
320
Non-Maskable Interrupt Status Clear Register (NMICLR)
321
NMI Pin Interrupt Control Register (NMICR)
322
NMI Pin Digital Filter Enable Register (NMIFLTE)
322
NMI Pin Digital Filter Setting Register (NMIFLTC)
323
Group M Interrupt Source Register (Grpm) (M: Group Number)
324
Group M Interrupt Enable Register (Genm) (M = Group Number)
327
Group M Interrupt Clear Register (Gcrm) (M = Group Number)
329
Unit Selecting Register (SEL)
330
Vector Table
331
Interrupt Vector Table
331
Fast Interrupt Vector Table
338
Non-Maskable Interrupt Vector Table
338
Peripheral Module Interrupt Request Groups and Unit Selection
338
Interrupt Request Groups
338
Unit Selection
340
Interrupt Operation
341
Detecting Interrupts
341
Operation of Status Flags for Edge-Detected Interrupts
342
Operation of Status Flags for Level-Detected Interrupts
344
Edge Detection Group Interrupts and Interrupt Status Flags
345
Level Detection Group Interrupts and Interrupt Status Flags
347
Unit Selection and Interrupt Status Flags
348
Enabling and Disabling Interrupt Sources
349
Selecting Interrupt Request Destinations
350
Determining Priority
351
Fast Interrupt
352
Digital Filter
352
External Pin Interrupts
353
Non-Maskable Interrupt Operation
353
Return from Power-Down States
354
Return from Sleep Mode
354
Return from All-Module Clock Stop Mode
354
Return from Software Standby Mode
355
Usage Note
355
Note on WAIT Instruction Used with Non-Maskable Interrupt
355
Buses
356
Overview
356
Description of Buses
358
CPU Buses
358
Memory Buses
358
Internal Main Buses
359
Internal Peripheral Buses
359
Write Buffer Function (Internal Peripheral Bus)
360
External Bus
361
Parallel Operation
363
Bus Settings
363
Restrictions
363
Register Descriptions
364
Csn Control Register (Csncr) (N = 0 to 7)
364
Csn Recovery Cycle Register (Csnrec) (N = 0 to 7)
365
CS Recovery Cycle Insertion Enable Register (CSRECEN)
367
Csn Mode Register (Csnmod) (N = 0 to 7)
369
Csn Wait Control Register 1 (Csnwcr1) (N = 0 to 7)
371
Csn Wait Control Register 2 (Csnwcr2) (N = 0 to 7)
374
Bus Error Status Clear Register (BERCLR)
377
Bus Error Monitoring Enable Register (BEREN)
377
Bus Error Status Register 1 (BERSR1)
378
Bus Error Status Register 2 (BERSR2)
378
Bus Priority Control Register (BUSPRI)
379
Endian and Data Alignment
381
Data Alignment Control for CS Area
381
Operation of CS Area Controller
387
Separate Bus
387
Address/Data Multiplexed Bus
402
External Wait Function
405
Insertion of Recovery Cycles
407
No Access State
410
Write Buffer Function (External Bus)
411
Limitations
411
Bus Error Monitoring Section
413
Types of Bus Error
413
Illegal Address Access
413
Timeout
413
Operations When a Bus Error Occurs
413
Conditions Leading to Bus Errors
414
Memory-Protection Unit (MPU)
415
Overview
415
Types of Access Control
417
Regions for Access Control
417
Background Region
417
Overlap between Regions
417
Instructions and Data that Span Regions
417
Register Descriptions
418
Region-N Start Page Number Register (Rspagen) (N = 0 to 7)
418
Region-N End Page Number Register (Repagen) (N = 0 to 7)
419
Memory-Protection Enable Register (MPEN)
420
Background Access Control Register (MPBAC)
421
Memory-Protection Error Status-Clearing Register (MPECLR)
422
Memory-Protection Error Status Register (MPESTS)
423
Data Memory-Protection Error Address Register (MPDEA)
424
Region Search Address Register (MPSA)
424
Region Search Operation Register (MPOPS)
425
Region Invalidation Operation Register (MPOPI)
425
Instruction-Hit Region Register (MHITI)
426
Data-Hit Region Register (MHITD)
427
Functions
429
Memory Protection
429
Region Search
429
Protection of Registers Related to the Memory-Protection Unit
429
Flow for Determination of Access by the Memory-Protection Function
430
Procedures for Using Memory Protection
432
Setting Access-Control Information
432
Enabling Memory Protection
432
Transition to User Mode
432
Processing in Response to Memory-Protection Errors
432
DMA Controller (DMACA)
434
Overview
434
Register Descriptions
436
DMA Source Address Register (DMSAR)
436
DMA Destination Address Register (DMDAR)
436
DMA Transfer Count Register (DMCRA)
437
DMA Block Transfer Count Register (DMCRB)
438
DMA Transfer Mode Register (DMTMD)
439
DMA Interrupt Setting Register (DMINT)
440
DMA Address Mode Register (DMAMD)
442
DMA Offset Register (DMOFR)
445
DMA Transfer Enable Register (DMCNT)
445
DMA Software Start Register (DMREQ)
446
DMA Status Register (DMSTS)
447
DMA Activation Source Flag Control Register (DMCSL)
448
DMACA Module Activation Register (DMAST)
449
Operation
450
Transfer Mode
450
Extended Repeat Area Function
454
Address Update Function Using Offset
456
Activation Sources
460
Operation Timing
461
DMAC Execution Cycles
462
Activating the DMAC
463
Starting DMA Transfer
464
Registers During DMA Transfer
464
Channel Priority
465
Ending DMA Transfer
466
Transfer End by Completion of Specified Total Number of Transfer Operations
466
Transfer End by Repeat Size End Interrupt
466
Transfer End by Interrupt on Extended Repeat Area Overflow
466
Interrupts
467
Low-Power Consumption Function
469
Usage Notes
470
DMA Transfer to External Devices
470
DMA Transfer to Peripheral Modules
470
Access to the Registers During DMA Transfer
470
DMA Transfer to Reserved Areas
470
Interrupt Request by the DMA Activation Source Flag Control Register (DMCSL) at the End of each Transfer
470
Setting of DMAC Activation Request Select Register of the Interrupt Controller (Icu.dmrsrm)
470
Suspending or Restarting DMA Activation
470
Data Transfer Controller (Dtca)
471
Overview
471
Register Descriptions
473
DTC Mode Register a (MRA)
473
DTC Mode Register B (MRB)
474
DTC Transfer Source Register (SAR)
475
DTC Transfer Destination Register (DAR)
475
DTC Transfer Count Register a (CRA)
476
DTC Transfer Count Register B (CRB)
477
DTC Control Register (DTCCR)
477
DTC Vector Base Register (DTCVBR)
478
DTC Address Mode Register (DTCADMOD)
478
DTC Module Start Register (DTCST)
479
DTC Status Register (DTCSTS)
480
Sources of Activation
481
Allocating Transfer Data and DTC Vector Table
481
Operation
483
Transfer Data Read Skip Function
485
Transfer Data Write-Back Skip Function
486
Normal Transfer Mode
486
Repeat Transfer Mode
487
Block Transfer Mode
489
Chain Transfer
490
Operation Timing
491
Execution Cycles of the DTC
494
DTC Bus Mastership Release Timing
494
DTC Setting Procedure
495
Examples of DTC Usage
496
Normal Transfer
496
Chain Transfer
496
Chain Transfer When Counter = 0
498
Interrupt Source
499
Low-Power Consumption Function
500
Usage Notes
500
Transfer Data Start Address/Source Address/Destination Address
500
Allocating Transfer Data
500
Setting the DTC Activation Enable Register (Icu.dtcern) of the Interrupt Controller
501
I/O Ports
502
Overview
502
I/O Port Configuration
505
Register Descriptions
509
Port Direction Register (PDR)
509
Port Output Data Register (PODR)
510
Port Input Data Register (PIDR)
511
Port Mode Register (PMR)
512
Open Drain Control Register 0 (ODR0)
513
Open Drain Control Register 1 (ODR1)
514
Pull-Up Control Register (PCR)
515
Driving Ability Control Register (DSCR)
516
Handling of Unused Pins
517
Usage Notes
517
Products with Fewer than 176 Pins
517
Multi-Function Pin Controller (MPC)
518
Overview
518
Register Descriptions
533
Write-Protect Register (PWPR)
533
P0N Pin Function Control Register (P0Npfs) (N = 0 to 3, 5, 7)
534
P1N Pin Function Control Registers (P1Npfs) (N = 0 to 7)
535
P2N Pin Function Control Registers (P2Npfs) (N = 0 to 7)
537
P3N Pin Function Control Registers (P3Npfs) (N = 0 to 4)
539
P4N Pin Function Control Registers (P4Npfs) (N = 0 to 7)
540
P5N Pin Function Control Registers (P5Npfs) (N = 0 to 2, 4 to 6)
541
P6N Pin Function Control Registers (P6Npfs) (N = 0, 1, 6 or 7)
542
P7N Pin Function Control Registers (P7Npfs) (N = 0, 3 to 7)
543
P8N Pin Function Control Registers (P8Npfs) (N = 0 to 3, 6, 7)
544
P9N Pin Function Control Registers (P9Npfs) (N = 0 to 3)
545
Pan Pin Function Select Registers (Panpfs) (N = 0 to 7)
546
Pbn Pin Function Control Registers (Pbnpfs) (N = 0 to 7)
548
Pcn Pin Function Control Register (Pcnpfs) (N = 0 to 7)
550
Pdn Pin Function Control Register (Pdnpfs) (N = 0 to 7)
552
Pen Pin Function Control Register (Penpfs) (N = 0 to 7)
553
Pfn Pin Function Select Register (Pfnpfs) (N = 0 to 2, 5)
555
PJ3 Pin Function Control Register (PJ3PFS)
556
Pkn Pin Function Control Register (Pknpfs) (N = 2 to 5)
557
CS Output Enable Register (PFCSE)
557
CS Output Pin Select Register 0 (PFCSS0)
558
CS Output Pin Select Register 1 (PFCSS1)
559
Address Output Enable Register 0 (PFAOE0)
560
Address Output Enable Register 1 (PFAOE1)
560
External Bus Control Register 0 (PFBCR0)
561
External Bus Control Register 1 (PFBCR1)
561
USB0 Control Register (PFUSB0)
562
How to Set the External Bus Interface
563
Usage Notes
566
Procedure for Specifying Input/Output Pin Function
566
Notes on MPC Register Setting
566
Notes on the Use of Analog Functions
567
Multi-Function Timer Pulse Unit 2 (Mtu2A)
568
Overview
568
Register Descriptions
573
Timer Control Register (TCR)
573
Timer Mode Register (TMDR)
576
Timer I/O Control Register (TIOR)
578
Timer Compare Match Clear Register (TCNTCMPCLR)
589
Timer Interrupt Enable Register (TIER)
590
Timer Status Register (TSR)
592
Timer Buffer Operation Transfer Mode Register (TBTM)
593
Timer Input Capture Control Register (TICCR)
594
Timer A/D Converter Start Request Control Register (TADCR)
595
Timer A/D Converter Start Request Cycle Set Registers a and B (TADCORA and TADCORB)
596
Timer A/D Converter Start Request Cycle Set Buffer Registers a and B (TADCOBRA and TADCOBRB)
596
Timer Counter (TCNT)
597
Timer General Register (TGR)
597
Timer Start Registers (TSTR)
598
Timer Synchronous Registers (TSYR)
599
Timer Read/Write Enable Registers (TRWER)
600
Timer Output Master Enable Registers (TOER)
601
Timer Output Control Registers 1 (TOCR1)
602
Timer Output Control Registers 2 (TOCR2)
604
Timer Output Level Buffer Registers (TOLBR)
606
Timer Gate Control Registers (TGCR)
607
Timer Subcounters (TCNTS)
608
Timer Dead Time Data Registers (TDDR)
608
Timer Cycle Data Registers (TCDR)
609
Timer Cycle Buffer Registers (TCBR)
609
Timer Interrupt Skipping Set Registers (TITCR)
609
Timer Interrupt Skipping Counters (TITCNT)
611
Timer Buffer Transfer Set Registers (TBTER)
612
Timer Dead Time Enable Registers (TDER)
613
Timer Waveform Control Registers (TWCR)
614
Noise Filter Control Registers (NFCR)
615
Bus Master Interface
617
Operation
617
Basic Functions
617
Synchronous Operation
622
Buffer Operation
624
Cascaded Operation
627
PWM Modes
632
Phase Counting Mode
636
Reset-Synchronized PWM Mode
642
Complementary PWM Mode
645
A/D Converter Start Request Delaying Function
673
External Pulse Width Measurement
676
Dead Time Compensation
677
Noise Filter
679
Interrupt Sources
680
Interrupt Sources and Priorities
680
DTC and DMAC Activation
681
A/D Converter Activation
681
Operation Timing
683
Input/Output Timing
683
Interrupt Signal Timing
688
Usage Notes
691
Module Clock Stop Mode Setting
691
Input Clock Restrictions
691
Note on Cycle Setting
691
Contention between TCNT Write and Clear Operations
692
Contention between TCNT Write and Increment Operations
692
Contention between TGR Write Operation and Compare Match
693
Contention between Buffer Register Write Operation and Compare Match
693
Contention between Buffer Register Write and TCNT Clear Operations
694
Contention between TGR Read Operation and Input Capture
694
Contention between TGR Write Operation and Input Capture
695
Contention between Buffer Register Write Operation and Input Capture
696
Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation
696
Counter Value When Stopped in Complementary PWM Mode
697
Buffer Operation Setting in Complementary PWM Mode
698
Buffer Operation and Compare Match Flags in Reset-Synchronized PWM Mode
698
Overflow Flags in Reset-Synchronized PWM Mode
699
Contention between Overflow/Underflow and Counter Clearing
700
Contention between TCNT Write Operation and Overflow/Underflow
700
Note on Transition from Normal Mode or PWM Mode 1 to Reset-Synchronized PWM Mode
700
Output Level in Complementary PWM Mode or Reset-Synchronized PWM Mode
701
Interrupts During Periods in the Module-Stop State
701
Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection
701
Notes When Complementary PWM Mode Output Protection Functions Are Not Used
701
Point for Caution Regarding MTU5.TCNT and MTU5.TGR Registers
701
Points for Caution to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode
702
Continuous Output of Interrupt Signal in Response to a Compare Match
704
MTU Output Pin Initialization
705
Operating Modes
705
Operation in Case of Re-Setting Due to Error During Operation
705
Overview of Pin Initialization Procedures and Mode Transitions in Case of Error During Operation
706
Port Output Enable 2 (Poe2A)
732
Overview
732
Register Descriptions
735
Input Level Control/Status Register 1 (ICSR1)
735
Output Level Control/Status Register 1 (OCSR1)
737
Input Level Control/Status Register 2 (ICSR2)
738
Software Port Output Enable Register (SPOER)
739
Port Output Enable Control Register 1 (POECR1)
740
Port Output Enable Control Register 2 (POECR2)
740
Input Level Control/Status Register 3 (ICSR3)
741
Operation
742
Input Level Detection Operation
744
Output-Level Compare Operation
745
High-Impedance Control Using Registers
745
High-Impedance Control on Detection of Stopped Oscillation
745
Release from the High-Impedance
745
Interrupts
746
Usage Notes
746
Transitions to Software Standby Mode or Deep Standby Mode
746
When POE Is Not Used
746
Specifying Pins Corresponding to the MTU
746
Overview
747
Register Descriptions
753
Timer Control Register (TCR)
753
Timer Mode Register (TMDR)
758
Timer I/O Control Register (TIORH, TIORL, TIOR)
759
Timer Interrupt Enable Register (TIER)
769
Timer Status Register (TSR)
770
Timer Counter (TCNT)
772
Timer General Register a (TGRA) Timer General Register B (TGRB) Timer General Register C (TGRC) Timer General Register D (TGRD)
773
Timer Start Register (TSTR)
774
Timer Synchronous Register (TSYR)
775
Noise Filter Control Register (NFCR)
776
Operation
778
Basic Functions
778
Synchronous Operation
783
Buffer Operation
785
Cascaded Operation
788
PWM Modes
790
Phase Counting Mode
795
Phase Counting Mode Application Example
800
Noise Filters
801
Interrupt Sources
802
DTC Activation
804
DMAC Activation
804
A/D Converter Activation
804
PPG Trigger
804
Operation Timing
805
Input/Output Timing
805
Interrupt Signal Timing
809
24.10 Usage Notes
811
Module-Stop Function Setting
811
Input Clock Restrictions
811
Caution on Cycle Setting
812
Conflict between Tpum.tcnt Write and Clear Operations
812
Conflict between Tpum.tcnt Write and Increment Operations
812
Conflict between Tpum.tgry Write and Compare Match
813
Conflict between Buffer Register Write and Compare Match
813
Conflict between Tpum.tgry Read and Input Capture
814
Conflict between Tpum.tgry Write and Input Capture
814
Conflict between Buffer Register Write and Input Capture
815
Conflict between Overflow/Underflow and Counter Clearing
815
Conflict between Tpum.tcnt Write and Overflow/Underflow
816
Multiplexing of I/O Pins
816
Continuous Output of Compare-Match Pulse Interrupt Signal
817
Continuous Output of Input-Capture Pulse Interrupt Signal
817
Continuous Output of Underflow Pulse Interrupt Signal
818
Programmable Pulse Generator (PPG)
819
Overview
819
Register Descriptions
822
PPG Trigger Select Register (PTRSLR)
822
Next Data Enable Registers H (NDERH) Next Data Enable Registers L (NDERL)
823
Output Data Registers H (PODRH) Output Data Registers L (PODRL)
825
Next Data Registers H (NDRH) Next Data Registers L (NDRL)
828
PPG Output Control Register (PCR)
832
PPG Output Mode Register (PMR)
834
Operation
837
Output Timing
838
Sample Setup Procedure for Normal Pulse Output
839
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
841
Non-Overlapping Pulse Output
842
Sample Setup Procedure for Non-Overlapping Pulse Output
843
Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output)
845
Inverted Pulse Output
847
Pulse Output Triggered by Input Capture
848
Usage Note
848
Module-Stop Function Setting
848
Bit Timer (TMR)
849
Overview
849
Register Descriptions
853
Timer Counter (TCNT)
854
Time Constant Register a (TCORA)
854
Time Constant Register B (TCORB)
855
Timer Control Register (TCR)
855
Timer Counter Control Register (TCCR)
856
Timer Control/Status Register (TCSR)
858
Operation
860
Pulse Output
860
Reset Input
860
Operation Timing
861
TCNT Count Timing
861
Timing of Interrupt Flag Signal Output on a Compare Match
862
Timing of Timer Output at Compare Match
863
Timing of Counter Clear by Compare Match
863
Timing of the External Reset for TCNT
864
Timing of Interrupt Signal Output on an Overflow
865
Operation with Cascaded Connection
865
16-Bit Count Mode
865
Compare Match Count Mode
865
Interrupt Sources
866
Interrupt Sources and DTC Activation
866
A/D Converter Activation
866
Usage Notes
867
Module-Stop State Setting
867
Notes on Setting Cycle
867
Conflict between TCNT Write and Counter Clear
867
Conflict between TCNT Write and Increment
868
Conflict between TCORA or TCORB Write and Compare Match
868
Conflict between Compare Matches a and B
869
Switching of Frequency Dividing Clocks and TCNT Operation
869
Clock Source Setting with Cascaded Connection
871
Continuous Output of Compare Match Interrupt Signal
871
Compare Match Timer (CMT)
872
Overview
872
Register Descriptions
873
Compare Match Timer Start Register 0 (CMSTR0)
873
Compare Match Timer Start Register 1 (CMSTR1)
873
Compare Match Timer Control Register (CMCR)
874
Compare Match Timer Counter (CMCNT)
875
Compare Match Timer Constant Register (CMCOR)
875
Operation
876
Periodic Count Operation
876
CMCNT Count Timing
876
Interrupts
877
Interrupt Sources
877
Timing of Compare Match Interrupt Generation
877
Usage Notes
878
Setting the Module-Stop Function
878
Conflict between Write and Compare-Match Processes of CMCNT
878
Conflict between Write and Count-Up Processes of CMCNT
878
Realtime Clock (Rtca)
879
Overview
879
Register Descriptions
881
64-Hz Counter (R64CNT)
881
Second Counter (RSECCNT)
882
Minute Counter (RMINCNT)
882
Hour Counter (RHRCNT)
883
Day-Of-Week Counter (RWKCNT)
884
Date Counter (RDAYCNT)
885
Month Counter (RMONCNT)
885
Year Counter (RYRCNT)
886
Second Alarm Register (RSECAR)
886
Minute Alarm Register (RMINAR)
887
Hour Alarm Register (RHRAR)
888
Day-Of-Week Alarm Register (RWKAR)
889
Date Alarm Register (RDAYAR)
890
Month Alarm Register (RMONAR)
891
Year Alarm Register (RYRAR)
892
Year Alarm Enable Register (RYRAREN)
892
RTC Control Register 1 (RCR1)
893
RTC Control Register 2 (RCR2)
894
RTC Control Register 3 (RCR3)
896
RTC Control Register 4 (RCR4)
897
Frequency Register H/L (RFRH/L)
898
Time Error Adjustment Register (RADJ)
899
Time Capture Control Register y (Rtccry) (y = 0 to 2)
900
Second Capture Register y (Rseccpy) (y = 0 to 2)
901
Minute Capture Register y (Rmincpy) (y = 0 to 2)
902
Hour Capture Register y (Rhrcpy) (y = 0 to 2)
902
Date Capture Register y (Rdaycpy) (y = 0 to 2)
903
Month Capture Register y (Rmoncpy) (y = 0 to 2)
903
Operation
904
Outline of Initial Settings of Registers after Power-On
904
Clock Setting Procedure
905
Setting the Time
906
30-Second Adjustment
907
Reading 64-Hz Counter and Time
908
Alarm Function
909
Procedure for Disabling Alarm Interrupt
910
Time-Error Adjustment Function
910
Automatic Adjustment
910
Adjustment by Software
911
Procedure for Changing the Mode of Adjustment
911
Procedure for Stopping Adjustment
911
Capturing the Time
912
Interrupt Sources
913
Usage Notes
914
Register Writing During Counting
914
Use of Periodic Interrupts
914
RTCOUT (1-Hz) Output
915
Transitions to Low Power Consumption Modes after Setting Registers
915
Points for Caution When Writing to and Reading from Registers
915
Initialization Procedure When the Realtime Clock Is Not to be Used
916
Watchdog Timer (WDTA)
917
Overview
917
Register Descriptions
919
WDT Refresh Register (WDTRR)
919
WDT Control Register (WDTCR)
920
WDT Status Register (WDTSR)
923
WDT Reset Control Register (WDTRCR)
924
Option Function Select Register 0 (OFS0)
924
Operation
925
Count Operation in each Start Mode
925
Register Start Mode
925
Auto-Start Mode
926
Control over Writing to the WDTCR and WDTRCR Registers
927
Refresh Operation
928
Status Flags
929
Reset Output
930
Interrupt Source
930
Reading the Down-Counter Value
930
Correspondence between Option Function Select Register 0 (OFS0) and WDT Registers
931
Independent Watchdog Timer (Iwdta)
932
Overview
932
Register Descriptions
934
IWDT Refresh Register (IWDTRR)
934
IWDT Control Register (IWDTCR)
935
IWDT Status Register (IWDTSR)
938
IWDT Reset Control Register (IWDTRCR)
939
IWDT Count Stop Control Register (IWDTCSTPR)
939
Option Function Select Register 0 (OFS0)
940
Operation
940
Count Operation in each Start Mode
940
Register Start Mode
940
Auto-Start Mode
941
Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers
942
Refresh Operation
943
Status Flags
945
Interrupt Source
946
Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers
947
Overview
948
Register Descriptions
950
System Configuration Status Register 0 (SYSSTS0)
951
Device State Control Register 0 (DVSTCTR0)
952
D0FIFO Port Register (D0FIFO D1FIFO Port Register (D1FIFO)
953
D0FIFO Port Select Register (D0FIFOSEL D1FIFO Port Select Register (D1FIFOSEL)
955
D0FIFO Port Control Register (D0FIFOCTR D1FIFO Port Control Register (D1FIFOCTR)
959
Interrupt Enable Register 0 (INTENB0)
961
BRDY Interrupt Enable Register (BRDYENB)
962
NRDY Interrupt Enable Register (NRDYENB)
963
BEMP Interrupt Enable Register (BEMPENB)
964
SOF Output Configuration Register (SOFCFG)
965
BRDY Interrupt Status Register (BRDYSTS)
968
NRDY Interrupt Status Register (NRDYSTS)
969
BEMP Interrupt Status Register (BEMPSTS)
970
Frame Number Register (FRMNUM)
971
Device State Changing Register (DVCHGR)
972
USB Request Type Register (USBREQ)
973
USB Request Index Register (USBINDX)
974
DCP Maximum Packet Size Register (DCPMAXP)
975
DCP Control Register (DCPCTR)
976
Pipe Window Select Register (PIPESEL)
978
Pipe Configuration Register (PIPECFG)
979
Pipe Maximum Packet Size Register (PIPEMAXP)
981
Pipe Cycle Control Register (PIPEPERI)
982
Pipen Control Registers (Pipenctr) (N = 1 to 9)
983
Pipen Transaction Counter Enable Registers (Pipentre) (N = 1 to 5)
989
Pipen Transaction Counter Registers (Pipentrn) (N = 1 to 5)
990
Deep Standby USB Transceiver Control/Pin Monitor Register (DPUSR0R)
991
Deep Standby USB Suspend/Resume Interrupt Register (DPUSR1R)
992
Operation
993
Canceling Deep Software Standby Mode by a USB Suspend/Resume Interrupt
995
Interrupt Sources
998
Interrupt Descriptions
1000
NRDY Interrupt
1003
BEMP Interrupt
1005
Device State Transition Interrupt
1007
Control Transfer Stage Transition Interrupt
1008
Frame Update Interrupt
1009
Pipe Control Register Switching Procedures
1010
Endpoint Number
1011
Data PID Sequence Bit
1012
Null Auto Response Mode
1013
FIFO Buffer Memory
1014
FIFO Port Functions
1015
DMA Transfers (D0FIFO and D1FIFO Ports)
1016
Control Transfers (DCP)
1017
Bulk Transfers (PIPE1 to PIPE5)
1018
Isochronous Transfers (PIPE1 and PIPE2)
1019
Data-Pid
1020
SOF Interpolation Function
1025
Overview
1026
Register Descriptions
1035
Transmit Shift Register (TSR)
1036
Serial Control Register (SCR)
1039
Serial Status Register (SSR)
1043
Smart Card Mode Register (SCMR)
1047
Bit Rate Register (BRR)
1048
Serial Extended Mode Register (SEMR)
1056
Noise Filter Setting Register (SNFR)
1058
SPI Mode Register (SPMR)
1064
Extended Serial Module Enable Register (ESMER)
1065
Control Register 0 (CR0)
1066
Control Register 1 (CR1)
1067
Control Register 2 (CR2)
1068
Control Register 3 (CR3)
1069
Interrupt Control Register (ICR)
1070
Status Register (STR)
1071
Status Clear Register (STCR)
1072
Control Field 0 Compare Enable Register (CF0CR)
1073
Secondary Control Field 1 Data Register (SCF1DR)
1074
Timer Control Register (TCR)
1075
Timer Prescaler Register (TPRE)
1076
Operation in Asynchronous Mode
1077
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
1079
Clock
1080
SCI Initialization (Asynchronous Mode)
1081
Serial Data Transmission (Asynchronous Mode)
1082
Serial Data Reception (Asynchronous Mode)
1084
Multi-Processor Communications Function
1088
Multi-Processor Serial Data Transmission
1089
Multi-Processor Serial Data Reception
1090
Operation in Clock Synchronous Mode
1093
SCI Initialization (Clock Synchronous Mode)
1094
Serial Data Transmission (Clock Synchronous Mode)
1095
Serial Data Reception (Clock Synchronous Mode)
1096
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
1099
Operation in Smart Card Interface Mode
1100
Block Transfer Mode
1102
Initialization of the SCI (Smart Card Interface Mode)
1103
Serial Data Transmission (Except in Block Transfer Mode)
1104
Serial Data Reception (Except in Block Transfer Mode)
1107
Clock Output Control
1108
Generation of Start, Restart, and Stop Conditions
1111
Clock Synchronization
1112
SSDA Output Delay
1113
Operation in Simple SPI Mode
1119
States of Pins in Master and Slave Modes
1120
Relationship between Clock and Transmit/Receive Data
1121
Transmission and Reception of Serial Data (Simple SPI Mode)
1122
Transmitting a Start Frame
1123
Receiving a Start Frame
1126
Priority Interrupt Bit
1131
Detection of Bus Collisions
1132
Digital Filter for Input on the RXDX Pin
1133
Bit-Rate Measurement
1134
Selectable Timing for Sampling Data Received through RXDX12
1135
Noise Cancellation Function
1137
Interrupt Sources
1138
Interrupts in Smart Card Interface Mode
1139
Interrupts from the Extended Serial Mode Control Section
1141
Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
1142
External Clock Input in Clock Synchronous Mode
1145
Limitation 2 on Usage of the Extended Serial Mode Control Section
1146
Overview
1147
Register Descriptions
1150
Slave Address Register Ly (Sarly) (y = 0 to 2)
1170
Slave Address Register Uy (Saruy) (y = 0 to 2)
1171
Operation
1176
Initial Settings
1177
Master Transmit Operation
1178
Master Receive Operation
1181
Slave Transmit Operation
1185
Slave Receive Operation
1188
SCL Synchronization Circuit
1190
Facility for Delaying SDA Output
1191
Digital Noise-Filter Circuits
1192
Address Match Detection
1193
Detection of the General Call Address
1195
Host Address Detection
1196
Automatically Low-Hold Function for SCL
1197
NACK Reception Transfer Suspension Function
1198
Function to Prevent Failure to Receive Data
1199
Arbitration-Lost Detection Functions
1201
Function to Detect Loss of Arbitration During NACK Transmission (NALE Bit)
1203
Slave Arbitration-Lost Detection (SALE Bit)
1204
Start Condition/Restart Condition/Stop Condition Issuing Function
1205
Issuing a Stop Condition
1206
Timeout Function
1207
Extra SCL Clock Cycle Output Function
1208
RIIC Reset and Internal Reset
1209
Packet Error Code (PEC)
1211
Interrupt Request
1212
Reset States
1213
Usage Notes
1214
Overview
1215
Register Descriptions
1217
Bit Configuration Register (BCR)
1221
Mask Register K (Mkrk) (K = 0 to 7)
1223
FIFO Received ID Compare Registers 0 and 1 (FIDCR0 and FIDCR1)
1224
Mask Invalid Register (MKIVLR)
1225
Mailbox Register J (Mbj) (J = 0 to 31)
1226
Mailbox Interrupt Enable Register (MIER)
1230
Message Control Register J (Mctlj) (J = 0 to 31)
1231
Receive FIFO Control Register (RFCR)
1234
Receive FIFO Pointer Control Register (RFPCR)
1237
Transmit FIFO Pointer Control Register (TFPCR)
1239
Status Register (STR)
1240
Mailbox Search Mode Register (MSMR)
1242
Mailbox Search Status Register (MSSR)
1243
Channel Search Support Register (CSSR)
1244
Acceptance Filter Support Register (AFSR)
1245
Error Interrupt Enable Register (EIER)
1246
Error Interrupt Factor Judge Register (EIFR)
1247
Receive Error Count Register (RECR)
1249
Transmit Error Count Register (TECR)
1250
Time Stamp Register (TSR)
1251
Test Control Register (TCR)
1252
Operating Mode
1254
CAN Halt Mode
1255
CAN Sleep Mode
1256
CAN Operation Mode (Excluding Bus-Off State)
1257
CAN Operation Mode (Bus-Off State)
1258
CAN Communication Speed Setting
1259
Bit Rate
1260
Mailbox and Mask Register Structure
1261
Acceptance Filtering and Masking Functions
1262
Reception and Transmission
1264
Reception
1265
Transmission
1267
CAN Interrupt
1268
Overview
1269
Register Descriptions
1273
RSPI Slave Select Polarity Register (SSLP)
1274
RSPI Pin Control Register (SPPCR)
1275
RSPI Status Register (SPSR)
1276
RSPI Data Register (SPDR)
1278
RSPI Sequence Control Register (SPSCR)
1281
RSPI Sequence Status Register (SPSSR)
1282
RSPI Bit Rate Register (SPBR)
1283
RSPI Data Control Register (SPDCR)
1284
RSPI Clock Delay Register (SPCKD)
1285
RSPI Slave Select Negation Delay Register (SSLND)
1286
RSPI Control Register 2 (SPCR2)
1287
RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7)
1288
Operation
1291
Controlling RSPI Pins
1292
RSPI System Configuration Examples
1293
Single Master/Single Slave (with this LSI Acting as Slave)
1294
Single Master/Multi-Slave (with this LSI Acting as Master)
1295
Single Master/Multi-Slave (with this LSI Acting as Slave)
1296
Multi-Master/Multi-Slave (with this LSI Acting as Master)
1297
Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation with this LSI Acting as Master)
1298
Data Format
1299
When Parity Is Disabled (SPCR2.SPPE = 0)
1300
When Parity Is Enabled (SPCR2.SPPE = 1)
1304
Transfer Format
1308
Cpha = 1
1309
Communications Operating Mode
1310
Transmit Operations Only (SPCR.TXMD = 1)
1311
Transmit Buffer Empty/Receive Buffer Full Interrupts
1312
Error Detection
1314
Overrun Error
1315
Parity Error
1316
Mode Fault Error
1317
Initializing RSPI
1318
SPI Operation
1319
Slave Mode Operation
1329
Clock Synchronous Operation
1333
Slave Mode Operation
1337
Loopback Mode
1339
Self-Diagnosis of Parity Bit Function
1340
Interrupt Sources
1341
Usage Note
1342
Overview
1343
Transfer Data (Data Field Contents)
1344
Register Descriptions
1349
Iebus Command Register (IECMR)
1350
Iebus Master Control Register (IEMCR)
1351
Iebus Master Unit Address Register 1 (IEAR1)
1352
Iebus Slave Address Setting Register 1 (IESA1)
1353
Iebus Transmit Message Length Register (IETBFL)
1354
Iebus Reception Master Address Register 2 (IEMA2)
1355
Iebus Receive Message Length Register (IERBFL)
1356
Iebus General Flag Register (IEFLG)
1357
Iebus Transmit Status Register (IETSR)
1359
Iebus Transmit Interrupt Enable Register (IEIET)
1361
Iebus Receive Status Register (IERSR)
1362
Iebus Receive Interrupt Enable Register (IEIER)
1365
Iebus Clock Selection Register (IECKSR)
1366
Iebus Transmit Data Buffer Registers 001 to 032 (IETB001 to IETB032)
1368
Data Format
1369
Reception Format
1370
Control Flows
1371
Master Transmission
1372
Slave Reception
1373
Master Reception
1374
Slave Transmission
1375
Operation Timing
1376
Slave Reception
1377
Master Reception
1378
Slave Transmission
1379
Interrupt Sources
1380
Usage Notes
1381
Notes on Operation When Message Length Is Greater than Maximum Number of Transfer Bytes
1383
Setting for the Module-Stop State
1384
Overview
1385
Register Descriptions
1386
CRC Data Output Register (CRCDOR)
1387
Operation
1388
Usage Notes
1391
Overview
1392
Register Descriptions
1395
A/D Channel Select Register 0 (ADANS0)
1397
A/D-Converted Value Addition Mode Select Register 0 (ADADS0)
1398
A/D-Converted Value Addition Count Select Register (ADADC)
1399
A/D Control Extended Register (ADCER)
1400
A/D Start Trigger Select Register (ADSTRGR)
1401
A/D-Converted Extended Input Control Register (ADEXICR)
1402
A/D Temperature Sensor Data Register (ADTSDR)
1403
A/D Internal Reference Voltage Data Register (ADOCDR)
1404
A/D Data Register y (Addry) (y = 0 to 20)
1405
A/D Sampling State Register 01 (ADSSTR01)
1406
A/D Sampling State Register 23 (ADSSTR23)
1407
Operation
1408
A/D Conversion When Selecting Temperature Sensor Output/Internal Reference Voltage
1409
Continuous Scan Mode
1410
Analog Input Scan Time
1411
Usage Example of Addry Register Automatic Clearing Function
1412
Starting A/D Conversion with Synchronous Trigger from Peripheral Modules
1413
Starting A/D Conversion Using MTU TRG0AN_0 and TRG0BN_0
1414
Starting A/D Conversion Using MTU TRG0EN_0 and TRG0FN_0
1416
Starting A/D Conversion Using MTU TRG4ABN_0 and TPU TRG4ABN_1
1417
Starting A/D Conversion Using TMR TMTRG0AN_0 and TMTRG0AN_1
1418
Usage Notes
1419
Analog Power Supply Pin Setting Range
1420
Notes on Noise Countermeasures
1421
Overview
1422
Register Descriptions
1425
A/D Control/Status Register (ADCSR)
1426
A/D Control Register (ADCR)
1427
A/D Control Register 2 (ADCR2)
1428
A/D Self-Diagnostic Register (ADDIAGR)
1429
Operation
1430
Single Channel Mode
1431
Scan Mode
1432
Single Scan Mode
1433
Extended Analog Input
1434
Usage of ANEX1
1435
Input Sampling and A/D Conversion Time
1436
Starting 10-Bit A/D Conversion with Asynchronous Trigger
1438
Using Synchronous Triggers from Peripheral Modules to Start A/D Conversion
1439
Starting A/D Conversion Using MTU TRG4ABN_0 and TPU TRG4ABN_1
1441
Starting A/D Conversion Using TMR TMTRG0AN_0
1442
Interrupt Sources
1443
Usage Notes
1445
Permissible Signal Source Impedance
1446
Analog Power Supply Pin Setting Range
1447
Notes on Noise Countermeasures
1448
Realizing High-Speed Conversion
1449
Overview
1450
Register Descriptions
1451
D/A Control Register (DACR)
1452
Dadrm Format Select Register (DADPR)
1453
D/A A/D Synchronous Start Control Register (DAADSCR)
1454
Operation
1455
Measure against Interference between D/A and A/D Conversion
1456
Usage Notes
1457
Overview
1458
Register Descriptions
1459
Using the Temperature Sensor
1460
Setting of 12-Bit A/D Converter
1461
Procedure for Using the Temperature Sensor
1462
Timing of A/D Conversion of Temperature Sensor Output
1463
Overview
1464
Overview
1465
Configuration of the ROM Area
1467
Block Configuration of the ROM
1468
Configuration of the E2 Dataflash Area
1470
Register Descriptions
1471
Flash Mode Register (FMODR)
1472
Flash Access Status Register (FASTAT)
1473
Flash Access Error Interrupt Enable Register (FAEINT)
1476
Flash Ready Interrupt Enable Register (FRDYIE)
1477
E2 Dataflash Read Enable Register 0 (DFLRE0)
1478
E2 Dataflash Read Enable Register 1 (DFLRE1)
1479
E2 Dataflash P/E Enable Register 0 (DFLWE0)
1480
E2 Dataflash P/E Enable Register 1 (DFLWE1)
1481
FCU RAM Enable Register (FCURAME)
1482
Flash Status Register 0 (FSTATR0)
1483
Flash Status Register 1 (FSTATR1)
1485
Flash P/E Mode Entry Register (FENTRYR)
1486
Flash Protection Register (FPROTR)
1488
Flash Reset Register (FRESETR)
1489
FCU Command Register (FCMDR)
1490
FCU Processing Switching Register (FCPSR)
1491
Flash P/E Status Register (FPESTAT)
1492
Peripheral Clock Notification Register (PCKAR)
1493
Operating Modes Associated with Flash Memory
1494
FCU Modes
1495
ROM Read Modes
1496
E2 Dataflash P/E Modes
1497
FCU Commands
1498
Connections between FCU Modes and Commands
1500
FCU Command Usage
1501
Programming and Erasure Procedures
1505
Suspension and Resumption
1513
Processing to Check for Errors and to Confirm the Value of the FRDY Bit
1516
Suspending Operation
1518
Suspension During Erasure (Suspension Priority Mode)
1519
Suspension During Erasure (Erasure Priority Mode)
1520
Command-Locked State
1521
User Boot Mode
1523
State Transitions in Boot Mode
1524
Automatic Adjustment of the Bit Rate
1526
ID Code Protection (Boot Mode)
1527
UB Code a
1528
Inquiry/Selection Command Wait
1529
ID Code Wait State
1540
Programming/Erasure Command Wait
1541
USB Boot Mode
1549
State Transitions
1550
Notes on Program Execution in USB Boot Mode
1551
ROM Code Protection
1552
Usage Notes (Common to the ROM/E2 Dataflash Memory)
1553
Usage Notes (for E2 Dataflash)
1554
Features
1555
Register Descriptions
1556
Instruction Register (JTIR)
1557
Bypass Register (JTBPR)
1558
Operations
1568
List of Commands
1569
Usage Notes
1570
Absolute Maximum Ratings
1572
DC Characteristics
1573
AC Characteristics
1577
Reset Timing
1578
Clock Timing
1579
Timing of Recovery from Low Power Consumption Modes
1583
Control Signal Timing
1584
Bus Timing
1585
Timing of On-Chip Peripheral Modules
1591
USB Characteristics
1601
A/D Conversion Characteristics
1602
D/A Conversion Characteristics
1604
Power-On Reset Circuit and Voltage Detection Circuit Characteristics
1605
Oscillation Stop Detection Timing
1608
ROM (Flash Memory for Code Storage) Characteristics
1609
Appendix 1. Port States in each Processing Mode
1612
Appendix 2. Package Dimensions
1615
Revision History
1623

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