Yamaha SB168-ES Service Manual page 134

H G
BLOCK DIAGRAM 003 (SB168-ES)
ES
28CA1-2001041659-3
F E
see page 4
DM
M128_FS(OUT),
M256_FS(OUT),
MFS_FS(OUT)
SO WCLK(IN) M256_FS(IN)
CN603 (40P)
CN002 (40P)
M128FS_IN,M256FS_IN
36―38 58 59
CPLD
IC002
4
(100P)
SEL
SEL /
Frequency dividing
Synchronous
84,85 87 88 89
6
PLL
(CLOCK
GENERATOR)
2
IC003 (8P)
BCLK_IN LRCK_OUT MCLK_OUT
SI LRCK_IN
MCLK_IN
Ether Sound Module
(AVDM-ES100Y1)
D C
DB
AB
[0―7]
/CS /RD,/WR [1―8] /RES_ES TX,RX
SI
CN602 (40P)
CN001 (40P)
4
+3.3D
41―44, 29 30,31 14―17, 3―6, 13,25,33, 2
47―50 19―22 8―11 40,45,63,
75,83,90,
95
Address Decoder
+
X200
CPU I/F
14.7456MHz
circuit
85 64―67 97―100 78―81 91―94
4 4
4
4
MUTE SO
LED SPI /RESET_IN UART_RX UART_CLK
UART_TX
B
SB-168-ES
LD001―004
RX
(Green 4pcs.)
IN
TX
LD [1―4]
RX
OUT
+3.3PLL +3.3D
TX
T001
Pulse
TRDA[0]±
Trans
IN
TRDA[1]±
H1102
JK003
Ether
Sound
T002
Pulse
TRDB[0]±
Trans
OUT
TRDB[1]±
H1102
JK004
BLOCK DIAGRAM 003 (SB168-ES)
A
1
2
3
4
5
5
6