Port Allocations - Icom IC-F2610 Service Manual

4-5 PORT ALLOCATIONS

CPU (IC20)
Pin Port
number name
Outputs the PTT control signal.
20 PTTO
Low : While transmitting
Input port for the PTT control signal
21 PTTI
from PTTO port.
Input port for the AF amplifier ON sig-
22 AFON
nal from an optional unit.
Outputs busy signal for an optional
24 BUSY
unit.
Input port for the power switch.
25 POSW
Low : While power switch is pushed
Input port for microphone audio mute
30 MMUT
control signal from an optional unit.
Input port for receive audio mute con-
31 RMUT
trol signal from an optional unit.
Input port for noise signals (pulse-
32 NOIS
type) for noise squelch operation.
38 AFV Input port for the volume control.
Input port for receiving signal strength
40 RSSI
level detection.
43 CDEC Input port for CTCSS/DTCS decoding.
Output ports for CTCSS/DTCS sig-
44 CENC
nals.
Output ports for EEPROM select sig-
ECS2, nals.
47, 48
ECS1 ECS1: For internal EEPROM (IC27)
ECS2: For optional EEPROM
49 ECK Outputs clock signal for EEPROMs.
Input port for serial signal from
50 ESI
EEPROMs.
51 ESO Outputs serial signal for EEPROMs.
53 BEEP Outputs beep audio signals.
Outputs mic. audio mute control signal
to the audio switch (IC25).
55 MCON
High : While DTMF signals are being
Outputs the AF mute switch (Q6) con-
56 AMUT trol signal.
High : While squelched, etc.
Outputs N/W switch control signals.
25 NWC
High : While wide is selected
Outputs high-pass filter's characteris-
57 HFSW tics select signal.
High : During CTCSS operation
Outputs mic. audio select signal to the
audio switch (IC25).
60 PA
High : While "Public-address" func-
Outputs MT8V regulator circuit (Q38,
62 TMUT D27) control signal.
High : While transmit is muted.
Description
transmitted, etc.
tion is ON
Pin Port
number name
64 DSTB
65 DDA
66 DCK
67 PSTB
68 PDA
69 PCK
72 UNLK
73 PLLT
75 VTX
76 VRX
77 PWON
78 PASP
79 SP
80 DIM
DTR1–
DTR4,
82–89
DTC4–
DTC1
93 HORN
99 SIFT
4 - 5
Description
Outputs strobe signals for the level
controller. (IC5)
Outputs data signal for the level con-
troller (IC5).
Outputs clock signal for the level con-
troller (IC5).
Outputs strobe signals for the PLL IC
(IC12).
Outputs data signal for the PLL IC
(IC12).
Outputs clock signal for the PLL IC
(IC12).
Input port for the PLL unlock signal.
High : During unlock
Outputs PLL accelerator control signal.
High : While scanning, etc.
Outputs the T8V regulator circuit (Q38,
D28) control signal.
Low : While transmitting
Outputs the R8V regulator circuit
(Q36, D27) control signal.
Low : While receiving
Outputs the power control circuit (Q12)
control signal.
High : During power ON
Outputs "Public-address" mute signal.
High : While PA and Ext. SP func-
tions are not used
Outputs the mute switch (Q7) control
signal (incl. beep).
High : While squelched, etc.
Input port for an external LCD back-
light brightness control signal.
Low : LCD backlight is dimmed
Outputs DTMF audio signals.
Outputs high level control signal for the
pre-set time to the connected external
unit when matched 2- or 5-tone code is
received.
Outputs CPU clock shift signal.